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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:43 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uyfKmJKN+HHIFlZerm3nnhi5/Li0h9VOpTobmaxIUWg=; b=Q/DcIRRE43d+1GAq2tLwDUPWw+HMrsrxKDb7VaKi0eQr1xYQT7J51cXQvxidDCkMEw R02JjxbbFhJfi5mOBc1iQyJOExv9bO3/O5kXFeUQjqIJldQPczXgT5XtQzlTZUaezqeJ AuitV9GRCzHkkzqjay6ZKjgQZ10tw+C+53Iwkmj4T2hh202BJ9Dw/uz9cyE4PLwRKWgZ 5B3KzpVR7nxa6dJakBG2wwwx8AHFSL/l2yKwZwBQO+Xy4CP6W+TGfDbsWs7r9cZ5vv3I k0XrZxt/GH/OZeUIMiF3UYBC/HJRuoZDiUTvA4s7bpC1LRAD54wZ6Lkp4RWh0OSZtMKr fxXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uyfKmJKN+HHIFlZerm3nnhi5/Li0h9VOpTobmaxIUWg=; b=EPiuVMAw+ZmDeIN+zH2hvViM09Z0IDKG9++ZPhJ+i96OwojPsymBw137ITUFWHGGIS NZapoM540O7JkK+bMxuqZ4LhlI+GxqZZ5hHuK5VUajrxhVrVu2NvEM8fhHVjDyIx7sML 4TDvyt9ppqIfs2KueCBHQIgY3w2PrcZSVq2nz6oH4sEc3CTvsJ65C1sCbangIpE9dJ5I xOTidjB2Ue9mrC1MJokxKw/EX9wqGSO/MmSvBDIYsCQETon580KAYErfqtmOUUTJv+9o MUklTK0YaTm5obzdG5/LxvpF5c1NX22cMIwz14OyhXG0uHV8wgM9YM77t5Zz1Zh5v8l3 3m1Q== X-Gm-Message-State: APt69E2GkMyZRwUjXBYWXQ5e29cgtWsQUYkJETed8/wdc5FipoyHsUVO OQ8AvLyPi0LswTuHk90S4Ilqm7hYB4Y= X-Google-Smtp-Source: ADUXVKKlvN23okKOiSjxaQhw8jIUcfsoa3EALLLCxmKGof7H2Iyb4mH1szzjz9Bl5VoMWYPGpgH8xw== X-Received: by 2002:a2e:9b91:: with SMTP id z17-v6mr6225461lji.121.1529266363875; Sun, 17 Jun 2018 13:12:43 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:54 +0200 Message-Id: <1529266325-18371-15-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 14/25] Marvell/Library: ComPhyLib: Get AHCI data with MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" ComPhy Library used to get Armada7k8k AHCI/SDMMC/XHCI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this library. This patch updates the driver to get AHCI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 - Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 6 +- Silicon/Marvell/Include/Library/MvHwDescLib.h | 60 --= ------------------ Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 4 ++ Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 50 ++= ++++++-------- 5 files changed, 35 insertions(+), 86 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index f2c173c..e888566 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -47,7 +47,6 @@ =20 [LibraryClasses] ArmLib - ComPhyLib DebugLib MemoryAllocationLib MppLib diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyLib.inf index ce0af54..f36c701 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -52,12 +52,16 @@ PcdLib SampleAtResetLib IoLib + UefiBootServicesTableLib =20 [Sources.common] ComPhyLib.c ComPhyCp110.c ComPhyMux.c =20 +[Protocols] + gMarvellBoardDescProtocolGuid ## CONSUMES + [FixedPcd] gMarvellTokenSpaceGuid.PcdComPhyDevices =20 @@ -80,5 +84,3 @@ gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags - - gMarvellTokenSpaceGuid.PcdPciEAhci diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 5fd514c..9f383f4 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -36,7 +36,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define __MVHWDESCLIB_H__ =20 #include -#include =20 // // Helper macros @@ -80,31 +79,6 @@ typedef struct { } MVHW_MDIO_DESC; =20 // -// NonDiscoverable devices description template definition -// -#define MVHW_MAX_XHCI_DEVS 4 -#define MVHW_MAX_AHCI_DEVS 4 -#define MVHW_MAX_SDHCI_DEVS 4 - -typedef struct { - // XHCI - UINT8 XhciDevCount; - UINTN XhciBaseAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN XhciMemSize[MVHW_MAX_XHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType[MVHW_MAX_XHCI_DEVS]; - // AHCI - UINT8 AhciDevCount; - UINTN AhciBaseAddresses[MVHW_MAX_AHCI_DEVS]; - UINTN AhciMemSize[MVHW_MAX_AHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType[MVHW_MAX_AHCI_DEVS]; - // SDHCI - UINT8 SdhciDevCount; - UINTN SdhciBaseAddresses[MVHW_MAX_SDHCI_DEVS]; - UINTN SdhciMemSize[MVHW_MAX_SDHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE SdhciDmaType[MVHW_MAX_SDHCI_DEVS]; -} MVHW_NONDISCOVERABLE_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -155,38 +129,4 @@ MVHW_MDIO_DESC mA7k8kMdioDescTemplate =3D {\ { MVHW_CP0_MDIO_BASE, MVHW_CP1_MDIO_BASE }\ } =20 -// -// Platform description of NonDiscoverable devices -// -#define MVHW_CP0_XHCI0_BASE 0xF2500000 -#define MVHW_CP0_XHCI1_BASE 0xF2510000 -#define MVHW_CP1_XHCI0_BASE 0xF4500000 -#define MVHW_CP1_XHCI1_BASE 0xF4510000 - -#define MVHW_CP0_AHCI0_BASE 0xF2540000 -#define MVHW_CP0_AHCI0_ID 0 -#define MVHW_CP1_AHCI0_BASE 0xF4540000 -#define MVHW_CP1_AHCI0_ID 1 - -#define MVHW_AP0_SDHCI0_BASE 0xF06E0000 -#define MVHW_CP0_SDHCI0_BASE 0xF2780000 - -#define DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE \ -STATIC \ -MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTemplate =3D {\ - 4, /* XHCI */\ - { MVHW_CP0_XHCI0_BASE, MVHW_CP0_XHCI1_BASE, MVHW_CP1_XHCI0_BASE, MVHW_CP= 1_XHCI1_BASE },\ - { SIZE_16KB, SIZE_16KB, SIZE_16KB, SIZE_16KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent,\ - NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent },\ - 2, /* AHCI */\ - { MVHW_CP0_AHCI0_BASE, MVHW_CP1_AHCI0_BASE },\ - { SIZE_8KB, SIZE_8KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent },\ - 2, /* SDHCI */\ - { MVHW_AP0_SDHCI0_BASE, MVHW_CP0_SDHCI0_BASE },\ - { SIZE_1KB, SIZE_1KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvel= l/Library/ComPhyLib/ComPhyLib.h index c675d74..090116d 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -35,6 +35,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __COMPHY_H__ #define __COMPHY_H__ =20 +#include #include #include #include @@ -43,6 +44,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include +#include + +#include =20 #define MAX_LANE_OPTIONS 10 =20 diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyCp110.c index 09994ca..5e0ebf6 100755 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -33,7 +33,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. **************************************************************************= *****/ =20 #include "ComPhyLib.h" -#include #include =20 #define SD_LANE_ADDR_WIDTH 0x1000 @@ -46,8 +45,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CP110_PCIE_REF_CLK_TYPE0 0 #define CP110_PCIE_REF_CLK_TYPE12 1 =20 -DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; - /* * For CP-110 we have 2 Selector registers "PHY Selectors" * and " PIPE Selectors". @@ -1138,36 +1135,23 @@ ComPhySataCheckPll ( STATIC UINTN ComPhySataPowerUp ( + IN UINTN ChipId, IN UINT32 Lane, IN EFI_PHYSICAL_ADDRESS HpipeBase, IN EFI_PHYSICAL_ADDRESS ComPhyBase, - IN UINT8 SataHostId + IN MV_BOARD_AHCI_DESC *Desc ) { EFI_STATUS Status; - UINT8 *SataDeviceTable; - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_PHYSICAL_ADDRESS HpipeAddr =3D HPIPE_ADDR(HpipeBase, Lane); EFI_PHYSICAL_ADDRESS SdIpAddr =3D SD_ADDR(HpipeBase, Lane); EFI_PHYSICAL_ADDRESS ComPhyAddr =3D COMPHY_ADDR(ComPhyBase, Lane); =20 - SataDeviceTable =3D (UINT8 *) PcdGetPtr (PcdPciEAhci); - - if (SataDeviceTable =3D=3D NULL || SataHostId >=3D PcdGetSize (PcdPciEAh= ci)) { - DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is undefined\n", SataHo= stId)); - return EFI_INVALID_PARAMETER; - } - - if (!MVHW_DEV_ENABLED (Sata, SataHostId)) { - DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is disabled\n", SataHos= tId)); - return EFI_INVALID_PARAMETER; - } - DEBUG ((DEBUG_INFO, "ComPhySata: Initialize SATA PHYs\n")); =20 DEBUG((DEBUG_INFO, "ComPhySataPowerUp: stage: MAC configuration - power = down ComPhy\n")); =20 - ComPhySataMacPowerDown (Desc->AhciBaseAddresses[SataHostId]); + ComPhySataMacPowerDown (Desc[ChipId].SoC->AhciBaseAddress); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPh= y\n")); =20 @@ -1183,7 +1167,7 @@ ComPhySataPowerUp ( =20 DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); =20 - ComPhySataPhyPowerUp (Desc->AhciBaseAddresses[SataHostId]); + ComPhySataPhyPowerUp (Desc[ChipId].SoC->AhciBaseAddress); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); =20 @@ -1884,6 +1868,8 @@ ComPhyCp110Init ( EFI_STATUS Status; COMPHY_MAP *PtrComPhyMap, *SerdesMap; EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_AHCI_DESC *AhciBoardDesc; UINT32 ComPhyMaxCount, Lane; UINT32 PcieWidth =3D 0; UINT8 ChipId; @@ -1927,11 +1913,29 @@ ComPhyCp110Init ( break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: - Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP0_AHCI0_ID); - break; case COMPHY_TYPE_SATA2: case COMPHY_TYPE_SATA3: - Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP1_AHCI0_ID); + /* Obtain AHCI board description */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + break; + } + + Status =3D BoardDescProtocol->BoardDescAhciGet (BoardDescProtocol, + &AhciBoardDesc); + if (EFI_ERROR (Status)) { + break; + } + + Status =3D ComPhySataPowerUp (ChipId, + Lane, + HpipeBaseAddr, + ComPhyBaseAddr, + AhciBoardDesc); + + BoardDescProtocol->BoardDescFree (AhciBoardDesc); break; case COMPHY_TYPE_USB3_HOST0: case COMPHY_TYPE_USB3_HOST1: --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel