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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id q75-v6sm387272lfq.47.2018.06.17.13.12.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 17 Jun 2018 13:12:44 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22e; helo=mail-lf0-x22e.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Wpwvz/nZfmMXGyInFtEIakn0VTbKo76T0DFOJa1iTwk=; b=yaoquEQcJc9Rohb2pbX+KnIclSDvpxPxLkoj5QeW8rprkZaBDPeRZhgvsNr45DltBa vwJsBUZ8nMrUMMn219r9qF4aLGEZyx6SydwZm7Tim/PAZDBdqhvVVUDd9MNLSiGsBMe+ a843MpAEFEhl1uAccG/OogAKETjSqD/+WBSeVo1diIkUOKFRDoFF2OyarS9Jh+xVbCfa vJPEf8QVa0wYlZW0aooJFRaLEXfMu8d2DWphpuiKYDxseg3hVs+Oi05rlblWRQAthwkv RmcU4Ao4JoW6dcTXrGbTwSxvEJht6Jirp08ozrvJtfFK44fc0+DjUdFGdN88eWHyUTow vvQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Wpwvz/nZfmMXGyInFtEIakn0VTbKo76T0DFOJa1iTwk=; b=n1f2IEpyn9XvaAhustXOxF9BVMGcqKEsNQdnSS06KnGaTYDcuOQ7LxUaWo2uxZV5DA OqGPQ3NksJG/X9GK31EMqeKrYtKivsJPufdFayggkLQAt+B5dXEqj+4ho5uvJQMpwYgr G/hR/e4dT/OyymapBvuWEZWxJi5akpb9tLmQGBPEOgOVVp+grJgTCQu/8IOHMwpOjZVr rBtZvYaHeJtoJW9WuqrGhCJuemx74OygjazOdLPJWqWAuTncx7kD1Ckx59ugC+J7MfKQ 4LJpKOBBec5R7lpf9QWz6H5/L61Yvmuc99usXHdo6Oj/Vofk8alfPKM4WAHbnP/9fOrX mWzg== X-Gm-Message-State: APt69E1/ONNkzMJJsuVCNeCkyD/MPJX50ZTFYzShPdncgdiBL3zD20xg ZnLtZ/Bhi95PEc7i1LcFuSOr3IN7LAg= X-Google-Smtp-Source: ADUXVKJLlvi4qmKZZjpRsHQ23NwQdL7rQi8MOBGfSpYv0d6IG87HuLki1FSzXyd2N1X3/B0CI1LoVw== X-Received: by 2002:a2e:594d:: with SMTP id n74-v6mr6632017ljb.128.1529266365059; Sun, 17 Jun 2018 13:12:45 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Sun, 17 Jun 2018 22:11:55 +0200 Message-Id: <1529266325-18371-16-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529266325-18371-1-git-send-email-mw@semihalf.com> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 15/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with ComPhy information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescComPhyGet ()), which dynamically allocates and fills MV_SOC_COMPHY_DESC structure with the SoC description of ComPhy SerDes controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 8 +++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 20 ++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 33 ++++++++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index 94fd6fa..f372ca0 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -30,6 +30,14 @@ #define MV_SOC_AHCI_ID(Cp) ((Cp) % 2) =20 // +// Platform description of ComPhy controllers +// +#define MV_SOC_COMPHY_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x441000) +#define MV_SOC_HPIPE3_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x120000) +#define MV_SOC_COMPHY_LANE_COUNT 6 +#define MV_SOC_COMPHY_MUX_BITS 4 + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE ((Cp)) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 3b29d78..a133d1c 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -14,9 +14,29 @@ #ifndef __ARMADA_SOC_DESC_LIB_H__ #define __ARMADA_SOC_DESC_LIB_H__ =20 +#include #include =20 // +// ComPhy SoC description +// +typedef struct { + UINTN ComPhyId; + UINTN ComPhyBaseAddress; + UINTN ComPhyHpipe3BaseAddress; + UINTN ComPhyLaneCount; + UINTN ComPhyMuxBitCount; + MV_COMPHY_CHIP_TYPE ComPhyChipType; +} MV_SOC_COMPHY_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescComPhyGet ( + IN OUT MV_SOC_COMPHY_DESC **ComPhyDesc, + IN OUT UINTN *DescCount + ); + +// // NonDiscoverable devices SoC description // // AHCI diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 97fe3f8..580c0f4 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -30,6 +30,39 @@ =20 EFI_STATUS EFIAPI +ArmadaSoCDescComPhyGet ( + IN OUT MV_SOC_COMPHY_DESC **ComPhyDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_COMPHY_DESC *Desc; + UINTN CpCount, CpIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_COMPHY_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].ComPhyBaseAddress =3D MV_SOC_COMPHY_BASE (CpIndex); + Desc[CpIndex].ComPhyHpipe3BaseAddress =3D MV_SOC_HPIPE3_BASE (CpIndex); + Desc[CpIndex].ComPhyLaneCount =3D MV_SOC_COMPHY_LANE_COUNT; + Desc[CpIndex].ComPhyMuxBitCount =3D MV_SOC_COMPHY_MUX_BITS; + Desc[CpIndex].ComPhyChipType =3D MvComPhyTypeCp110; + Desc[CpIndex].ComPhyId =3D CpIndex; + } + + *ComPhyDesc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescAhciGet ( IN OUT MV_SOC_AHCI_DESC **AhciDesc, IN OUT UINTN *DescCount --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel