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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p20-v6sm3367058lji.37.2018.07.12.00.40.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Jul 2018 00:40:48 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::244; helo=mail-lj1-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=khXYrXboyx3QH1WBZ/mJZbVwxRFH3071/vUReyzgwNg=; b=IyWgTgLVAZnLjm/k98snth4f7E1cI4nvHO9ISQG10elxjWfw3PWlKa1TIltBKgk281 N3IIHQUeZa+6/aBN8Nr5NPyUCoK0g+mC5OOe/PeqbJ0UYHhrXgbWFhcs/GaV73BMxMEb vkFaOActBzwNwQSPvL0NvqjXZO0v1A2sK1ORVGwyDIOQlPY8kX7ZSxOYo1ZEodrEaE7c eVaRlM8167icLXUWHTIQ6r3IGFyHvpnuVD+pipkqJ3LzhVRgLNxaCTtvkXSFVnHUsjbY 9WNVnQCjRM1wK6QrfDrApLdeHJmqXgn/giRywKEwgFWTuiiYdPHMVTI5L/WsvgA/E89Q sRFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=khXYrXboyx3QH1WBZ/mJZbVwxRFH3071/vUReyzgwNg=; b=fVACNb6X2bP3UlqR6Aakc7VgrMc1vO0CX4S4/wvfNmul4qERRSPGFqXevqbRHw2Pza 7IuRhAxn6zvTSr8CjwRwQf0ZzI2FT+HJ3hl4ZsmCn4KgtP1m55Fj3Bd5Xrxu3ucyZmmn EtE9I26G0tmhnOfAasQmTqBiVWj+pa8cMvALvgxaDMzE003OhMceylt3+yPePZRTPWPl BvPjtP2a0tI3nz5PgeVxxaBlHVZZh/jCajTfD6Ffa4yr8IrnvQ4vX2C2F3Gn568ZJncm hXRvf45Nowdq0KycSPcY8CRj3ODYULhF79aAVL8vwJo/Ny5EV0cr0CXwPGu1Cw3H9n5E EqRg== X-Gm-Message-State: APt69E3xdnvsmdoj9GynmjkfBFwZtySfOsJk8K8bdy74rPpwYTkhg7eM OdtKH2UmTo0cremebHL6ryjYwJIDkA0= X-Google-Smtp-Source: AAOMgpf/uyb4wN2jYdh0RfghJq6oO2jIZpO6fn0kqQhPQzg2LFgkfsXzoPWh7eJt3tFO/Yjkrnfm5g== X-Received: by 2002:a2e:9dc7:: with SMTP id x7-v6mr8163507ljj.142.1531381249225; Thu, 12 Jul 2018 00:40:49 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Thu, 12 Jul 2018 09:39:56 +0200 Message-Id: <1531381201-5022-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531381201-5022-1-git-send-email-mw@semihalf.com> References: <1531381201-5022-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 1/6] Marvell/Armada70x0Db: Set correct CP110 count X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" As a preparation for adding the ICU (Interrupt Consolidation Unit) library implementation a correct CP110 count is required. Do it for Armada70x0Db and fix depending XHCI/AHCI PCD's accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 5ccee1b..2240a57 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -53,6 +53,9 @@ # ##########################################################################= ###### [PcdsFixedAtBuild.common] + #CP110 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|2 =20 @@ -129,8 +132,8 @@ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } =20 #PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 01:32:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1531381256758573.5529131021584; Thu, 12 Jul 2018 00:40:56 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2A2ED2097F56B; Thu, 12 Jul 2018 00:40:54 -0700 (PDT) Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9FE7A2097F564 for ; Thu, 12 Jul 2018 00:40:52 -0700 (PDT) Received: by mail-lj1-x242.google.com with SMTP id q127-v6so20668582ljq.11 for ; Thu, 12 Jul 2018 00:40:52 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p20-v6sm3367058lji.37.2018.07.12.00.40.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Jul 2018 00:40:49 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::242; helo=mail-lj1-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BNVNb9tu64AqW9rxFWo2VMw745bsHNjllCy9LucySZc=; b=vlgmMKJtQaNxQYE3mvopoURpRoTiow3kbk59rVocdkMlKtibl+HNJSOio9KunO6qaA 9bqvzv4Szu1LSCZHBG7mNeQE+Q6ItH84FnIQMjFr2HxNfjj0qcq0KiAKok2ARJ9hXgs6 1qiiVkR+5U8LYO2Nj/fGg8h9L8a4c+S0MNGCzS3wcSFd/h6Z4cin9B0QL8PPV/549OG0 U6h7fZxAqxsGfdBqC0MvccSWikHzVa/0BsKphYUbsA6UYD4+mFeRdPy6acKw++HDOl90 cTdFNSBuf5BzQGvIqIQqOVDmnkoiY/be0twDx4jQcPIL/mIlKm1PbjjHrDX40bclNfjr WckA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BNVNb9tu64AqW9rxFWo2VMw745bsHNjllCy9LucySZc=; b=ZGtlWIuUmhBFBrsQSJ1OyntQf6h7riIVEW9IGTMIEwfcxsrnnD8iy7yKydwm2vN1yC TZnj3L/KiOu014TzorVUxN0ua3d8W/HMvu4wJ/g/Xi6Lx0sRkk1ivoiP2wtwQL9DU8x9 i0ME3kork8SRAHp9a02gvZD/3BGR8mbmG2hcDzdvZKGJ9u8HK9qDT7y2JT6OE0wEVmDo 0j/LFVDBWZxuGOtpNniQ0nBynae1T/fVDRsNgQBRThHlsoi4omSRd4HknGG/di3hVWII ghOgFiZ+Ve92gE2MzEkHxLHVHvi6Z/eyxvBmo8186BSk6SObUO0HX2Y5lYXiO6T5JwGZ xQeA== X-Gm-Message-State: APt69E3kjhCY49+lWzM4KG9PKRQtRLssYdsUVsi8P8rkWG/R3jaF4O8m cxOyfFJhLsyOokDadB2YMfNvp0W5SRw= X-Google-Smtp-Source: AAOMgpcka0YLAegaKZaYCYYxn7De5OSeocOFtI4ckW7MYp7qXb/6rugvm/qOxMgzOPMMuOeywRAMjg== X-Received: by 2002:a2e:5617:: with SMTP id k23-v6mr20816852ljb.86.1531381250561; Thu, 12 Jul 2018 00:40:50 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Thu, 12 Jul 2018 09:39:57 +0200 Message-Id: <1531381201-5022-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531381201-5022-1-git-send-email-mw@semihalf.com> References: <1531381201-5022-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 2/6] Marvell/Library: Introduce ArmadaIcuLib class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" ICU (Interrupt Consolidation Unit) is a mechanism, that allows to send a message-based interrupts from the CP110 unit (South Bridge) to the Application Processor hardware block. After dispatching the interrupts in the GIC are generated. This patch adds a basic version of the library, that allows to configure a static mapping between CP110 interfaces and GIC. It is required for the cases, where the OS does not support the ICU controller on its own (e.g. ACPI boot). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Marvell.dec | 1 + Silicon/Marvell/Include/Library/ArmadaIcuLib.h | 45 ++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 Silicon/Marvell/Include/Library/ArmadaIcuLib.h diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 4def897..616624e 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -61,6 +61,7 @@ =20 [LibraryClasses] ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h + ArmadaIcuLib|Include/Library/ArmadaIcuLib.h ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h SampleAtResetLib|Include/Library/SampleAtResetLib.h =20 diff --git a/Silicon/Marvell/Include/Library/ArmadaIcuLib.h b/Silicon/Marve= ll/Include/Library/ArmadaIcuLib.h new file mode 100644 index 0000000..9b68934 --- /dev/null +++ b/Silicon/Marvell/Include/Library/ArmadaIcuLib.h @@ -0,0 +1,45 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ +#ifndef __ARMADA_ICU_LIB_H__ +#define __ARMADA_ICU_LIB_H__ + +typedef enum { + Level =3D 0, + Edge =3D 1 +} ICU_IRQ_TYPE; + +typedef struct { + UINTN IcuId; + UINTN SpiId; + ICU_IRQ_TYPE IrqType; +} ICU_IRQ; + +typedef struct { + const ICU_IRQ *Map; + UINTN Size; +} ICU_CONFIG_ENTRY; + +typedef struct { + ICU_CONFIG_ENTRY NonSecure; + ICU_CONFIG_ENTRY Sei; + ICU_CONFIG_ENTRY Rei; +} ICU_CONFIG; + +EFI_STATUS +EFIAPI +ArmadaIcuInitialize ( + VOID + ); + +#endif /* __ARMADA_ICU_LIB_H__ */ --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 01:32:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1531381259865848.1967695696189; Thu, 12 Jul 2018 00:40:59 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5865E2097F565; Thu, 12 Jul 2018 00:40:55 -0700 (PDT) Received: from mail-lf0-x232.google.com (mail-lf0-x232.google.com [IPv6:2a00:1450:4010:c07::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9B9F12097F564 for ; Thu, 12 Jul 2018 00:40:53 -0700 (PDT) Received: by mail-lf0-x232.google.com with SMTP id v22-v6so9925779lfe.8 for ; Thu, 12 Jul 2018 00:40:53 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p20-v6sm3367058lji.37.2018.07.12.00.40.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Jul 2018 00:40:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::232; helo=mail-lf0-x232.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Pn1xYGYYZXpnEpZLtNSY5KPjfwkTi8g10LGVFZuCg24=; b=oeoHbljFBKm+D17mXuyaKAeYEDOvfqhc/7dXoZ8FoOWkXe3FEC4Tu4ypQaBZJpb6Uw 6CzG271Vlro+Q2ahSgu3EcBahdG8281zpalimUVR6/vSlupXye+V6P7Xzs4y6Mk12m+H GMnCZV1fffHbjTHPJljy9qxi9A5tHo6cUCYzjIKcYmxtrdjqMAJ/TQpq2PCpQ16W64Eo JLv4B32yDKZVe7DmvoBfrepWptY4pCmFOj0jfCuN66dKLj5XRn0wSHqiDF3bmNcoZB8y 3JsM9/HBEq8q2QbEHpC6vP48dApNjR/Qzr1X2/wsVFVlB21f2n8pvqO/07BvEhF4lVle NdAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Pn1xYGYYZXpnEpZLtNSY5KPjfwkTi8g10LGVFZuCg24=; b=Sl/TC712p2LfwJa2ZnS9ZibvWiu0D719UP5C6lhqzPBdjVvxdcJRczUmSV/CGbi4KY MvFsNGYdy3QOvJXF0p/z+l1+dtijWmHvYQV7rX0ZUmn6BI/VCj5cf8xNh03inJs5K5Ca Ai7vnzOOiwEG+jRAGq1aheOi0ocd8phkMmc5z6gi7Y44mdy5fpbO0Xf7YeRiOv+YRZ2d fBuylf+OObPQuGcl4/WHgwy69m5p16n55zHtzkvD4O/PESZyS+lnLccDuSKhQWO8aXfj nHmsEmYGU5QaS7nld32XY1oRT8IOrdAFZQvIH8HRrYS4ygihYe0ExV57hola7JyazSpt J1/A== X-Gm-Message-State: AOUpUlEI4nvDtsCOKIbrGHMwrTCZoswh1fHqhHgx1OT1vyJFp7hTQAG8 uwRssuxzKZH4uX9m5Jf7doZxIIEvmgU= X-Google-Smtp-Source: AAOMgpeBeGK9vZ4nKiHzgMz2rBnJCKOoajtoQeL+PLLee4cOfakI4MK3dsvF64YamS7TTPARyk02+g== X-Received: by 2002:a19:dd81:: with SMTP id w1-v6mr903627lfi.114.1531381251674; Thu, 12 Jul 2018 00:40:51 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Thu, 12 Jul 2018 09:39:58 +0200 Message-Id: <1531381201-5022-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531381201-5022-1-git-send-email-mw@semihalf.com> References: <1531381201-5022-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 3/6] Marvell/Library: Armada7k8kSoCDescLib: Enable getting CP base address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" For upcoming patches there is a need to get the CP110 base address, introduce according getter function for it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 6 ++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 11 +++++++++++ 2 files changed, 17 insertions(+) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index d2bcf2a..56efdbe 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -36,6 +36,12 @@ ArmadaSoCDescComPhyGet ( IN OUT UINTN *DescCount ); =20 +UINTN +EFIAPI +ArmadaSoCDescCpBaseGet ( + IN UINTN CpIndex + ); + // // I2C // diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 6ce6bad..c7c9c13 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -61,6 +61,17 @@ ArmadaSoCDescComPhyGet ( return EFI_SUCCESS; } =20 +UINTN +EFIAPI +ArmadaSoCDescCpBaseGet ( + IN UINTN CpIndex + ) +{ + ASSERT (CpIndex < FixedPcdGet8 (PcdMaxCpCount)); + + return MV_SOC_CP_BASE (CpIndex); +} + EFI_STATUS EFIAPI ArmadaSoCDescI2cGet ( --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 01:32:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 153138126275010.390341919705747; Thu, 12 Jul 2018 00:41:02 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8D33C2097F572; Thu, 12 Jul 2018 00:40:55 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E884D202E5483 for ; Thu, 12 Jul 2018 00:40:54 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id f18-v6so7317133lfc.2 for ; Thu, 12 Jul 2018 00:40:54 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p20-v6sm3367058lji.37.2018.07.12.00.40.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Jul 2018 00:40:52 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BWZvCmJMPNnJqXpAYTpyMg5PqkORAGAREWYG1XnApYc=; b=xNCeN7plqD/6pXKvyi0uHV4VmlaI6W02080kVrdvNvgZEk0ioE+1qa6cn/Lrv6KADK XnAHWYy/xnW8dx2Mx1wLs6XVS5b+WR5qpkOLnXmBCB+bfhTYBT8fEU5CSSxjLIQNR2Sn UUp6KyOB4uo668LppUEQP8X9TxOBkbQRr3XyIoOXjUZQ1TWcIBMS0PACG5Jboyef8RX5 p2/ACJwIRotxg4+i8pXZDL/XIlGDCb3sBdLTvVqxh18oTk+6H3f3cKBATH333PjKdvsh 4bFEiaQAGtdc+Y4u0pZ1NruZroDGmMqZm2bEaLJxUOhpERSt6H4+z1iHqc3iG/3BTNvd ZdqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BWZvCmJMPNnJqXpAYTpyMg5PqkORAGAREWYG1XnApYc=; b=f6FbUqvQdbUJPuG6SwzumRgNlVqjl4b9xP1PAdLJ6kFiwJfo1trCICOHxU/sq5q4ib VU5DenVkzORuYC1h6g56K2DbY0Gb66Tu2dRfO2LvzlMl+9U5dx+4QD8+BUfHIijslW2/ qJf8RZa5ITjkdhUj5zL6+MHMoCWnFrbHxhn6OFWMXM+V1EsHGo7Kz7i8ksks+5SUv0Oh fCwUJbGMjnBsGQFXyDSfrfYo+yEtgrZA0s9SCYD5DoQhsLTsJpcuts2QGq1jHH5S696d X+2qwYi61SHtDrOeYAR69IjSuhgkiLnoebxDmN8WP7CaWvYjE36E2/0IjBhBOTbLE5eg cCCw== X-Gm-Message-State: AOUpUlEinkx3SoxXQYP0jaGAfrvKDn5owHrf5u/OHxgnvtFSBQdUG2tS Dy3m0AJMnuvFV4bw09VsNPp6ErQhdZI= X-Google-Smtp-Source: AAOMgpdPGjKNDuEaV+39mJ9+j5hVvoQsCdEbMCA4yB4Qcv3ps2M0IT53OG+cvhKDdRHU5xzS8fuPcQ== X-Received: by 2002:a19:921a:: with SMTP id u26-v6mr946547lfd.89.1531381252842; Thu, 12 Jul 2018 00:40:52 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Thu, 12 Jul 2018 09:39:59 +0200 Message-Id: <1531381201-5022-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531381201-5022-1-git-send-email-mw@semihalf.com> References: <1531381201-5022-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 4/6] Marvell/Library: Armada7k8kSoCDescLib: Introduce ICU information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescIcuGet ()), which dynamically allocates and fills MV_SOC_ICU_DESC structure with the SoC description of ICU (Interrupt Consolidation Unit). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 12 ++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 30 +++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 39 ++++++++++++++++++++ 3 files changed, 81 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index 3072883..c14b985 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -44,6 +44,18 @@ #define MV_SOC_I2C_BASE(I2c) (0x701000 + ((I2c) * 0x100)) =20 // +// Platform description of ICU (Interrupt Consolidation Unit) controllers +// +#define ICU_GIC_MAPPING_OFFSET 0 +#define ICU_NSR_SET_SPI_BASE 0xf03f0040 +#define ICU_NSR_CLEAR_SPI_BASE 0xf03f0048 +#define ICU_SEI_SET_SPI_BASE 0xf03f0230 +#define ICU_SEI_CLEAR_SPI_BASE 0xf03f0230 +#define ICU_REI_SET_SPI_BASE 0xf03f0270 +#define ICU_REI_CLEAR_SPI_BASE 0xf03f0270 +#define ICU_GROUP_UNSUPPORTED 0x0 + +// // Platform description of MDIO controllers // #define MV_SOC_MDIO_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x12A200) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 56efdbe..4d2a85f 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -58,6 +58,36 @@ ArmadaSoCDescI2cGet ( ); =20 // +// ICU (Interrupt Consolidation Unit) +// +typedef enum { + ICU_GROUP_NSR =3D 0, + ICU_GROUP_SR =3D 1, + ICU_GROUP_LPI =3D 2, + ICU_GROUP_VLPI =3D 3, + ICU_GROUP_SEI =3D 4, + ICU_GROUP_REI =3D 5, + ICU_GROUP_MAX, +} ICU_GROUP; + +typedef struct { + ICU_GROUP Group; + UINTN SetSpiAddr; + UINTN ClrSpiAddr; +} ICU_MSI; + +typedef struct { + UINTN IcuSpiBase; + ICU_MSI IcuMsi[ICU_GROUP_MAX]; +} MV_SOC_ICU_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescIcuGet ( + IN OUT MV_SOC_ICU_DESC **IcuDesc + ); + +// // MDIO // typedef struct { diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index c7c9c13..8383206 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -103,6 +103,45 @@ ArmadaSoCDescI2cGet ( return EFI_SUCCESS; } =20 +// +// Allocate the MSI address per interrupt Group, +// unsupported Groups get NULL address. +// +STATIC +MV_SOC_ICU_DESC mA7k8kIcuDescTemplate =3D { + ICU_GIC_MAPPING_OFFSET, + { + /* Non secure interrupts */ + {ICU_GROUP_NSR, ICU_NSR_SET_SPI_BASE, ICU_NSR_CLEAR_SPI_BASE}, + /* Secure interrupts */ + {ICU_GROUP_SR, ICU_GROUP_UNSUPPORTED, ICU_GROUP_UNSUPPORTED}, + /* LPI interrupts */ + {ICU_GROUP_LPI, ICU_GROUP_UNSUPPORTED, ICU_GROUP_UNSUPPORTED}, + /* Virtual LPI interrupts */ + {ICU_GROUP_VLPI, ICU_GROUP_UNSUPPORTED, ICU_GROUP_UNSUPPORTED}, + /* System error interrupts */ + {ICU_GROUP_SEI, ICU_SEI_SET_SPI_BASE, ICU_SEI_CLEAR_SPI_BASE}, + /* RAM error interrupts */ + {ICU_GROUP_REI, ICU_REI_SET_SPI_BASE, ICU_REI_CLEAR_SPI_BASE}, + } +}; + +EFI_STATUS +EFIAPI +ArmadaSoCDescIcuGet ( + IN OUT MV_SOC_ICU_DESC **IcuDesc + ) +{ + *IcuDesc =3D AllocateCopyPool (sizeof (mA7k8kIcuDescTemplate), + &mA7k8kIcuDescTemplate); + if (*IcuDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + return EFI_SUCCESS; +} + EFI_STATUS EFIAPI ArmadaSoCDescMdioGet ( --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 01:32:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 153138126592287.17201123384837; Thu, 12 Jul 2018 00:41:05 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B7D622097F578; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p20-v6sm3367058lji.37.2018.07.12.00.40.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Jul 2018 00:40:53 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=urwfgaU4a0i8EW5uny6nlGXo1PKZcEk2BzjXpTJ1kP4=; b=GXdTDJiuVTn96Wq1Cl36hw4ibK9mLdnF4pw6IvRFes4YwAwXKNrFEreLL30dd/xvWQ A+0A81osJU5FgwrtDM9/6lf0TNZMxNCLYF3IuHelrLcRMnFzO/8SxsqMwWzABvPhcg9K U47r0wBRgVRsglHBWnIP3z89wBpRlhfBmQITsOQw4Uz1anbn7JF6eSe5R1DDmr9bVQ0L Bu1CDGkWrGwyFXw2wudvhjcpJoWsNbeial0vBgDMVzQtxI5ouWwUG8a79TWjYmAW7cql oqqowVZOgWN8I9GXfWCS1f4csxXzZCg1RysI6r1WvmMTz4/UClN9LZeQkr/Iyx7Iyljy eJ6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=urwfgaU4a0i8EW5uny6nlGXo1PKZcEk2BzjXpTJ1kP4=; b=rd8EI+kEzesFZNMAFyOpMeWlf/cm8+sH0mXLq6LfGxLkVI52qPKeqxGtTmWki5+nL7 jXhk6He6rHJwxMagK46DSyispYgoBqQcPnM0e4u3ZakCjJ1uLsJH91+grNsoL/jkxqkO Xs33VDYNkaDfn6Lwhoh0htmwOLb+uXogZs9rfgwX7jzJDp5sctqEWTzyWSHpFWbkL1rc pdRWY3rB6bM50Xx3uvF7JHY3ckZ7e5Ag91mTaXYsMSXrTDb7KDOZyRSGksYUDTmX0rDz Moa2S7AZds/APkovTv4WM9ntxdvWsAAdKvDpvb0vERvwGiIVJXyf6Hvjk2J2Ev7h8wiq xMQg== X-Gm-Message-State: AOUpUlGGxzFGRNqEzTYypfzsg0N4Jp1ZZPLLokkbyg5l8Rmkq9s4UcmO snjyKguOLRJWaETwoBwDcIK8f9Zv6Z4= X-Google-Smtp-Source: AAOMgpfRVKshFPW7nlOIelVdie8LADGQ6JMDR2wIDqMymxfOjz7pGk+WWtV4hPQE4mpLWSJeHZPKDw== X-Received: by 2002:a19:d54c:: with SMTP id m73-v6mr881146lfg.27.1531381254133; Thu, 12 Jul 2018 00:40:54 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Thu, 12 Jul 2018 09:40:00 +0200 Message-Id: <1531381201-5022-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531381201-5022-1-git-send-email-mw@semihalf.com> References: <1531381201-5022-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 5/6] Marvell/Library: Implement common ArmadaIcuLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" ICU (Interrupt Consolidation Unit) is a mechanism, that allows to send-message based interrupts from the CP110 unit (South Bridge) to the Application Processor hardware block. After dispatching the interrupts in the GIC are generated. This patch adds a basic version of the library, that allows to configure a static mapping between CP110 interfaces and GICv2 of the Armada7k8k SoC family. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Library/IcuLib/IcuLib.inf | 38 +++ Silicon/Marvell/Library/IcuLib/IcuLib.h | 46 +++ Silicon/Marvell/Library/IcuLib/IcuLib.c | 315 ++++++++++++++++++++ 3 files changed, 399 insertions(+) create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.inf create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.h create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.c diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.inf b/Silicon/Marvell/Li= brary/IcuLib/IcuLib.inf new file mode 100644 index 0000000..0010141 --- /dev/null +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.inf @@ -0,0 +1,38 @@ +## @file +# +# Copyright (C) 2018, Marvell International Ltd. and its affiliates
+# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D IcuLib + FILE_GUID =3D 0301c9cb-43e6-40a8-96bf-41bd0501e86d + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmadaIcuLib + +[Sources] + IcuLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + ArmadaSoCDescLib + DebugLib + IoLib + PcdLib + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdMaxCpCount diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.h b/Silicon/Marvell/Libr= ary/IcuLib/IcuLib.h new file mode 100644 index 0000000..4bf2298 --- /dev/null +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.h @@ -0,0 +1,46 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Glossary - abbreviations used in Marvell SampleAtReset library implemen= tation: +* ICU - Interrupt Consolidation Unit +* AP - Application Processor hardware block (Armada 7k8k incorporates AP8= 06) +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ICU_REG_BASE(Cp) ArmadaSoCDescCpBaseGet (CpIndex) + 0x1E0000 + +#define ICU_SET_SPI_AL(x) (0x10 + (0x10 * x)) +#define ICU_SET_SPI_AH(x) (0x14 + (0x10 * x)) +#define ICU_CLR_SPI_AL(x) (0x18 + (0x10 * x)) +#define ICU_CLR_SPI_AH(x) (0x1c + (0x10 * x)) +#define ICU_INT_CFG(x) (0x100 + 4 * x) + +#define ICU_INT_ENABLE_OFFSET 24 +#define ICU_IS_EDGE_OFFSET 28 +#define ICU_GROUP_OFFSET 29 + +#define ICU_MAX_SUPPORTED_UNITS 2 +#define ICU_MAX_IRQS_PER_CP 64 + +#define MAX_ICU_IRQS 207 diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c b/Silicon/Marvell/Libr= ary/IcuLib/IcuLib.c new file mode 100644 index 0000000..4ac98aa --- /dev/null +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c @@ -0,0 +1,315 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Glossary - abbreviations used in Marvell SampleAtReset library implemen= tation: +* ICU - Interrupt Consolidation Unit +* AP - Application Processor hardware block (Armada 7k8k incorporates AP8= 06) +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +* +**/ + +#include "IcuLib.h" + +EFI_EVENT EfiExitBootServicesEvent =3D (EFI_EVENT)NULL; + +STATIC CONST ICU_IRQ IrqMapNonSecure[] =3D { + {22, 0, Level}, /* PCIx4 INT A interrupt */ + {23, 1, Level}, /* PCIx1 INT A interrupt */ + {24, 2, Level}, /* PCIx1 INT A interrupt */ + {27, 3, Level}, /* SD/MMC */ + {33, 4, Level}, /* PPv2 DBG AXI monitor */ + {34, 4, Level}, /* HB1 AXI monitor */ + {35, 4, Level}, /* AP AXI monitor */ + {36, 4, Level}, /* PPv2 AXI monitor */ + {39, 5, Level}, /* PPv2 Irq */ + {40, 6, Level}, /* PPv2 Irq */ + {41, 7, Level}, /* PPv2 Irq */ + {43, 8, Level}, /* PPv2 Irq */ + {44, 9, Level}, /* PPv2 Irq */ + {45, 10, Level}, /* PPv2 Irq */ + {47, 11, Level}, /* PPv2 Irq */ + {48, 12, Level}, /* PPv2 Irq */ + {49, 13, Level}, /* PPv2 Irq */ + {51, 14, Level}, /* PPv2 Irq */ + {52, 15, Level}, /* PPv2 Irq */ + {53, 16, Level}, /* PPv2 Irq */ + {55, 17, Level}, /* PPv2 Irq */ + {56, 18, Level}, /* PPv2 Irq */ + {57, 19, Level}, /* PPv2 Irq */ + {59, 20, Level}, /* PPv2 Irq */ + {60, 21, Level}, /* PPv2 Irq */ + {61, 22, Level}, /* PPv2 Irq */ + {63, 23, Level}, /* PPv2 Irq */ + {64, 24, Level}, /* PPv2 Irq */ + {65, 25, Level}, /* PPv2 Irq */ + {67, 26, Level}, /* PPv2 Irq */ + {68, 27, Level}, /* PPv2 Irq */ + {69, 28, Level}, /* PPv2 Irq */ + {71, 29, Level}, /* PPv2 Irq */ + {72, 30, Level}, /* PPv2 Irq */ + {73, 31, Level}, /* PPv2 Irq */ + {78, 32, Level}, /* MG Irq */ + {79, 33, Level}, /* GPIO 56-63 */ + {80, 34, Level}, /* GPIO 48-55 */ + {81, 35, Level}, /* GPIO 40-47 */ + {82, 36, Level}, /* GPIO 32-39 */ + {83, 37, Level}, /* GPIO 24-31 */ + {84, 38, Level}, /* GPIO 16-23 */ + {85, 39, Level}, /* GPIO 8-15 */ + {86, 40, Level}, /* GPIO 0-7 */ + {88, 41, Level}, /* EIP-197 ring-0 */ + {89, 42, Level}, /* EIP-197 ring-1 */ + {90, 43, Level}, /* EIP-197 ring-2 */ + {91, 44, Level}, /* EIP-197 ring-3 */ + {92, 45, Level}, /* EIP-197 int */ + {95, 46, Level}, /* EIP-150 Irq */ + {102, 47, Level}, /* USB3 Device Irq */ + {105, 48, Level}, /* USB3 Host-1 Irq */ + {106, 49, Level}, /* USB3 Host-0 Irq */ + {107, 50, Level}, /* SATA Host-1 Irq */ + {109, 50, Level}, /* SATA Host-0 Irq */ + {115, 52, Level}, /* NAND Irq */ + {117, 53, Level}, /* SPI-1 Irq */ + {118, 54, Level}, /* SPI-0 Irq */ + {120, 55, Level}, /* I2C 0 Irq */ + {121, 56, Level}, /* I2C 1 Irq */ + {122, 57, Level}, /* UART 0 Irq */ + {123, 58, Level}, /* UART 1 Irq */ + {124, 59, Level}, /* UART 2 Irq */ + {125, 60, Level}, /* UART 3 Irq */ + {127, 61, Level}, /* GOP-3 Irq */ + {128, 62, Level}, /* GOP-2 Irq */ + {129, 63, Level}, /* GOP-0 Irq */ +}; + +/* + * SEI - System Error Interrupts + * Note: SPI ID 0-20 are reserved for North-Bridge + */ +STATIC ICU_IRQ IrqMapSei[] =3D { + {11, 21, Level}, /* SEI error CP-2-CP */ + {15, 22, Level}, /* PIDI-64 SOC */ + {16, 23, Level}, /* D2D error Irq */ + {17, 24, Level}, /* D2D Irq */ + {18, 25, Level}, /* NAND error */ + {19, 26, Level}, /* PCIx4 error */ + {20, 27, Level}, /* PCIx1_0 error */ + {21, 28, Level}, /* PCIx1_1 error */ + {25, 29, Level}, /* SDIO reg error */ + {75, 30, Level}, /* IOB error */ + {94, 31, Level}, /* EIP150 error */ + {97, 32, Level}, /* XOR-1 system error */ + {99, 33, Level}, /* XOR-0 system error */ + {108, 34, Level}, /* SATA-1 error */ + {110, 35, Level}, /* SATA-0 error */ + {114, 36, Level}, /* TDM-MC error */ + {116, 37, Level}, /* DFX server Irq */ + {117, 38, Level}, /* Device bus error */ + {147, 39, Level}, /* Audio error */ + {171, 40, Level}, /* PIDI Sync error */ +}; + +/* REI - RAM Error Interrupts */ +STATIC CONST ICU_IRQ IrqMapRei[] =3D { + {12, 0, Level}, /* REI error CP-2-CP */ + {26, 1, Level}, /* SDIO memory error */ + {87, 2, Level}, /* EIP-197 ECC error */ + {93, 3, Edge}, /* EIP-150 RAM error */ + {96, 4, Level}, /* XOR-1 memory Irq */ + {98, 5, Level}, /* XOR-0 memory Irq */ + {100, 6, Edge}, /* USB3 device tx parity */ + {101, 7, Edge}, /* USB3 device rq parity */ + {103, 8, Edge}, /* USB3H-1 RAM error */ + {104, 9, Edge}, /* USB3H-0 RAM error */ +}; + +STATIC CONST ICU_CONFIG IcuConfigDefault =3D { + .NonSecure =3D { IrqMapNonSecure, ARRAY_SIZE (IrqMapNonSecure) }, + .Sei =3D { IrqMapSei, ARRAY_SIZE (IrqMapSei) }, + .Rei =3D { IrqMapRei, ARRAY_SIZE (IrqMapRei) }, +}; + +STATIC +VOID +IcuClearIrq ( + IN UINTN IcuBase, + IN UINTN Nr +) +{ + MmioWrite32 (IcuBase + ICU_INT_CFG (Nr), 0); +} + +STATIC +VOID +IcuSetIrq ( + IN UINTN IcuBase, + IN CONST ICU_IRQ *Irq, + IN UINTN SpiBase, + IN ICU_GROUP Group + ) +{ + UINT32 IcuInt; + + IcuInt =3D (Irq->SpiId + SpiBase) | (1 << ICU_INT_ENABLE_OFFSET); + IcuInt |=3D Irq->IrqType << ICU_IS_EDGE_OFFSET; + IcuInt |=3D Group << ICU_GROUP_OFFSET; + + MmioWrite32 (IcuBase + ICU_INT_CFG (Irq->IcuId), IcuInt); +} + +STATIC +VOID +IcuConfigure ( + IN UINTN CpIndex, + IN MV_SOC_ICU_DESC *IcuDesc, + IN CONST ICU_CONFIG *Config + ) +{ + UINTN IcuBase, Index, SpiOffset, SpiBase; + CONST ICU_IRQ *Irq; + ICU_MSI *Msi; + + /* Get ICU registers base address */ + IcuBase =3D ICU_REG_BASE (CpIndex); + /* Get the base of the GIC SPI ID in the MSI message */ + SpiBase =3D IcuDesc->IcuSpiBase; + /* Get multiple CP110 instances SPI ID shift */ + SpiOffset =3D CpIndex * ICU_MAX_IRQS_PER_CP; + /* Get MSI addresses per interrupt group */ + Msi =3D IcuDesc->IcuMsi; + + /* Set the address for SET_SPI and CLR_SPI registers in AP */ + for (Index =3D 0; Index < ICU_GROUP_MAX; Index++, Msi++) { + MmioWrite32 (IcuBase + ICU_SET_SPI_AL (Msi->Group), Msi->SetSpiAddr & = 0xFFFFFFFF); + MmioWrite32 (IcuBase + ICU_SET_SPI_AH (Msi->Group), Msi->SetSpiAddr >>= 32); + MmioWrite32 (IcuBase + ICU_CLR_SPI_AL (Msi->Group), Msi->ClrSpiAddr & = 0xFFFFFFFF); + MmioWrite32 (IcuBase + ICU_CLR_SPI_AH (Msi->Group), Msi->ClrSpiAddr >>= 32); + } + + /* Mask all ICU interrupts */ + for (Index =3D 0; Index < MAX_ICU_IRQS; Index++) { + IcuClearIrq (IcuBase, Index); + } + + /* Configure the ICU interrupt lines */ + Irq =3D Config->NonSecure.Map; + for (Index =3D 0; Index < Config->NonSecure.Size; Index++, Irq++) { + IcuSetIrq (IcuBase, Irq, SpiBase + SpiOffset, ICU_GROUP_NSR); + } + + Irq =3D Config->Sei.Map; + for (Index =3D 0; Index < Config->Sei.Size; Index++, Irq++) { + IcuSetIrq (IcuBase, Irq, SpiBase, ICU_GROUP_SEI); + } + + Irq =3D Config->Rei.Map; + for (Index =3D 0; Index < Config->Rei.Size; Index++, Irq++) { + IcuSetIrq (IcuBase, Irq, SpiBase, ICU_GROUP_REI); + } +} + +STATIC +VOID +IcuClearGicSpi ( + IN UINTN CpIndex, + IN MV_SOC_ICU_DESC *IcuDesc + ) +{ + CONST ICU_CONFIG *Config; + UINTN Index, SpiOffset, SpiBase; + CONST ICU_IRQ *Irq; + ICU_MSI *Msi; + + Config =3D &IcuConfigDefault; + + /* Get the base of the GIC SPI ID in the MSI message */ + SpiBase =3D IcuDesc->IcuSpiBase; + /* Get multiple CP110 instances SPI ID shift */ + SpiOffset =3D CpIndex * ICU_MAX_IRQS_PER_CP; + /* Get MSI addresses per interrupt group */ + Msi =3D IcuDesc->IcuMsi; + + /* Clear ICU-generated GIC SPI interrupts */ + Irq =3D Config->NonSecure.Map; + for (Index =3D 0; Index < Config->NonSecure.Size; Index++, Irq++) { + MmioWrite32 (Msi->ClrSpiAddr, Irq->SpiId + SpiBase + SpiOffset); + } +} + +VOID +EFIAPI +IcuCleanUp ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + MV_SOC_ICU_DESC *IcuDesc; + UINTN CpCount, CpIndex; + + IcuDesc =3D Context; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + if (CpCount > ICU_MAX_SUPPORTED_UNITS) { + CpCount =3D ICU_MAX_SUPPORTED_UNITS; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + IcuClearGicSpi (CpIndex, IcuDesc); + } +} + +EFI_STATUS +EFIAPI +ArmadaIcuInitialize ( + ) +{ + MV_SOC_ICU_DESC *IcuDesc; + UINTN CpCount, CpIndex; + EFI_STATUS Status; + + /* + * Due to limited amount of interrupt lanes, only 2 units can be + * wired to the GIC. + */ + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + if (CpCount > ICU_MAX_SUPPORTED_UNITS) { + DEBUG ((DEBUG_ERROR, + "%a: Default ICU to GIC mapping is available for maximum %d CP110 un= its", + ICU_MAX_SUPPORTED_UNITS, + __FUNCTION__)); + CpCount =3D ICU_MAX_SUPPORTED_UNITS; + } + + /* Obtain SoC description of the ICU */ + Status =3D ArmadaSoCDescIcuGet (&IcuDesc); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Configure default ICU to GIC interrupt mapping for each CP110 */ + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + IcuConfigure (CpIndex, IcuDesc, &IcuConfigDefault); + } + + /* + * In order to be immune to the OS capability of clearing ICU-generated + * GIC interrupts, register ExitBootServices event, that will + * make sure they remain disabled during OS boot. + */ + Status =3D gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_NOTIFY, + IcuCleanUp, + IcuDesc, + &EfiExitBootServicesEvent); + + return Status; +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 01:32:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 153138126922827.342912162692073; Thu, 12 Jul 2018 00:41:09 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E3E152097F57A; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p20-v6sm3367058lji.37.2018.07.12.00.40.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 12 Jul 2018 00:40:54 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T4qnvTvThFqm0EkupzXK8oo7D50DloF28IyRSXi8/CQ=; b=o2aONctrTLoBPacBIGWEy5OBJOnxAc4HZWk9amTT7HiBviPxK7ryVzLO6qCn7iEBJ8 Q3lxMZPk3PagrAtf+1fJ/rLD1fhR+JeJ1Eh7lRckrLZVNIQchggMVZtvq5EvzVWj2hqK gllA5Z7rP9uH1VojUQqQ48I1/dsStR2kHbGkfMB+rhtu7N1gxpCWpODXGYKXPPM4OMpG SWAK4IIW8EUN8xiDfOGd0jSIrwcrDLhv5E2+0R4JR67bMFcPg28T6cfd4cvHpAnoJZWz 1g0SANg77cxv0v6ylmS5eb1fl58kSswzQYUDLJMCAC9Tm880AlqIT5E6/LIBwEGYE23A 06yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T4qnvTvThFqm0EkupzXK8oo7D50DloF28IyRSXi8/CQ=; b=rogvSJvnYp4N2/0UUrSpCCbASzSQD7GRnNP9ZUMqscaY1R5EbJAhvE4aTaGuMAQm+v v3s/ozqALoIoYrMP+GBwxsc+TdON/Y9CALQT7ZxBumYf6ztb7rSjw7zCoeofNRqlzHoa LmBwLoC+4rQUeNk6kEHUdukYrETRzEvQp/wP4SklPEvlI8cSkszBrwGK2g8ZteuVKmnL XExEtP0Lk2nDSbNB2rSVeBydb9yRAqpwFZ8+D7Bz57jIsYA80gtRNmJDfcI7SWWbb5Ps 0Nsi8/XNDCnk21ttUxUcG7gr8O94FSkdM/6DNbZVEi3LpcjoizmDDx/NXl9bzNAZfmcH bK8A== X-Gm-Message-State: AOUpUlHVRZTjxRzd+b3NnguvEwT9HurtT+6e9yrhGwHs0KnCybprbNj2 eprjvzSKcS1wY9uIGvW8Ymk0zs8SULk= X-Google-Smtp-Source: AAOMgpcUyKccoQT3mB8K5mj5LWy1GMipt1bXLzPf7N/eplee4S4hzzdPSYJH5pFVUbkFtIiewxEYew== X-Received: by 2002:a19:8f8f:: with SMTP id s15-v6mr963052lfk.96.1531381255279; Thu, 12 Jul 2018 00:40:55 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Thu, 12 Jul 2018 09:40:01 +0200 Message-Id: <1531381201-5022-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531381201-5022-1-git-send-email-mw@semihalf.com> References: <1531381201-5022-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 6/6] Marvell/Armada7k8k: Enable ICU configuration X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch enables the ICU (Interrupt Consolidation Unit) configuration in the common platform initialization driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 + Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf | 1 + Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index a9d67a2..27b14ed 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -32,6 +32,7 @@ #SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # [LibraryClasses.common] + ArmadaIcuLib|Silicon/Marvell/Library/IcuLib/IcuLib.inf ArmadaSoCDescLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib= /Armada7k8kSoCDescLib.inf ArmPlatformLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k= 8kLib.inf ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf= b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf index 803dc6e..5503463 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf +++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -30,6 +30,7 @@ Silicon/Marvell/Marvell.dec =20 [LibraryClasses] + ArmadaIcuLib ComPhyLib DebugLib MppLib diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c b= /Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c index 1efad77..18b6783 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c +++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c @@ -12,6 +12,7 @@ =20 **/ =20 +#include #include #include #include @@ -40,6 +41,7 @@ ArmadaPlatInitDxeEntryPoint ( MvComPhyInit (); UtmiPhyInit (); MppInitialize (); + ArmadaIcuInitialize (); =20 return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel