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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id o74-v6sm81596lfg.31.2018.07.26.00.21.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Jul 2018 00:21:58 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::242; helo=mail-lj1-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MsTwYLserrvOSmmArl1slovX027EQLv/c1hy0RJyAX0=; b=COxPsMavQpMhnV0A/fCjTzRTtE8xYRG5vdRcPXNm7u5Zy8YSdZ8bCfDcZIfmsaJ4vl 7DQ6mWbE4E/EuEg8tLkmO9IBqb7JynLYpR8Da4R61xyiZMbxyWujh2w3kYyMrohQ93pC 5H1v84Yy1WEttudlNmULksfMz1D3c2twhjHVhTHLSmpSfRkth0dWBzSftzT+xc/b+mdi YuvlX1NYlMsyVOIrcqHhSu8Ueh3Dtar2bs5rB+LltC5zeiYhZx6sgT/EeyFuVEqO7Odb z/KlDhtwJIv9CTz/tw8uH3wvhsqBbFmMWxceZkELlUOeOs54N0oqcVeQSpnnntUaG8uF VySw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MsTwYLserrvOSmmArl1slovX027EQLv/c1hy0RJyAX0=; b=HX2pB2z+0Ja02k08RELMKz8e+jyh3rPmF7IiYJsDHdabOo8Fg+VmghhmkzS97C9Ws/ xSgfSNWup36Z+4Wh/fUtpMPtOYa69+QYRJETquE407ejHuk1Nu/AfnZqJFaG0HN5lSij wBtOpMaufDT+P50/pwNLrDRnGtlCkrpAN9LSt4PbCfEqmr96XmJB3qGYmhqsDsL9mkH4 /nB9CsXZ+TaiIWnf7YQ0lUVHPZ0lSpeNxlI1DlgmCN6/ee93xywKcXL2k6tuDxwS7XdK TxrFn5Ih5Y/a3g4VcoJMqRNM+gsnBW46R8XPJF7PlJNAtZZj+u+garPb370Rrmsax0iy 93bA== X-Gm-Message-State: AOUpUlHAdP4wakKx0QUClmMQKSA9FrUX63XMEwJwH3IRltRSUNs7TZqA 7KUPgBgRCHStLEuTlp66K2E5bQJYvmod0g== X-Google-Smtp-Source: AAOMgpcxZAeGLL3+DBW0B7nxgieUKAIrUvt4URP1gvMwZqYzaHXfCcPrrVWFxa8naVoC1a4Ad97bHA== X-Received: by 2002:a2e:800e:: with SMTP id j14-v6mr654847ljg.114.1532589719678; Thu, 26 Jul 2018 00:21:59 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Thu, 26 Jul 2018 09:21:34 +0200 Message-Id: <1532589696-16902-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532589696-16902-1-git-send-email-mw@semihalf.com> References: <1532589696-16902-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 4/6] Marvell/Library: ComPhyLib: Configure USB in ARM-TF X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Grzegorz Jaszczyk Replace the comphy initialization for USB with appropriate SMC call, so the ARM-TF will execute required serdes configuration. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 167 +------------------- 1 file changed, 4 insertions(+), 163 deletions(-) diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyCp110.c index c46cad1..35ac459 100755 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -100,168 +100,6 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] =3D { =20 STATIC VOID -ComPhyUsb3RFUConfiguration ( - IN EFI_PHYSICAL_ADDRESS ComPhyAddr -) -{ - UINT32 Mask, Data; - - /* RFU configurations - hard reset ComPhy */ - Mask =3D COMMON_PHY_CFG1_PWR_UP_MASK; - Data =3D 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; - Mask |=3D COMMON_PHY_CFG1_PIPE_SELECT_MASK; - Data |=3D 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; - Mask |=3D COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - Data |=3D 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - Mask |=3D COMMON_PHY_CFG1_CORE_RSTN_MASK; - Data |=3D 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - Mask |=3D COMMON_PHY_PHY_MODE_MASK; - Data |=3D 0x1 << COMMON_PHY_PHY_MODE_OFFSET; - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); - - /* Release from hard reset */ - Mask =3D COMMON_PHY_CFG1_PWR_ON_RESET_MASK; - Data =3D 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; - Mask |=3D COMMON_PHY_CFG1_CORE_RSTN_MASK; - Data |=3D 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; - RegSet (ComPhyAddr + COMMON_PHY_CFG1_REG, Data, Mask); - - /* Wait 1ms - until band gap and ref clock ready */ - MicroSecondDelay (1000); - MemoryFence (); -} - -STATIC -VOID -ComPhyUsb3PhyConfiguration ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr -) -{ - UINT32 Mask, Data; - - /* Set PIPE soft reset */ - Mask =3D HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; - Data =3D 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; - - /* Set PHY Datapath width mode for V0 */ - Mask |=3D HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; - Data |=3D 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; - - /* Set Data bus width USB mode for V0 */ - Mask |=3D HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; - Data |=3D 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; - - /* Set CORE_CLK output frequency for 250Mhz */ - Mask |=3D HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; - Data |=3D 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask); - - /* Set PLL ready delay for 0x2 */ - RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, - 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, - HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); - - /* Set reference clock to come from group 1 - 25Mhz */ - RegSet (HpipeAddr + HPIPE_MISC_REG, 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, - HPIPE_MISC_REFCLK_SEL_MASK); - - /* Set reference frequcency select - 0x2 */ - Mask =3D HPIPE_PWR_PLL_REF_FREQ_MASK; - Data =3D 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; - - /* Set PHY mode to USB - 0x5 */ - Mask |=3D HPIPE_PWR_PLL_PHY_MODE_MASK; - Data |=3D 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; - RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask); - - /* Set the amount of time spent in the LoZ state - set for 0x7 */ - RegSet (HpipeAddr + HPIPE_GLOBAL_PM_CTRL, - 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET, - HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK); - - /* Set max PHY generation setting - 5Gbps */ - RegSet (HpipeAddr + HPIPE_INTERFACE_REG, - 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK); - - /* Set select Data width 20Bit (SEL_BITS[2:0]) */ - RegSet (HpipeAddr + HPIPE_LOOPBACK_REG, - 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); -} - -STATIC -VOID -ComPhyUsb3SetAnalogParameters ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr -) -{ - UINT32 Data, Mask; - - /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS =3D 0x0 */ - Mask =3D HPIPE_LANE_CFG4_DFE_CTRL_MASK; - Data =3D 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; - - /* Set Override PHY DFE control pins for 0x1 */ - Mask |=3D HPIPE_LANE_CFG4_DFE_OVER_MASK; - Data |=3D 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; - - /* Set Spread Spectrum Clock Enable fot 0x1 */ - Mask |=3D HPIPE_LANE_CFG4_SSC_CTRL_MASK; - Data |=3D 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; - RegSet (HpipeAddr + HPIPE_LANE_CFG4_REG, Data, Mask); -} - -STATIC -UINTN -ComphyUsb3PowerUp ( - UINT32 Lane, - EFI_PHYSICAL_ADDRESS HpipeBase, - EFI_PHYSICAL_ADDRESS ComPhyBase - ) -{ - EFI_STATUS Status =3D EFI_SUCCESS; - UINT32 Data; - EFI_PHYSICAL_ADDRESS HpipeAddr =3D HPIPE_ADDR(HpipeBase, Lane); - EFI_PHYSICAL_ADDRESS ComPhyAddr =3D COMPHY_ADDR(ComPhyBase, Lane); - - DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPh= y\n")); - - ComPhyUsb3RFUConfiguration (ComPhyAddr); - - /* Start ComPhy Configuration */ - DEBUG((DEBUG_INFO, "stage: Comphy configuration\n")); - - ComPhyUsb3PhyConfiguration (HpipeAddr); - - /* Start analog paramters from ETP(HW) */ - DEBUG((DEBUG_INFO, "ComPhy: stage: Analog paramters from ETP(HW)\n")); - - ComPhyUsb3SetAnalogParameters (HpipeAddr); - - DEBUG((DEBUG_INFO, "ComPhy: stage: Comphy power up\n")); - - /* Release from PIPE soft reset */ - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); - - /* Wait 15ms - for ComPhy calibration done */ - MicroSecondDelay (15000); - MemoryFence (); - - DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); - - /* Read Lane status */ - Data =3D MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG); - if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) =3D=3D 0) { - DEBUG((DEBUG_ERROR, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n")); - Status =3D EFI_D_ERROR; - } - - return Status; -} - -STATIC -VOID ComPhySataMacPowerDown ( IN EFI_PHYSICAL_ADDRESS SataBase ) @@ -528,7 +366,10 @@ ComPhyCp110Init ( break; case COMPHY_TYPE_USB3_HOST0: case COMPHY_TYPE_USB3_HOST1: - Status =3D ComphyUsb3PowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr); + Status =3D ComPhySmc (MV_SIP_COMPHY_POWER_ON, + PtrChipCfg->ComPhyBaseAddr, + Lane, + COMPHY_FW_MODE_FORMAT (COMPHY_USB3H_MODE)); break; case COMPHY_TYPE_SGMII0: case COMPHY_TYPE_SGMII1: --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel