From nobody Fri Apr 19 20:51:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 15332785327781005.6094191533772; Thu, 2 Aug 2018 23:42:12 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B22A8210C4DD1; Thu, 2 Aug 2018 23:42:11 -0700 (PDT) Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C0F102097FA8F for ; Thu, 2 Aug 2018 23:42:10 -0700 (PDT) Received: by mail-pl0-x241.google.com with SMTP id z7-v6so2131989plo.9 for ; Thu, 02 Aug 2018 23:42:10 -0700 (PDT) Received: from localhost.localdomain ([117.197.43.141]) by smtp.gmail.com with ESMTPSA id t88-v6sm10505465pfg.10.2018.08.02.23.42.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 02 Aug 2018 23:42:09 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=sumit.garg@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sYNdrocr3d2RIZqKYvvA+BDzw7sOhd06MQNo+Ea5E6s=; b=ENJwD+AVSdqQpbtIJUb9xGhI+TBJ26Ura73INtyY34/tipBnK7G9ooAIGLg8X5zs3u C9Jut1mgF4ARbLPijitW5Bpn6Cp2yjOqTWNw5JH17C7tHl310q6bmQHt8JVGfAONAd/D 6ePlbcDMrR/T4/S4RioqooVF+rYUfOypHt6g0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sYNdrocr3d2RIZqKYvvA+BDzw7sOhd06MQNo+Ea5E6s=; b=fC4Bqo1OjzYG55ECAqtcDVz6ZoOR/+UposckoJ9i0NJjisMj3HnwzYACMeEH3Hrfj0 l2XzNe8tKq2fP0/sBdjYVV1C/Q4DsPb1QIGaKTR3wr0oWg8X28WI3tRWsoA0lCt7DXv6 L5xuvQSZCIbL7Yi1ItB3VA2gAaX7My7PPeF+fMoN430ct2GDnvr6MUsR+s0cXAQLtvsd s7SLRA+aRWUN0UlJ8e+gJNwGmuc4GSYOMTqkIdJxDjHc2z2eiQjeX8BInFvV2f/Pzsni JX4S70I2jHo7QqCR7zaEsallpTj3b5HUFvreexb53MZEF7dCvVBgszlxFsPNexggORKJ Y+aw== X-Gm-Message-State: AOUpUlH6CEXGB2+a5PXmKtRYDgkKhKvX07pwb2zm7FGz4dYpqdpjEiyq SzoAiif8pcoI1g0lceNCy7GLlaWD3bs= X-Google-Smtp-Source: AAOMgpd4xyRHW6hdQLwZzX4gFmyaEy1nPJMDpA5AR1sBevdwk73LJyEilD6R+iIDbSRS2ri4g9F0Ug== X-Received: by 2002:a17:902:4906:: with SMTP id u6-v6mr2344410pld.44.1533278530161; Thu, 02 Aug 2018 23:42:10 -0700 (PDT) From: Sumit Garg To: edk2-devel@lists.01.org Date: Fri, 3 Aug 2018 12:11:34 +0530 Message-Id: <1533278495-25323-2-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533278495-25323-1-git-send-email-sumit.garg@linaro.org> References: <1533278495-25323-1-git-send-email-sumit.garg@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/2] Silicon/SynQuacer: add optional OP-TEE DT node X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" OP-TEE is optional on Developerbox controlled via SCP firmware. To check if we need to enable OP-TEE DT node, we use "IsOpteePresent" OpteeLib api. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg Cc: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 1 + .../Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 8 +++++++ .../SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 28 ++++++++++++++++++= ++++ .../SynQuacerDtbLoaderLib.inf | 2 ++ 4 files changed, 39 insertions(+) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/So= cionext/DeveloperBox/DeveloperBox.dsc index fc498eb65217..4ff5df978e8e 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -76,6 +76,7 @@ [LibraryClasses.common] ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatfo= rmStackLib.inf ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/Ar= mGenericTimerPhyCounterLib.inf + OpteeLib|ArmPkg/Library/OpteeLib/OpteeLib.inf =20 BaseLib|MdePkg/Library/BaseLib/BaseLib.inf BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.i= nf diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silico= n/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 37d642e4b237..d6a5f013e58c 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -574,6 +574,14 @@ #address-cells =3D <1>; #size-cells =3D <0>; }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + status =3D "disabled"; + }; + }; }; =20 #include "SynQuacerCaches.dtsi" diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQ= uacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoade= rLib/SynQuacerDtbLoaderLib.c index 897d06743708..77db30c204fe 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDt= bLoaderLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDt= bLoaderLib.c @@ -19,6 +19,7 @@ #include #include #include +#include #include =20 // add enough space for three instances of 'status =3D "disabled"' @@ -47,6 +48,29 @@ DisableDtNode ( } } =20 +STATIC +VOID +EnableDtNode ( + IN VOID *Dtb, + IN CONST CHAR8 *NodePath + ) +{ + INT32 Node; + INT32 Rc; + + Node =3D fdt_path_offset (Dtb, NodePath); + if (Node < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", + __FUNCTION__, NodePath, fdt_strerror (Node))); + return; + } + Rc =3D fdt_setprop_string (Dtb, Node, "status", "okay"); + if (Rc < 0) { + DEBUG ((DEBUG_ERROR, "%a: failed to set status to 'disabled' on '%a': = %a\n", + __FUNCTION__, NodePath, fdt_strerror (Rc))); + } +} + /** Return a pool allocated copy of the DTB image that is appropriate for booting the current platform via DT. @@ -107,6 +131,10 @@ DtPlatformLoadDtb ( DisableDtNode (CopyDtb, "/sdhci@52300000"); } =20 + if (IsOpteePresent()) { + EnableDtNode (CopyDtb, "/firmware/optee"); + } + *Dtb =3D CopyDtb; *DtbSize =3D CopyDtbSize; =20 diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQ= uacerDtbLoaderLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoa= derLib/SynQuacerDtbLoaderLib.inf index 548d62fd5c0a..fd21f7c376ce 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDt= bLoaderLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDt= bLoaderLib.inf @@ -24,6 +24,7 @@ [Sources] SynQuacerDtbLoaderLib.c =20 [Packages] + ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec EmbeddedPkg/EmbeddedPkg.dec Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -34,6 +35,7 @@ [LibraryClasses] DxeServicesLib FdtLib MemoryAllocationLib + OpteeLib =20 [Pcd] gSynQuacerTokenSpaceGuid.PcdPcieEnableMask --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Apr 19 20:51:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=dMI5JYo7UNUCX7qhQtXmYq5671fFvNLWtuZcCv+dwBc=; b=Px2eYSSxUabzfpWlz1E8NYJVEHxzHG/q5GcCeSunupCiyh20kJFwhOMl/EipBPBJvt sVoogLJ+/PWPgcXcP5uzIFv30TXPUJfRngjBTyaECxWRb04LR3hKCFSs/Bs1EPXiIeYl LlYuT2V+vJOB7pkJCIA4280CiV/1+RhwjdQ+S+k3t0NVq75MbPtQBUJzi91NYeIc8RPE JQPbZpEJT/JZvzJsIvwqRUqGL9GwB7pZgzTczCI8tK1ZjPg4txRZMrWOOo0ff5Fmxm30 FKlG4FAiWyUZ1q4v22P+NipoENvGBj1xevTTndip4mLmOp6MZvGTJ7ArY8bRar1Jj2tx +Tpg== X-Gm-Message-State: AOUpUlEZ1dpijz7KaY5GiYol6TAMGc4WdTVBya9Z7bq48mLQQooKgfEb +AOHBIIRG101SM+zcWLSCpNU303Dbwc= X-Google-Smtp-Source: AAOMgpe4qCFyOXhVJvdvAPuyEdlOR3oJf3MJGpHevKb/P3Jv8m3YJbYOhdaaYNEU9NXbHucnyPNGEg== X-Received: by 2002:a17:902:7683:: with SMTP id m3-v6mr2275777pll.255.1533278538399; Thu, 02 Aug 2018 23:42:18 -0700 (PDT) From: Sumit Garg To: edk2-devel@lists.01.org Date: Fri, 3 Aug 2018 12:11:35 +0530 Message-Id: <1533278495-25323-3-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533278495-25323-1-git-send-email-sumit.garg@linaro.org> References: <1533278495-25323-1-git-send-email-sumit.garg@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/2] Silicon/SynQuacer: Add status property in PCIe & SDHC DT nodes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add status =3D "disabled" property by default for PCIe and SDHC DT nodes. If required, update them at runtime with status =3D "okay". Using this method we don't need extra DTB_PADDING. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sumit Garg Cc: Leif Lindholm Reviewed-by: Ard Biesheuvel --- .../Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 3 ++ .../SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 40 ++++--------------= ---- 2 files changed, 10 insertions(+), 33 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silico= n/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index d6a5f013e58c..003e21bd6f85 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -473,6 +473,7 @@ =20 msi-map =3D <0x000 &its 0x0 0x7f00>; dma-coherent; + status =3D "disabled"; }; =20 pcie1: pcie@70000000 { @@ -492,6 +493,7 @@ =20 msi-map =3D <0x0 &its 0x10000 0x7f00>; dma-coherent; + status =3D "disabled"; }; =20 gpio: gpio@51000000 { @@ -537,6 +539,7 @@ clocks =3D <&clk_alw_c_0 &clk_alw_b_0>; clock-names =3D "core", "iface"; dma-coherent; + status =3D "disabled"; }; =20 clk_alw_1_8: spi_ihclk { diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQ= uacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoade= rLib/SynQuacerDtbLoaderLib.c index 77db30c204fe..96090c20502c 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDt= bLoaderLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDt= bLoaderLib.c @@ -22,32 +22,6 @@ #include #include =20 -// add enough space for three instances of 'status =3D "disabled"' -#define DTB_PADDING 64 - -STATIC -VOID -DisableDtNode ( - IN VOID *Dtb, - IN CONST CHAR8 *NodePath - ) -{ - INT32 Node; - INT32 Rc; - - Node =3D fdt_path_offset (Dtb, NodePath); - if (Node < 0) { - DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", - __FUNCTION__, NodePath, fdt_strerror (Node))); - return; - } - Rc =3D fdt_setprop_string (Dtb, Node, "status", "disabled"); - if (Rc < 0) { - DEBUG ((DEBUG_ERROR, "%a: failed to set status to 'disabled' on '%a': = %a\n", - __FUNCTION__, NodePath, fdt_strerror (Rc))); - } -} - STATIC VOID EnableDtNode ( @@ -105,7 +79,7 @@ DtPlatformLoadDtb ( return EFI_NOT_FOUND; } =20 - CopyDtbSize =3D OrigDtbSize + DTB_PADDING; + CopyDtbSize =3D OrigDtbSize; CopyDtb =3D AllocatePool (CopyDtbSize); if (CopyDtb =3D=3D NULL) { return EFI_OUT_OF_RESOURCES; @@ -118,17 +92,17 @@ DtPlatformLoadDtb ( return EFI_NOT_FOUND; } =20 - if (!(PcdGet8 (PcdPcieEnableMask) & BIT0)) { - DisableDtNode (CopyDtb, "/pcie@60000000"); + if (PcdGet8 (PcdPcieEnableMask) & BIT0) { + EnableDtNode (CopyDtb, "/pcie@60000000"); } - if (!(PcdGet8 (PcdPcieEnableMask) & BIT1)) { - DisableDtNode (CopyDtb, "/pcie@70000000"); + if (PcdGet8 (PcdPcieEnableMask) & BIT1) { + EnableDtNode (CopyDtb, "/pcie@70000000"); } =20 SettingsVal =3D PcdGet64 (PcdPlatformSettings); Settings =3D (SYNQUACER_PLATFORM_VARSTORE_DATA *)&SettingsVal; - if (Settings->EnableEmmc =3D=3D EMMC_DISABLED) { - DisableDtNode (CopyDtb, "/sdhci@52300000"); + if (Settings->EnableEmmc =3D=3D EMMC_ENABLED) { + EnableDtNode (CopyDtb, "/sdhci@52300000"); } =20 if (IsOpteePresent()) { --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel