From nobody Tue May 13 16:40:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1533632441373740.6912013153718; Tue, 7 Aug 2018 02:00:41 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BDD2D210DC1CE; Tue, 7 Aug 2018 02:00:27 -0700 (PDT) Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 69DD4210DC1CB for ; Tue, 7 Aug 2018 02:00:25 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id l16-v6so11045260lfc.13 for ; Tue, 07 Aug 2018 02:00:25 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id w27-v6sm181697lfk.5.2018.08.07.02.00.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 07 Aug 2018 02:00:21 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::135; helo=mail-lf1-x135.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jWs0jsn1KBz7f6KWj9PD/o0zN2Q060UXQcjdwjkkBc8=; b=GNzyMMVBxHWpwCK1UrinPO25aem6qUUghOVgV6CWogYoH+VBgsWNbfbmdjWgrT6hoR qoGRcLp16STnBgIG75sYSlcmGJfKFPuxfHcLfWrtf8ZvnTX9FntvyW6SzJBc24LVKVnr huIwp6Fc5mPOIeaScBr9F/a+KInJH2q/QM8UYxOzd36l/8dJaWIPRc7BhkHtp5EgH5jV CGd5qKGpdpj1f1A/nJO5ZPbmBRrObFHA5lXWeUDHahrGpcDAtJCjJdl8S0GY6o8oUz31 Aqn/xhNY7ewro2DsPvcAQggsznxSQPVav6I44XmWg37GPkiqNC72KCV1beN2WN5wuygz RQ1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jWs0jsn1KBz7f6KWj9PD/o0zN2Q060UXQcjdwjkkBc8=; b=ZC94+ew0y0zocIG+JYK3eaVf8L8w6gDfauL06/u9qQZ7KuAICTP9fsbDLMFHiuoyvb WnZRCGopLMdNZUOLqArUSxAH/0IwN+/9C8s9HePkQBylbEWBYGBeXwi01SqKgxTYEahF P/fKKgDM052dwzr+c6OxkRtA3TK9GyDGefWGAhKwP7p+VNZLHqk5beBieeMjTe16FYFX QCRqZvX6F8Tno+ZTRD88lnbzKzGhyr3z8iWT8QP+ZQnefwDgTUcuEyFMepbOnMqcLcW9 pBjs4zOvrgjouMzW89fB8b8fosL8yHIRdRT5LhufiKp8an1WDn/kqSl8lOAFOIx+mBQB 8Jog== X-Gm-Message-State: AOUpUlEARvAxK3W8ddWWPyBpvz0g/MsooaHLT/TJPdROycvsR9/QuA0S CsVfT0kPY6e0iroqcPFEq5WTn1pqB5oQmA== X-Google-Smtp-Source: AAOMgpcKJtmzMp+JRQVszSNrdq2MPp/frbxJJ6DbwNmz02VvBmNkc9jdtSJpB7wpow7FZhavkSoFAQ== X-Received: by 2002:a19:8d07:: with SMTP id p7-v6mr14200510lfd.117.1533632422512; Tue, 07 Aug 2018 02:00:22 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 7 Aug 2018 10:58:15 +0200 Message-Id: <1533632298-4981-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1533632298-4981-1-git-send-email-mw@semihalf.com> References: <1533632298-4981-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 6/9] Marvell/Armada7k8k: Add common ACPI tables X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch adds ACPI tables and necessary headers, which are common for Armada7k8k SoCs. Per-board tables and wiring up of support will be done in the follow-up commits. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 45 ++++ Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 42 ++++ Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc | 86 ++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc | 64 ++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc | 139 +++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc | 216 ++++++++++++++= ++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 53 +++++ 7 files changed, 645 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h b/Silicon/M= arvell/Armada7k8k/AcpiTables/AcpiHeader.h new file mode 100644 index 0000000..f5ebd27 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h @@ -0,0 +1,45 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#define ACPI_OEM_ID_ARRAY {'M','V','E','B','U',' '} +#define ACPI_OEM_REVISION 0 +#define ACPI_CREATOR_ID SIGNATURE_32('L','N','R','O') +#define ACPI_CREATOR_REVISION 0 + +#if defined(ARMADA7K) +#define ACPI_OEM_TABLE_ID SIGNATURE_64('A','R','M','A','D','A','7',= 'K') +#elif defined (ARMADA8K) +#define ACPI_OEM_TABLE_ID SIGNATURE_64('A','R','M','A','D','A','8',= 'K') +#endif + +/** + * A macro to initialize the common header part of EFI ACPI tables + * as defined by EFI_ACPI_DESCRIPTION_HEADER structure. + **/ +#define __ACPI_HEADER(sign, type, rev) { \ + sign, /* UINT32 Signature */ \ + sizeof (type), /* UINT32 Length */ \ + rev, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + ACPI_OEM_ID_ARRAY, /* UINT8 OemId[6] */ \ + ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + ACPI_OEM_REVISION, /* UINT32 OemRevision */ \ + ACPI_CREATOR_ID, /* UINT32 CreatorId */ \ + ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h b/Silico= n/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h new file mode 100644 index 0000000..5746ad4 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h @@ -0,0 +1,42 @@ +/** + + Copyright (C) 2018, Marvell International Ltd. and its affiliates. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + Glossary - abbreviations used in Marvell SampleAtReset library implement= ation: + ICU - Interrupt Consolidation Unit + AP - Application Processor hardware block (Armada 7k8k incorporates AP80= 6) + CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) + +**/ + +#define CP_GIC_SPI_CP0_PCI0 64 +#define CP_GIC_SPI_CP0_PCI1 65 +#define CP_GIC_SPI_CP0_PCI2 66 +#define CP_GIC_SPI_CP0_SDMMC 67 +#define CP_GIC_SPI_PP2_CP0_PORT0 69, 72, 75, 78, 81, 127 +#define CP_GIC_SPI_PP2_CP0_PORT1 70, 73, 76, 79, 82, 126 +#define CP_GIC_SPI_PP2_CP0_PORT2 71, 74, 77, 80, 83, 125 +#define CP_GIC_SPI_CP0_EIP_RNG0 105 +#define CP_GIC_SPI_CP0_USB_H1 112 +#define CP_GIC_SPI_CP0_USB_H0 113 +#define CP_GIC_SPI_CP0_SATA_H0 114 + +#define CP_GIC_SPI_CP1_PCI0 288 +#define CP_GIC_SPI_CP1_PCI1 289 +#define CP_GIC_SPI_CP1_PCI2 290 +#define CP_GIC_SPI_CP1_SDMMC 291 +#define CP_GIC_SPI_PP2_CP1_PORT0 293, 296, 299, 302, 305, 351 +#define CP_GIC_SPI_PP2_CP1_PORT1 294, 297, 300, 303, 306, 350 +#define CP_GIC_SPI_PP2_CP1_PORT2 295, 298, 301, 304, 307, 349 +#define CP_GIC_SPI_CP1_EIP_RNG0 329 +#define CP_GIC_SPI_CP1_USB_H1 336 +#define CP_GIC_SPI_CP1_USB_H0 337 +#define CP_GIC_SPI_CP1_SATA_H0 338 diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Fadt.aslc new file mode 100644 index 0000000..de88210 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Fadt.aslc @@ -0,0 +1,86 @@ +/** @file + + Fixed ACPI Description Table (FADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" + +#define FADT_FLAGS EFI_ACPI_6_0_HW_REDUCED_ACPI | \ + EFI_ACPI_6_0_LOW_POWER_S0_IDLE_CAPABLE | \ + EFI_ACPI_6_0_HEADLESS + +EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D { + __ACPI_HEADER (EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_0_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmP= rofile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + 0, // UINT16 IaPcBootArch + 0, // UINT8 Reserved1 + FADT_FLAGS, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_0_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArch + EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 = MinorVersion + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_6_0_GENERIC_AD= DRESS_STRUCTURE SleepStatusReg +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Fadt; diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Gtdt.aslc new file mode 100644 index 0000000..16a8806 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Gtdt.aslc @@ -0,0 +1,64 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" + +// active low, level triggered +#define GTDT_GTIMER_FLAGS EFI_ACPI_6_0_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILI= TY + +// active high, level triggered +#define GTDT_WDG_FLAGS 0x0 + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE Header; + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE SbsaWatchdog; +} ACPI_6_0_GTDT_STRUCTURE; +#pragma pack() + +ACPI_6_0_GTDT_STRUCTURE Gtdt =3D { + { + __ACPI_HEADER (EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_GTDT_STRUCTURE, + EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION), + 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAdd= ress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecureEL1Ti= merGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecureEL1Ti= merFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecureEL= 1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL= 1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTime= rGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTime= rFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecureEL= 2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecureEL= 2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBase= Address + 0x1, // UINT32 PlatformTim= erCount + sizeof (Gtdt.Header) // UINT32 PlatformTim= erOffset + }, { + EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type + sizeof (Gtdt.SbsaWatchdog), // UINT16 Length + 0x0, // UINT8 Reserved + FixedPcdGet64 (PcdGenericWatchdogRefreshBase), // UINT64 RefreshFram= ePhysicalAddress + FixedPcdGet64 (PcdGenericWatchdogControlBase), // UINT64 WatchdogCon= trolFramePhysicalAddress + FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), // UINT32 WatchdogTim= erGSIV + GTDT_WDG_FLAGS // UINT32 WatchdogTim= erFlags + }, +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Gtdt; diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Madt.aslc new file mode 100644 index 0000000..3dae5d3 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Madt.aslc @@ -0,0 +1,139 @@ +/** @file + + Multiple APIC Description Table (MADT) + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ Copyright (C) 2018, Marvell International Ltd. and its affiliates.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" + +#define GICC_BASE FixedPcdGet64 (PcdGicInterruptInterfaceB= ase) +#define GICD_BASE FixedPcdGet64 (PcdGicDistributorBase) +#define GICH_BASE 0xF0240000 +#define GICV_BASE 0xF0260000 +#define VGIC_MAINT_INT 25 // SPI #9 + +#define GIC_MSI_FRAME0 0xF0280000 +#define GIC_MSI_FRAME1 0xF0290000 +#define GIC_MSI_FRAME2 0xF02A0000 +#define GIC_MSI_FRAME3 0xF02B0000 + +#define PMU_INTERRUPT_CPU0 130 +#define PMU_INTERRUPT_CPU1 131 +#define PMU_INTERRUPT_CPU2 132 +#define PMU_INTERRUPT_CPU3 133 + +#pragma pack(push, 1) +typedef struct { + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_0_GIC_STRUCTURE GicC[4]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicD; + EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE GicM[4]; +} ACPI_6_0_MADT_STRUCTURE; +#pragma pack(pop) + + +ACPI_6_0_MADT_STRUCTURE Madt =3D { + { + __ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + ACPI_6_0_MADT_STRUCTURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION), + 0, // UINT32 LocalApicAddress + 0 // UINT32 Flags + }, + { + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(0, // GicId + 0x000, // AcpiCpu= Uid + 0x000, // Mpidr + EFI_ACPI_6_0_GIC_ENABLED, // Flags + PMU_INTERRUPT_CPU0, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(1, // GicId + 0x001, // AcpiCpu= Uid + 0x001, // Mpidr + EFI_ACPI_6_0_GIC_ENABLED, // Flags + PMU_INTERRUPT_CPU1, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(2, // GicId + 0x100, // AcpiCpu= Uid + 0x100, // Mpidr + EFI_ACPI_6_0_GIC_ENABLED, // Flags + PMU_INTERRUPT_CPU2, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(3, // GicId + 0x101, // AcpiCpu= Uid + 0x101, // Mpidr + EFI_ACPI_6_0_GIC_ENABLED, // Flags + PMU_INTERRUPT_CPU3, // PmuIrq + GICC_BASE, // GicBase + GICV_BASE, // GicVBase + GICH_BASE, // GicHBase + VGIC_MAINT_INT, // GsivId + 0, // GicRBase + 0 // Efficie= ncy + ), + }, + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0x0, // GicDist= HwId + GICD_BASE, // GicDist= Base + 0x0, // GicDist= Vector + EFI_ACPI_6_0_GIC_V2 // GicVers= ion + ), + { + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x0, // GicMsiF= rameId + GIC_MSI_FRAME0, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x1, // GicMsiF= rameId + GIC_MSI_FRAME1, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x2, // GicMsiF= rameId + GIC_MSI_FRAME2, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0x3, // GicMsiF= rameId + GIC_MSI_FRAME3, // BaseAdd= ress + 0, // Flags + 0, // SPICount + 0 // SPIBase + ), + } +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Madt; diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Pptt.aslc new file mode 100644 index 0000000..8de29bd3 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Pptt.aslc @@ -0,0 +1,216 @@ +/** @file + + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ Copyright (c) 2018, Marvell International Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include "AcpiHeader.h" + +#define NUM_CORES FixedPcdGet64 (PcdCoreCount) + +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name) + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 Offset[2]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache; +} ACPI_6_2_PPTT_CORE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache; + ACPI_6_2_PPTT_CORE Cores[2]; +} ACPI_6_2_PPTT_CLUSTER; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 Offset[1]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache; + ACPI_6_2_PPTT_CLUSTER Clusters[NUM_C= ORES / 2]; +} ACPI_6_2_PPTT_PACKAGE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt; + ACPI_6_2_PPTT_PACKAGE Packages[1]; +} ACPI_6_2_PPTT_STRUCTURE; +#pragma pack() + +#define PPTT_CORE(pid, cid, id) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_CORE, DCache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */= \ + }, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid]), /* Parent */ = \ + 256 * (cid) + (id), /* AcpiProcessorId */ = \ + 2, /* NumberOfPrivateResource= s */ \ + }, { = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid].Cores[id].DCache), = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, = \ + Packages[pid].Clusters[cid].Cores[id].ICache), = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_32KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 2, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 0, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + 3 * SIZE_16KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 3, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType = */ \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \ + 0, /* WritePolicy */ = \ + }, = \ + 64 /* LineSize */ = \ + } = \ +} + +#define PPTT_CLUSTER(pid, cid) { = \ + { = \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_CLUSTER, L2Cache), = \ + {}, = \ + { = \ + 0, /* PhysicalPackage */ = \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ = \ + }, = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid]), /* Parent */ = \ + 0, /* AcpiProcessorId */ = \ + 1, /* NumberOfPrivateResources = */ \ + }, { = \ + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[pid].Clusters[cid].L2C= ache), \ + }, { = \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \ + {}, = \ + { = \ + 1, /* SizePropertyValid */ = \ + 1, /* NumberOfSetsValid */ = \ + 1, /* AssociativityValid */ = \ + 1, /* AllocationTypeValid */ = \ + 1, /* CacheTypeValid */ = \ + 1, /* WritePolicyValid */ = \ + 1, /* LineSizeValid */ = \ + }, = \ + 0, /* NextLevelOfCache */ = \ + SIZE_512KB, /* Size */ = \ + 256, /* NumberOfSets */ = \ + 16, /* Associativity */ = \ + { = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \ + }, = \ + 64 /* LineSize */ = \ + }, { = \ + PPTT_CORE(pid, cid, 0), = \ + PPTT_CORE(pid, cid, 1), = \ + } = \ +} + +ACPI_6_2_PPTT_STRUCTURE Pptt =3D { + { + __ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTU= RE_SIGNATURE, + ACPI_6_2_PPTT_STRUCTURE, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVIS= ION), + }, + { + { + { + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, + FIELD_OFFSET (ACPI_6_2_PPTT_PACKAGE, L3Cache), + {}, + { + 1, /* PhysicalPackage */ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid = */ + }, + 0, /* Parent */ + 0, /* AcpiProcessorId */ + 1, /* NumberOfPrivateResour= ces */ + }, { + FIELD_OFFSET (ACPI_6_2_PPTT_STRUCTURE, Packages[0].L3Cache), + }, { + EFI_ACPI_6_2_PPTT_TYPE_CACHE, + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), + {}, + { + 1, /* SizePropertyValid */ + 1, /* NumberOfSetsValid */ + 1, /* AssociativityValid */ + 1, /* AllocationTypeValid */ + 1, /* CacheTypeValid */ + 1, /* WritePolicyValid */ + 1, /* LineSizeValid */ + }, + 0, /* NextLevelOfCache */ + SIZE_1MB, /* Size */ + 2048, /* NumberOfSets */ + 8, /* Associativity */ + { + 0, /* AllocationType */ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, + }, + 64 /* LineSize */ + }, { + PPTT_CLUSTER (0, 0), +#if NUM_CORES > 3 + PPTT_CLUSTER (0, 1), +#endif + } + } + } +}; + +VOID * CONST ReferenceAcpiTable =3D &Pptt; diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc b/Silicon/Marv= ell/Armada7k8k/AcpiTables/Spcr.aslc new file mode 100644 index 0000000..e78bb90 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc @@ -0,0 +1,53 @@ +/** @file + Serial Port Console Redirection Table (SPCR) + + Copyright (c) 2017, Linaro Limited. All rights reserved. + Copyright (C) 2018, Marvell International Ltd. and its affiliates. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +#include +#include + +#include "AcpiHeader.h" + +EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D { + __ACPI_HEADER(EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATU= RE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION + ), + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550, //= InterfaceType + { EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE }, //= Reserved1[3] + ARM_GAS32 (FixedPcdGet64(PcdSerialRegisterBase)), //= BaseAddress + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, //= InterruptType + 0, //= Irq + 51, //= GlobalSystemInterrupt + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, //= BaudRate + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, //= Parity + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, //= StopBits + 0, //= FlowControl + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, //= TerminalType + EFI_ACPI_RESERVED_BYTE, //= Language + 0xFFFF, //= PciDeviceId + 0xFFFF, //= PciVendorId + 0, //= PciBusNumber + 0, //= PciDeviceNumber + 0, //= PciFunctionNumber + 0, //= PciFlags + 0, //= PciSegment + EFI_ACPI_RESERVED_DWORD //= Reserved2 +}; + +VOID CONST * CONST ReferenceAcpiTable =3D &Spcr; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel