[PATCH] ARM: imx: mach-imx6ul: added gpr enet<x>-tx-clock config

Pieter Cardoen posted 1 patch 2 weeks, 5 days ago
arch/arm/boot/dts/imx6ul.dtsi   |  1 +
arch/arm/mach-imx/mach-imx6ul.c | 15 ++++++++++++++-
2 files changed, 15 insertions(+), 1 deletion(-)

[PATCH] ARM: imx: mach-imx6ul: added gpr enet<x>-tx-clock config

Posted by Pieter Cardoen 2 weeks, 5 days ago
Allow enable/disable of IMX6UL_GPR1_ENET1_CLK_OUTPUT and
IMX6UL_GPR2_ENET_CLK_OUTPUT as it may not be enabled when
using a phy in RMII mode. Enabling this clock output in
RMII mode results in multiple drivers on a single line.

Configuration can be done using gpr device-tree handle by
including string options enet1-tx-clock and enet2-tx-clock.

Signed-off-by: Pieter Cardoen <p.cardoen@televic.com>
---
 arch/arm/boot/dts/imx6ul.dtsi   |  1 +
 arch/arm/mach-imx/mach-imx6ul.c | 15 ++++++++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 7901494..f4dbde8 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -737,6 +737,7 @@
 				compatible = "fsl,imx6ul-iomuxc-gpr",
 					     "fsl,imx6q-iomuxc-gpr", "syscon";
 				reg = <0x020e4000 0x4000>;
+				enet1-tx-clock = "enable";
 			};
 
 			gpt2: timer@20e8000 {
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
index 35e8120..ea2fae8 100644
--- a/arch/arm/mach-imx/mach-imx6ul.c
+++ b/arch/arm/mach-imx/mach-imx6ul.c
@@ -19,11 +19,24 @@
 static void __init imx6ul_enet_clk_init(void)
 {
 	struct regmap *gpr;
+	unsigned int enet_clk_output = 0;
+	struct device_node *node = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-iomuxc-gpr");
+	const char *enable;
+
+	if (node) {
+		if (!of_property_read_string(node, "enet1-tx-clock", &enable))
+			if (strcmp(enable, "enable") == 0)
+				enet_clk_output |= IMX6UL_GPR1_ENET_CLK_OUTPUT;
+
+		if (!of_property_read_string(node, "enet2-tx-clock", &enable))
+			if (strcmp(enable, "enable") == 0)
+				enet_clk_output |= IMX6UL_GPR1_ENET2_CLK_OUTPUT;
+	}
 
 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
 	if (!IS_ERR(gpr))
 		regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
-				   IMX6UL_GPR1_ENET_CLK_OUTPUT);
+				   enet_clk_output);
 	else
 		pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
 }
-- 
2.7.4

[PATCH] ARM: imx: mach-imx6ul: support ptp and rmii clock from pad

Posted by Pieter Cardoen 2 weeks, 5 days ago
On imx6ul, the ENET RMII and PTP clock can come from either internal
ANATOP/CCM or external clock source through pad ENET1_TX_CLK.  But in case
of the external clock source, bit IOMUXC_GPR1[21] needs to be cleared.

The patch adds the support for systems that use an external clock source
and distinguishes above two cases by checking if the PTP clock specified
in device tree is the one coming from the internal ANATOP/CCM.

Signed-off-by: Pieter Cardoen <p.cardoen@televic.com>
---
 arch/arm/mach-imx/mach-imx6ul.c | 44 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 41 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
index 35e8120..70d82cf 100644
--- a/arch/arm/mach-imx/mach-imx6ul.c
+++ b/arch/arm/mach-imx/mach-imx6ul.c
@@ -2,6 +2,7 @@
 /*
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
  */
+#include <linux/clk.h>
 #include <linux/irqchip.h>
 #include <linux/mfd/syscon.h>
 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
@@ -18,14 +19,51 @@
 
 static void __init imx6ul_enet_clk_init(void)
 {
+	struct device_node *np;
+	struct clk *ptp_clk;
+	struct clk *enet_ref;
 	struct regmap *gpr;
+	u32 clksel;
 
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-fec");
+	if (!np) {
+		pr_warn("%s: failed to find fec node\n", __func__);
+		return;
+	}
+
+	ptp_clk = of_clk_get(np, 2);
+	if (IS_ERR(ptp_clk)) {
+		pr_warn("%s: failed to get ptp clock\n", __func__);
+		goto put_node;
+	}
+
+	enet_ref = clk_get_sys(NULL, "enet_ref");
+	if (IS_ERR(enet_ref)) {
+		pr_warn("%s: failed to get enet clock\n", __func__);
+		goto put_ptp_clk;
+	}
+
+	/*
+	 * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
+	 * set bit IOMUXC_GPR1[21].  Or the PTP clock must be from pad
+	 * (external OSC), and we need to clear the bit.
+	 */
+	clksel = clk_is_match(ptp_clk, enet_ref) ?
+				IMX6Q_GPR1_ENET_CLK_SEL_ANATOP :
+				IMX6Q_GPR1_ENET_CLK_SEL_PAD;
 	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
 	if (!IS_ERR(gpr))
-		regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
-				   IMX6UL_GPR1_ENET_CLK_OUTPUT);
+		regmap_update_bits(gpr, IOMUXC_GPR1,
+				IMX6Q_GPR1_ENET_CLK_SEL_MASK,
+				clksel);
 	else
-		pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
+		pr_err("failed to find fsl,imx6ul-iomuxc-gpr regmap\n");
+
+	clk_put(enet_ref);
+put_ptp_clk:
+	clk_put(ptp_clk);
+put_node:
+	of_node_put(np);
 }
 
 static inline void imx6ul_enet_init(void)
-- 
2.7.4