From nobody Sat Dec 28 10:06:38 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1495613211771723.399662051363; Wed, 24 May 2017 01:06:51 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B966E219FFEE2; Wed, 24 May 2017 01:06:48 -0700 (PDT) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F0B3821AE3CD8 for ; Wed, 24 May 2017 01:06:45 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 May 2017 01:06:45 -0700 Received: from jfan12-desk.ccr.corp.intel.com ([10.239.158.57]) by FMSMGA003.fm.intel.com with ESMTP; 24 May 2017 01:06:44 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,385,1491289200"; d="scan'208";a="860723886" From: Jeff Fan To: edk2-devel@lists.01.org Date: Wed, 24 May 2017 16:06:17 +0800 Message-Id: <20170524080618.22272-2-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20170524080618.22272-1-jeff.fan@intel.com> References: <20170524080618.22272-1-jeff.fan@intel.com> Subject: [edk2] [PATCH 1/2] UefiCpuPkg/CpuCommonFeaturesLib: Support X2APIC enable X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael D Kinney , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Current X2APIC is enabled in MpInitLib (used by CpuMpPei and CpuDxe) to fol= low SDM suggestion. That means we only enable X2APIC if we found there are any initial CPU ID value >=3D 255. This patch is to provide one chance for platform to enable X2APIC even ther= e is no any initial CPU ID value >=3D 255. Cc: Michael D Kinney Cc: Eric Dong Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 +++++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | 2 +- UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c | 76 ++++++++++++++++++= +--- 3 files changed, 82 insertions(+), 11 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/= UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index aa6d112..9a7afed 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -798,6 +798,21 @@ C1eInitialize ( ); =20 /** + Prepares for the data used by CPU feature detection and initialization. + + @param[in] NumberOfProcessors The number of CPUs in the platform. + + @return Pointer to a buffer of CPU related configuration data. + + @note This service could be called by BSP only. +**/ +VOID * +EFIAPI +X2ApicGetConfigData ( + IN UINTN NumberOfProcessors + ); + +/** Detects if X2Apci feature supported on current processor. =20 Detect if X2Apci has been already enabled. diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c= b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index 3390aa8..793a095 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -211,7 +211,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) { Status =3D RegisterCpuFeature ( "X2Apic", - NULL, + X2ApicGetConfigData, X2ApicSupport, X2ApicInitialize, CPU_FEATURE_X2APIC, diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c b/UefiCpuPkg/= Library/CpuCommonFeaturesLib/X2Apic.c index 9c2ad9a..03d42a3 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c @@ -15,6 +15,28 @@ #include "CpuCommonFeatures.h" =20 /** + Prepares for the data used by CPU feature detection and initialization. + + @param[in] NumberOfProcessors The number of CPUs in the platform. + + @return Pointer to a buffer of CPU related configuration data. + + @note This service could be called by BSP only. +**/ +VOID * +EFIAPI +X2ApicGetConfigData ( + IN UINTN NumberOfProcessors + ) +{ + BOOLEAN *ConfigData; + + ConfigData =3D AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors); + ASSERT (ConfigData !=3D NULL); + return ConfigData; +} + +/** Detects if X2Apci feature supported on current processor. =20 Detect if X2Apci has been already enabled. @@ -39,8 +61,17 @@ X2ApicSupport ( IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL ) -{ - return (GetApicMode () =3D=3D LOCAL_APIC_MODE_X2APIC); +{ =20 + BOOLEAN *X2ApicEnabled; + + ASSERT (ConfigData !=3D NULL); + X2ApicEnabled =3D (BOOLEAN *) ConfigData; + // + // *ConfigData indicates if X2APIC enabled on current processor + // + X2ApicEnabled[ProcessorNumber] =3D (GetApicMode () =3D=3D LOCAL_APIC_MOD= E_X2APIC) ? TRUE : FALSE; + + return (CpuInfo->CpuIdVersionInfoEcx.Bits.x2APIC =3D=3D 1); } =20 /** @@ -69,13 +100,38 @@ X2ApicInitialize ( IN BOOLEAN State ) { - PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_APIC_BASE, - MSR_IA32_APIC_BASE_REGISTER, - Bits.EXTD, - (State) ? 1 : 0 - ); + BOOLEAN *X2ApicEnabled; + + ASSERT (ConfigData !=3D NULL); + X2ApicEnabled =3D (BOOLEAN *) ConfigData; + if (X2ApicEnabled[ProcessorNumber]) { + if (!State) { + DEBUG ((DEBUG_ERROR, "X2APIC should be enabled by PcdCpuFeaturesUser= Configuration!\n")); + ASSERT (FALSE); + } else { + PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_APIC_BASE, + MSR_IA32_APIC_BASE_REGISTER, + Bits.EXTD, + 1 + ); + } + } else { + if (State) { + // + //=20 + // + CPU_REGISTER_TABLE_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_APIC_BASE, + MSR_IA32_APIC_BASE_REGISTER, + Bits.EXTD, + 1 + ); + } + } return RETURN_SUCCESS; } --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Dec 28 10:06:38 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1495613213274364.73355679370275; Wed, 24 May 2017 01:06:53 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E9EC0219FFEF6; Wed, 24 May 2017 01:06:48 -0700 (PDT) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E7459219FFEF2 for ; Wed, 24 May 2017 01:06:46 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 May 2017 01:06:46 -0700 Received: from jfan12-desk.ccr.corp.intel.com ([10.239.158.57]) by FMSMGA003.fm.intel.com with ESMTP; 24 May 2017 01:06:45 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,385,1491289200"; d="scan'208";a="860723890" From: Jeff Fan To: edk2-devel@lists.01.org Date: Wed, 24 May 2017 16:06:18 +0800 Message-Id: <20170524080618.22272-3-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20170524080618.22272-1-jeff.fan@intel.com> References: <20170524080618.22272-1-jeff.fan@intel.com> Subject: [edk2] [PATCH 2/2] UefiCpuPkg/MpInitLib: Check APIC mode change around AP function X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael D Kinney , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" If APIC ID values are changed during AP functions execution, we need to upd= ate new APIC ID values in local data structure accordingly. But if APIC mode change happened during AP function execution, we do not su= pport APIC ID value changed. Cc: Michael D Kinney Cc: Eric Dong Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 735e099..c6f8191 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -547,6 +547,7 @@ ApWakeupFunction ( volatile UINT32 *ApStartupSignalBuffer; CPU_INFO_IN_HOB *CpuInfoInHob; UINT64 ApTopOfStack; + UINTN CurrentApicMode; =20 // // AP finished assembly code and begin to execute C code @@ -560,6 +561,7 @@ ApWakeupFunction ( ProgramVirtualWireMode (); SyncLocalApicTimerSetting (CpuMpData); =20 + CurrentApicMode =3D GetApicMode (); while (TRUE) { if (CpuMpData->InitFlag =3D=3D ApInitConfig) { // @@ -627,11 +629,23 @@ ApWakeupFunction ( ApStartupSignalBuffer =3D CpuMpData->CpuData[ProcessorNumber].= StartupApSignal; CpuInfoInHob[ProcessorNumber].ApTopOfStack =3D CpuInfoInHob[Cp= uMpData->NewBspNumber].ApTopOfStack; } else { - // - // Re-get the CPU APICID and Initial APICID - // - CpuInfoInHob[ProcessorNumber].ApicId =3D GetApicId (); - CpuInfoInHob[ProcessorNumber].InitialApicId =3D GetInitialApic= Id (); + if (CpuInfoInHob[ProcessorNumber].ApicId !=3D GetApicId () || + CpuInfoInHob[ProcessorNumber].InitialApicId !=3D GetInitia= lApicId ()) { + if (CurrentApicMode !=3D GetApicMode ()) { + // + // If APIC mode change happened during AP function executi= on, + // we do not support APIC ID value changed. + // + ASSERT (FALSE); + CpuDeadLoop (); + } else { + // + // Re-get the CPU APICID and Initial APICID if they are ch= anged + // + CpuInfoInHob[ProcessorNumber].ApicId =3D GetApicId = (); + CpuInfoInHob[ProcessorNumber].InitialApicId =3D GetInitial= ApicId (); + } + } } } SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateFinished= ); --=20 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel