From nobody Fri Dec 27 20:39:21 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1496942023239554.8826140119427; Thu, 8 Jun 2017 10:13:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8C1A221967BEB; Thu, 8 Jun 2017 10:12:31 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2AE8720082E76 for ; Thu, 8 Jun 2017 10:12:29 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E8F64C01CB8B; Thu, 8 Jun 2017 17:13:37 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-122.phx2.redhat.com [10.3.116.122]) by smtp.corp.redhat.com (Postfix) with ESMTP id 262447F1C3; Thu, 8 Jun 2017 17:13:36 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com E8F64C01CB8B Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com E8F64C01CB8B From: Laszlo Ersek To: edk2-devel-01 Date: Thu, 8 Jun 2017 19:13:29 +0200 Message-Id: <20170608171333.17937-2-lersek@redhat.com> In-Reply-To: <20170608171333.17937-1-lersek@redhat.com> References: <20170608171333.17937-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Thu, 08 Jun 2017 17:13:38 +0000 (UTC) Subject: [edk2] [PATCH 1/5] OvmfPkg: introduce Q35TsegSizeLib (class header and sole lib instance) X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" OvmfPkg contains three modules that work with the TSEG (SMRAM) size: PlatformPei (PEIM), SmmAccessPei (PEIM), and SmmAccess2Dxe (DXE_DRIVER). These modules open-code the interpretation of the ESMRAMC register's TSEG_SZ bit-field. That is OK as long as we stick with the Q35 hardware spec and nothing more, but it makes it difficult to benefit from an upcoming QEMU feature, namely extended TSEG sizes. Introduce the Q35TsegSizeLib class, and its sole lib instance, for extracting / centralizing TSEG size querying and interpretation. This library instance is self contained and does not consume dynamic PCDs (for example, it doesn't consume PcdOvmfHostBridgePciDevId), because such PCDs tend to be set in PlatformPei, but the dispatch order between PlatformPei and SmmAccessPei is unspecified (both have TRUE for DEPEX). In the next few patches we're going to rebase the three listed modules to Q35TsegSizeLib. As introduced, the library instance only captures the currently supported TSEG sizes. Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/OvmfPkg.dec | 5 + OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.inf | 47 +++++ OvmfPkg/Include/Library/Q35TsegSizeLib.h | 74 ++++++++ OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.c | 186 ++++++++++++++++++= ++ 7 files changed, 315 insertions(+) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 5627be0bab0a..7b9220369b95 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -27,14 +27,19 @@ [LibraryClasses] # LoadLinuxLib|Include/Library/LoadLinuxLib.h =20 ## @libraryclass Save and restore variables using a file # NvVarsFileLib|Include/Library/NvVarsFileLib.h =20 + ## @libraryclass Utility library to query TSEG size-related quantities= on + # Q35. + # + Q35TsegSizeLib|Include/Library/Q35TsegSizeLib.h + ## @libraryclass Access QEMU's firmware configuration interface # QemuFwCfgLib|Include/Library/QemuFwCfgLib.h =20 ## @libraryclass S3 support for QEMU fw_cfg # QemuFwCfgS3Lib|Include/Library/QemuFwCfgS3Lib.h diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 0647f346257a..8917c2f7b085 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -129,14 +129,15 @@ [LibraryClasses] UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf NvVarsFileLib|OvmfPkg/Library/NvVarsFileLib/NvVarsFileLib.inf + Q35TsegSizeLib|OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.inf FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 1182b1858a7d..56e9c5b790d7 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -134,14 +134,15 @@ [LibraryClasses] UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf NvVarsFileLib|OvmfPkg/Library/NvVarsFileLib/NvVarsFileLib.inf + Q35TsegSizeLib|OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.inf FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 636dfb1b5638..618b72bffa80 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -134,14 +134,15 @@ [LibraryClasses] UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf NvVarsFileLib|OvmfPkg/Library/NvVarsFileLib/NvVarsFileLib.inf + Q35TsegSizeLib|OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.inf FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf diff --git a/OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.inf b/OvmfPkg/Li= brary/Q35TsegSizeLib/Q35TsegSizeLib.inf new file mode 100644 index 000000000000..8f99e55b8c48 --- /dev/null +++ b/OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.inf @@ -0,0 +1,47 @@ +## @file +# Utility library to query TSEG size-related quantities on Q35. +# +# Copyright (C) 2017, Red Hat, Inc. +# +# This program and the accompanying materials are licensed and made availa= ble +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT +# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +## + +[Defines] + INF_VERSION =3D 1.25 + BASE_NAME =3D Q35TsegSizeLib + FILE_GUID =3D 6019578F-0078-46D4-86EE-06C486A304D2 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D Q35TsegSizeLib|PEIM DXE_DRIVER + +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources] + Q35TsegSizeLib.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + PcdLib + PciLib + +[FeaturePcd] + gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire + +[FixedPcd] + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes diff --git a/OvmfPkg/Include/Library/Q35TsegSizeLib.h b/OvmfPkg/Include/Lib= rary/Q35TsegSizeLib.h new file mode 100644 index 000000000000..580ef6887931 --- /dev/null +++ b/OvmfPkg/Include/Library/Q35TsegSizeLib.h @@ -0,0 +1,74 @@ +/** @file + Utility library to query TSEG size-related quantities on Q35. + + Copyright (C) 2017, Red Hat, Inc. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __Q35_TSEG_SIZE_LIB__ +#define __Q35_TSEG_SIZE_LIB__ + +/** + Query the preferred size of TSEG, in megabytes. + + The caller is responsible for calling this function only on the Q35 boar= d. If + the function is called on another board, the function logs an informative + error message and does not return. + + @return The preferred size of TSEG, expressed in megabytes. +**/ +UINT16 +EFIAPI +Q35TsegSizeGetPreferredMbytes ( + VOID + ); + +/** + Query the ESMRAMC.TSEG_SZ bit-field value that corresponds to the prefer= red + TSEG size. + + The caller is responsible for calling this function only on the Q35 boar= d. If + the function is called on another board, the function logs an informative + error message and does not return. + + @return The ESMRAMC.TSEG_SZ bit-field value that corresponds to the + preferred TSEG size. The return value is a subset of + MCH_ESMRAMC_TSEG_MASK, defined in . +**/ +UINT8 +EFIAPI +Q35TsegSizeGetPreferredEsmramcTsegSzMask ( + VOID + ); + +/** + Extract the TSEG_SZ bit-field from the passed in ESMRAMC register value,= and + return the number of megabytes that it represents. + + The caller is responsible for calling this function only on the Q35 boar= d. If + the function is called on another board, the function logs an informative + error message and does not return. + + @param[in] EsmramcVal The ESMRAMC register value to extract the TSEG_SZ + bit-field from, using MCH_ESMRAMC_TSEG_MASK from + . If the extracted + bit-field cannot be mapped to a MB count, the fun= ction + logs an error message and does not return. + + @return The number of megabytes that the extracted TSEG_SZ bit-field + represents. +**/ +UINT16 +EFIAPI +Q35TsegSizeConvertEsmramcValToMbytes ( + IN UINT8 EsmramcVal + ); + +#endif diff --git a/OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.c b/OvmfPkg/Libr= ary/Q35TsegSizeLib/Q35TsegSizeLib.c new file mode 100644 index 000000000000..db57a8b308de --- /dev/null +++ b/OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.c @@ -0,0 +1,186 @@ +/** @file + Utility library to query TSEG size-related quantities on Q35. + + Copyright (C) 2017, Red Hat, Inc. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#include +#include +#include +#include +#include +#include + +STATIC BOOLEAN mPreferencesInitialized; +STATIC UINT8 mPreferredEsmramcTsegSzMask; + +/** + Fetch the preferences into static variables that are going to be used by= the + public functions of this library instance. + + The Q35 board requirement documented on those interfaces is commonly enf= orced + here. +**/ +STATIC +VOID +Q35TsegSizeGetPreferences ( + VOID + ) +{ + UINT16 HostBridgeDevId; + + if (mPreferencesInitialized) { + return; + } + + // + // This function should only be reached if SMRAM support is required. + // + ASSERT (FeaturePcdGet (PcdSmmSmramRequire)); + + HostBridgeDevId =3D PciRead16 (OVMF_HOSTBRIDGE_DID); + if (HostBridgeDevId !=3D INTEL_Q35_MCH_DEVICE_ID) { + DEBUG (( + DEBUG_ERROR, + "%a: %a: no TSEG (SMRAM) on host bridge DID=3D0x%04x; " + "only DID=3D0x%04x (Q35) is supported\n", + gEfiCallerBaseName, + __FUNCTION__, + HostBridgeDevId, + INTEL_Q35_MCH_DEVICE_ID + )); + ASSERT (FALSE); + CpuDeadLoop (); + } + + mPreferencesInitialized =3D TRUE; + + switch (FixedPcdGet8 (PcdQ35TsegMbytes)) { + case 1: + mPreferredEsmramcTsegSzMask =3D MCH_ESMRAMC_TSEG_1MB; + break; + case 2: + mPreferredEsmramcTsegSzMask =3D MCH_ESMRAMC_TSEG_2MB; + break; + case 8: + mPreferredEsmramcTsegSzMask =3D MCH_ESMRAMC_TSEG_8MB; + break; + default: + ASSERT (FALSE); + } +} + + +/** + Query the preferred size of TSEG, in megabytes. + + The caller is responsible for calling this function only on the Q35 boar= d. If + the function is called on another board, the function logs an informative + error message and does not return. + + @return The preferred size of TSEG, expressed in megabytes. +**/ +UINT16 +EFIAPI +Q35TsegSizeGetPreferredMbytes ( + VOID + ) +{ + // + // Query the ESMRAMC.TSEG_SZ preference and convert it to megabytes. + // + return Q35TsegSizeConvertEsmramcValToMbytes ( + Q35TsegSizeGetPreferredEsmramcTsegSzMask () + ); +} + + +/** + Query the ESMRAMC.TSEG_SZ bit-field value that corresponds to the prefer= red + TSEG size. + + The caller is responsible for calling this function only on the Q35 boar= d. If + the function is called on another board, the function logs an informative + error message and does not return. + + @return The ESMRAMC.TSEG_SZ bit-field value that corresponds to the + preferred TSEG size. The return value is a subset of + MCH_ESMRAMC_TSEG_MASK, defined in . +**/ +UINT8 +EFIAPI +Q35TsegSizeGetPreferredEsmramcTsegSzMask ( + VOID + ) +{ + Q35TsegSizeGetPreferences (); + return mPreferredEsmramcTsegSzMask; +} + + +/** + Extract the TSEG_SZ bit-field from the passed in ESMRAMC register value,= and + return the number of megabytes that it represents. + + The caller is responsible for calling this function only on the Q35 boar= d. If + the function is called on another board, the function logs an informative + error message and does not return. + + @param[in] EsmramcVal The ESMRAMC register value to extract the TSEG_SZ + bit-field from, using MCH_ESMRAMC_TSEG_MASK from + . If the extracted + bit-field cannot be mapped to a MB count, the fun= ction + logs an error message and does not return. + + @return The number of megabytes that the extracted TSEG_SZ bit-field + represents. +**/ +UINT16 +EFIAPI +Q35TsegSizeConvertEsmramcValToMbytes ( + IN UINT8 EsmramcVal + ) +{ + UINT8 TsegSizeBits; + UINT16 Mbytes; + + Q35TsegSizeGetPreferences (); + + TsegSizeBits =3D EsmramcVal & MCH_ESMRAMC_TSEG_MASK; + switch (TsegSizeBits) { + case MCH_ESMRAMC_TSEG_1MB: + Mbytes =3D 1; + break; + case MCH_ESMRAMC_TSEG_2MB: + Mbytes =3D 2; + break; + case MCH_ESMRAMC_TSEG_8MB: + Mbytes =3D 8; + break; + default: + DEBUG (( + DEBUG_ERROR, + "%a: %a: unknown TsegSizeBits=3D0x%02x\n", + gEfiCallerBaseName, + __FUNCTION__, + TsegSizeBits + )); + ASSERT (FALSE); + CpuDeadLoop (); + + // + // Keep compilers happy. + // + Mbytes =3D 0; + } + + return Mbytes; +} --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Dec 27 20:39:21 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1496942024684329.26533956747164; Thu, 8 Jun 2017 10:13:44 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CADD321967BF1; Thu, 8 Jun 2017 10:12:31 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4DB4121967BEB for ; Thu, 8 Jun 2017 10:12:30 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1362189C2A; Thu, 8 Jun 2017 17:13:39 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-122.phx2.redhat.com [10.3.116.122]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4875F7F1C0; Thu, 8 Jun 2017 17:13:38 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 1362189C2A Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 1362189C2A From: Laszlo Ersek To: edk2-devel-01 Date: Thu, 8 Jun 2017 19:13:30 +0200 Message-Id: <20170608171333.17937-3-lersek@redhat.com> In-Reply-To: <20170608171333.17937-1-lersek@redhat.com> References: <20170608171333.17937-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Thu, 08 Jun 2017 17:13:39 +0000 (UTC) Subject: [edk2] [PATCH 2/5] OvmfPkg/PlatformPei: rebase to Q35TsegSizeLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Replace FixedPcdGet8 (PcdQ35TsegMbytes) macro invocations with Q35TsegSizeGetPreferredMbytes () function invocations. This causes no change in observable behavior. Remember that Q35TsegSizeGetPreferredMbytes() -- indirectly -- logs an error and calls CpuDeadLoop() if it is executed on a non-Q35 board. This is safe and intentional, because all the converted call sites are reached only when the PcdSmmSmramRequire Feature PCD is set, for which Q35 has always been a hard requirement. Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/PlatformPei/PlatformPei.inf | 2 +- OvmfPkg/PlatformPei/MemDetect.c | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index a1e12c1fc7e2..6125b52b8466 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -57,14 +57,15 @@ [LibraryClasses] PeiServicesLib PeiServicesTablePointerLib PeimEntryPoint QemuFwCfgLib QemuFwCfgS3Lib MtrrLib PcdLib + Q35TsegSizeLib =20 [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase @@ -78,15 +79,14 @@ [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd - gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index af96a04d194a..795a3f47d12a 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -29,14 +29,15 @@ Module Name: #include #include #include #include #include #include #include +#include =20 #include "Platform.h" #include "Cmos.h" =20 UINT8 mPhysMemAddressWidth; =20 STATIC UINT32 mS3AcpiReservedMemoryBase; @@ -344,15 +345,15 @@ PublishPeiMemory ( UINT32 PeiMemoryCap; =20 LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); if (FeaturePcdGet (PcdSmmSmramRequire)) { // // TSEG is chipped from the end of low RAM // - LowerMemorySize -=3D FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + LowerMemorySize -=3D Q35TsegSizeGetPreferredMbytes () * SIZE_1MB; } =20 // // If S3 is supported, then the S3 permanent PEI memory is placed next, // downwards. Its size is primarily dictated by CpuMpPei. The formula be= low // is an approximation. // @@ -452,15 +453,15 @@ QemuInitializeRam ( // Create memory HOBs // AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); =20 if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; =20 - TsegSize =3D FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + TsegSize =3D Q35TsegSizeGetPreferredMbytes () * SIZE_1MB; AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize, TRUE); } else { AddMemoryRangeHob (BASE_1MB, LowerMemorySize); } =20 @@ -601,15 +602,15 @@ InitializeRamRegions ( if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; =20 // // Make sure the TSEG area that we reported as a reserved memory res= ource // cannot be used for reserved memory allocations. // - TsegSize =3D FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + TsegSize =3D Q35TsegSizeGetPreferredMbytes () * SIZE_1MB; BuildMemoryAllocationHob ( GetSystemMemorySizeBelow4gb() - TsegSize, TsegSize, EfiReservedMemoryType ); } } --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Dec 27 20:39:21 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1496942030770874.1928663903644; Thu, 8 Jun 2017 10:13:50 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0F3CD20082E76; Thu, 8 Jun 2017 10:12:33 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 681CC20082E76 for ; Thu, 8 Jun 2017 10:12:31 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 317FDA6DFC; Thu, 8 Jun 2017 17:13:40 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-122.phx2.redhat.com [10.3.116.122]) by smtp.corp.redhat.com (Postfix) with ESMTP id 666977F1C4; Thu, 8 Jun 2017 17:13:39 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 317FDA6DFC Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 317FDA6DFC From: Laszlo Ersek To: edk2-devel-01 Date: Thu, 8 Jun 2017 19:13:31 +0200 Message-Id: <20170608171333.17937-4-lersek@redhat.com> In-Reply-To: <20170608171333.17937-1-lersek@redhat.com> References: <20170608171333.17937-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Thu, 08 Jun 2017 17:13:40 +0000 (UTC) Subject: [edk2] [PATCH 3/5] OvmfPkg/SmmAccess: rebase code unique to SmmAccessPei to Q35TsegSizeLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" SmmAccessPei and SmmAccess2Dxe share the internals between their PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL implementations, respectively, in "SmramInternal.c". In this patch, convert the code that is unique to SmmAccessPei -- namely SmmAccessPeiEntryPoint() -- to Q35TsegSizeLib client code, as follows: - Replace FixedPcdGet8 (PcdQ35TsegMbytes) macro invocations with Q35TsegSizeGetPreferredMbytes () function calls. - Replace any mapping, from FixedPcdGet8 (PcdQ35TsegMbytes) to MCH_ESMRAMC_TSEG_xMB bitmask macros, with Q35TsegSizeGetPreferredEsmramcTsegSzMask() function calls. This causes no change in observable behavior. After this patch, no module INF file except "OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.inf" refers to PcdQ35TsegMbytes. Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/SmmAccess/SmmAccessPei.inf | 4 +--- OvmfPkg/SmmAccess/SmmAccessPei.c | 7 +++---- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.inf b/OvmfPkg/SmmAccess/SmmAcce= ssPei.inf index 3908b085da3a..c07c603cb663 100644 --- a/OvmfPkg/SmmAccess/SmmAccessPei.inf +++ b/OvmfPkg/SmmAccess/SmmAccessPei.inf @@ -51,19 +51,17 @@ [LibraryClasses] DebugLib HobLib IoLib PcdLib PciLib PeiServicesLib PeimEntryPoint + Q35TsegSizeLib =20 [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire =20 -[FixedPcd] - gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes - [Ppis] gPeiSmmAccessPpiGuid ## PRODUCES =20 [Depex] TRUE diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.c b/OvmfPkg/SmmAccess/SmmAccess= Pei.c index a4ce610a4650..104671a15c64 100644 --- a/OvmfPkg/SmmAccess/SmmAccessPei.c +++ b/OvmfPkg/SmmAccess/SmmAccessPei.c @@ -28,14 +28,15 @@ #include #include #include #include #include #include #include +#include #include =20 #include =20 #include "SmramInternal.h" =20 // @@ -315,25 +316,23 @@ SmmAccessPeiEntryPoint ( PciWrite32 (DRAMC_REGISTER_Q35 (MCH_BGSM), TopOfLowRamMb << MCH_BGSM_MB_SHIFT); =20 // // Set TSEG Memory Base. // PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB), - (TopOfLowRamMb - FixedPcdGet8 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SHI= FT); + (TopOfLowRamMb - Q35TsegSizeGetPreferredMbytes ()) << MCH_TSEGMB_MB_SH= IFT); =20 // // Set TSEG size, and disable TSEG visibility outside of SMM. Note that = the // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility = is // *restricted* to SMM. // EsmramcVal &=3D ~(UINT32)MCH_ESMRAMC_TSEG_MASK; - EsmramcVal |=3D FixedPcdGet8 (PcdQ35TsegMbytes) =3D=3D 8 ? MCH_ESMRAMC_T= SEG_8MB : - FixedPcdGet8 (PcdQ35TsegMbytes) =3D=3D 2 ? MCH_ESMRAMC_TSE= G_2MB : - MCH_ESMRAMC_TSEG_1MB; + EsmramcVal |=3D Q35TsegSizeGetPreferredEsmramcTsegSzMask (); EsmramcVal |=3D MCH_ESMRAMC_T_EN; PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal); =20 // // TSEG should be closed (see above), but unlocked, initially. Set G_SMR= AME // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it. // --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Dec 27 20:39:21 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 14969420314200.16372569126235703; Thu, 8 Jun 2017 10:13:51 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4813121C8D635; Thu, 8 Jun 2017 10:12:34 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 86D5D2094554E for ; Thu, 8 Jun 2017 10:12:32 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 53D38C0586A2; Thu, 8 Jun 2017 17:13:41 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-122.phx2.redhat.com [10.3.116.122]) by smtp.corp.redhat.com (Postfix) with ESMTP id 851FD7F1C3; Thu, 8 Jun 2017 17:13:40 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 53D38C0586A2 Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx07.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 53D38C0586A2 From: Laszlo Ersek To: edk2-devel-01 Date: Thu, 8 Jun 2017 19:13:32 +0200 Message-Id: <20170608171333.17937-5-lersek@redhat.com> In-Reply-To: <20170608171333.17937-1-lersek@redhat.com> References: <20170608171333.17937-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Thu, 08 Jun 2017 17:13:41 +0000 (UTC) Subject: [edk2] [PATCH 4/5] OvmfPkg/SmmAccess: rebase shared PEIM/DXE code to Q35TsegSizeLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" SmmAccessPei and SmmAccess2Dxe share the internals between their PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL implementations, respectively, in "SmramInternal.c". In this patch, convert "SmramInternal.c" to Q35TsegSizeLib client code. Replace any mapping, from MCH_ESMRAMC_TSEG_xMB bitmask macros to byte counts, with (Q35TsegSizeConvertEsmramcValToMbytes (EsmramcVal) * SIZE_1MB) expressions. This causes no change in observable behavior. After this patch, the conversion to Q35TsegSizeLib is complete. Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/SmmAccess/SmmAccess2Dxe.inf | 1 + OvmfPkg/SmmAccess/SmramInternal.c | 13 ++++++------- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf b/OvmfPkg/SmmAccess/SmmAcc= ess2Dxe.inf index 31e4dfa02991..f591b837bb62 100644 --- a/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf +++ b/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf @@ -41,14 +41,15 @@ [Packages] MdePkg/MdePkg.dec OvmfPkg/OvmfPkg.dec =20 [LibraryClasses] DebugLib PcdLib PciLib + Q35TsegSizeLib UefiBootServicesTableLib UefiDriverEntryPoint =20 [Protocols] gEfiSmmAccess2ProtocolGuid ## PRODUCES =20 [FeaturePcd] diff --git a/OvmfPkg/SmmAccess/SmramInternal.c b/OvmfPkg/SmmAccess/SmramInt= ernal.c index c3267ca94031..e7a7acbf1f8b 100644 --- a/OvmfPkg/SmmAccess/SmramInternal.c +++ b/OvmfPkg/SmmAccess/SmramInternal.c @@ -14,14 +14,15 @@ =20 **/ =20 #include #include #include #include +#include =20 #include "SmramInternal.h" =20 /** Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL ob= ject, from the D_LCK and T_EN bits. @@ -128,15 +129,15 @@ SmramAccessGetCapabilities ( IN OUT UINTN *SmramMapSize, IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap ) { UINTN OriginalSize; UINT32 TsegMemoryBaseMb, TsegMemoryBase; UINT64 CommonRegionState; - UINT8 TsegSizeBits; + UINT8 EsmramcVal; =20 OriginalSize =3D *SmramMapSize; *SmramMapSize =3D DescIdxCount * sizeof *SmramMap; if (OriginalSize < *SmramMapSize) { return EFI_BUFFER_TOO_SMALL; } =20 @@ -162,27 +163,25 @@ SmramAccessGetCapabilities ( SmramMap[DescIdxSmmS3ResumeState].CpuStart =3D TsegMemoryBase; SmramMap[DescIdxSmmS3ResumeState].PhysicalSize =3D EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (sizeof (SMM_S3_RESUME_STATE))); SmramMap[DescIdxSmmS3ResumeState].RegionState =3D CommonRegionState | EFI_ALLOCATED; =20 // - // Get the TSEG size bits from the ESMRAMC register. + // Read the ESMRAMC register so we can extract the TSEG size bits. // - TsegSizeBits =3D PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC)) & - MCH_ESMRAMC_TSEG_MASK; + EsmramcVal =3D PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC)); =20 // // The second region is the main one, following the first. // SmramMap[DescIdxMain].PhysicalStart =3D SmramMap[DescIdxSmmS3ResumeState].PhysicalStart + SmramMap[DescIdxSmmS3ResumeState].PhysicalSize; SmramMap[DescIdxMain].CpuStart =3D SmramMap[DescIdxMain].PhysicalStart; SmramMap[DescIdxMain].PhysicalSize =3D - (TsegSizeBits =3D=3D MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB : - TsegSizeBits =3D=3D MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB : - SIZE_1MB) - SmramMap[DescIdxSmmS3ResumeState].PhysicalSize; + (Q35TsegSizeConvertEsmramcValToMbytes (EsmramcVal) * SIZE_1MB) - + SmramMap[DescIdxSmmS3ResumeState].PhysicalSize; SmramMap[DescIdxMain].RegionState =3D CommonRegionState; =20 return EFI_SUCCESS; } --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Dec 27 20:39:21 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1496942035798178.2771462232813; Thu, 8 Jun 2017 10:13:55 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7DC632094554F; Thu, 8 Jun 2017 10:12:35 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 16CD92095CC77 for ; Thu, 8 Jun 2017 10:12:34 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id CD97680C38; Thu, 8 Jun 2017 17:13:42 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-122.phx2.redhat.com [10.3.116.122]) by smtp.corp.redhat.com (Postfix) with ESMTP id A74337F1CB; Thu, 8 Jun 2017 17:13:41 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com CD97680C38 Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx02.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com CD97680C38 From: Laszlo Ersek To: edk2-devel-01 Date: Thu, 8 Jun 2017 19:13:33 +0200 Message-Id: <20170608171333.17937-6-lersek@redhat.com> In-Reply-To: <20170608171333.17937-1-lersek@redhat.com> References: <20170608171333.17937-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Thu, 08 Jun 2017 17:13:43 +0000 (UTC) Subject: [edk2] [PATCH 5/5] OvmfPkg/Q35TsegSizeLib: recognize an extended TSEG when QEMU offers it X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch interfaces with the QEMU feature introduced in QEMU patch q35/mch: implement extended TSEG sizes Excerpt: > The q35 machine type currently lets the guest firmware select a 1MB, 2MB > or 8MB TSEG (basically, SMRAM) size. In edk2/OVMF, we use 8MB, but even > that is not enough when a lot of VCPUs (more than approx. 224) are > configured -- SMRAM footprint scales largely proportionally with VCPU > count. > > Introduce a new property for "mch" called "extended-tseg-mbytes", which > expresses (in megabytes) the user's choice of TSEG (SMRAM) size. > > Invent a new, QEMU-specific register in the config space of the DRAM > Controller, at offset 0x50, in order to allow guest firmware to query > the TSEG (SMRAM) size. > > According to Intel Document Number 316966-002, Table 5-1 "DRAM > Controller Register Address Map (D0:F0)": > > [...] > > Offsets 0x50 and 0x51 are not listed in Table 5-1. They are also not > part of the standard PCI config space header. And they precede the > capability list as well, which starts at 0xe0 for this device. > > When the guest writes value 0xffff to this register, the value that can > be read back is that of "mch.extended-tseg-mbytes" -- unless it remains > 0xffff. The guest is required to write 0xffff first (as opposed to a > read-only register) because PCI config space is generally not cleared on > QEMU reset, and after S3 resume or reboot, new guest firmware running on > old QEMU could read a guest OS-injected value from this register. > > After reading the available "extended" TSEG size, the guest firmware may > actually request that TSEG size by writing pattern 11b to the ESMRAMC > register's TSEG_SZ bit-field. (The Intel spec referenced above defines > only patterns 00b (1MB), 01b (2MB) and 10b (8MB); 11b is reserved.) > > On the QEMU command line, the value can be set with > > -global mch.extended-tseg-mbytes=3DN > > The default value for 2.10+ q35 machine types is 16. [...] Users are > responsible for choosing sensible TSEG sizes. > > On 2.9 and earlier q35 machine types, the default value is 0. This lets > the 11b bit pattern in ESMRAMC.TSEG_SZ, and the register at offset 0x50, > keep their original behavior. Relegate PcdQ35TsegMbytes to a fallback role, renaming it to PcdQ35TsegDefaultMbytes. Cc: Jordan Justen Ref: https://bugzilla.redhat.com/show_bug.cgi?id=3D1447027 Ref: https://lists.01.org/pipermail/edk2-devel/2017-May/010456.html Ref: http://mid.mail-archive.com/20170608161013.17920-1-lersek@redhat.com Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/OvmfPkg.dec | 8 ++-- OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.inf | 2 +- OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 4 ++ OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.c | 46 +++++++++++++++++++- 4 files changed, 55 insertions(+), 5 deletions(-) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 7b9220369b95..2cae6a189d62 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -92,19 +92,21 @@ [PcdsFixedAtBuild] # MaxTarget and MaxLun, independently, should the host report higher va= lues, # so that scanning the number of devices given by their product is still # acceptably fast. gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6 gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7 =20 ## The following setting controls how many megabytes we configure as TSE= G on - # Q35, for SMRAM purposes. Permitted values are: 1, 2, 8. Other values = cause - # undefined behavior. + # Q35, for SMRAM purposes, by default. Permitted values are: 1, 2, 8. O= ther + # values cause undefined behavior. # # This PCD is only consulted if PcdSmmSmramRequire is TRUE (see below). - gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT8|0x20 + # Furthermore, if QEMU offers an extended TSEG (as a Q35 extension), th= en + # this PCD is ignored. + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegDefaultMbytes|8|UINT8|0x20 =20 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|= 0x8 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|= 0x9 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|= 0xc gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|= 0xd diff --git a/OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.inf b/OvmfPkg/Li= brary/Q35TsegSizeLib/Q35TsegSizeLib.inf index 8f99e55b8c48..b7467d1a716c 100644 --- a/OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.inf +++ b/OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.inf @@ -40,8 +40,8 @@ [LibraryClasses] PcdLib PciLib =20 [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire =20 [FixedPcd] - gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegDefaultMbytes diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Includ= e/IndustryStandard/Q35MchIch9.h index f480455ae432..68485bec71f7 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -29,14 +29,17 @@ #define INTEL_Q35_MCH_DEVICE_ID 0x29C0 =20 // // B/D/F/Type: 0/0/0/PCI // #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset)) =20 +#define MCH_EXT_TSEG_MB 0x50 +#define MCH_EXT_TSEG_MB_QUERY 0xFFFF + #define MCH_GGC 0x52 #define MCH_GGC_IVD BIT1 =20 #define MCH_PCIEXBAR_LOW 0x60 #define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF #define MCH_PCIEXBAR_BUS_FF 0 #define MCH_PCIEXBAR_EN BIT0 @@ -50,14 +53,15 @@ =20 #define MCH_ESMRAMC 0x9E #define MCH_ESMRAMC_H_SMRAME BIT7 #define MCH_ESMRAMC_E_SMERR BIT6 #define MCH_ESMRAMC_SM_CACHE BIT5 #define MCH_ESMRAMC_SM_L1 BIT4 #define MCH_ESMRAMC_SM_L2 BIT3 +#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1) #define MCH_ESMRAMC_TSEG_8MB BIT2 #define MCH_ESMRAMC_TSEG_2MB BIT1 #define MCH_ESMRAMC_TSEG_1MB 0 #define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1) #define MCH_ESMRAMC_T_EN BIT0 =20 #define MCH_GBSM 0xA4 diff --git a/OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.c b/OvmfPkg/Libr= ary/Q35TsegSizeLib/Q35TsegSizeLib.c index db57a8b308de..01054a093f51 100644 --- a/OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.c +++ b/OvmfPkg/Library/Q35TsegSizeLib/Q35TsegSizeLib.c @@ -17,14 +17,15 @@ #include #include #include #include =20 STATIC BOOLEAN mPreferencesInitialized; STATIC UINT8 mPreferredEsmramcTsegSzMask; +STATIC UINT16 mExtendedTsegMbytes; =20 /** Fetch the preferences into static variables that are going to be used by= the public functions of this library instance. =20 The Q35 board requirement documented on those interfaces is commonly enf= orced here. @@ -59,15 +60,49 @@ Q35TsegSizeGetPreferences ( )); ASSERT (FALSE); CpuDeadLoop (); } =20 mPreferencesInitialized =3D TRUE; =20 - switch (FixedPcdGet8 (PcdQ35TsegMbytes)) { + // + // Check if QEMU offers an extended TSEG. + // + // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TS= EG_MB + // register, and reading back the register. + // + // On a QEMU machine type that does not offer an extended TSEG, the init= ial + // write overwrites whatever value a malicious guest OS may have placed = in + // the (unimplemented) register, before entering S3 or rebooting. + // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged. + // + // On a QEMU machine type that offers an extended TSEG, the initial write + // triggers an update to the register. Subsequently, the value read back + // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us t= he + // number of megabytes. + // + PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY); + mExtendedTsegMbytes =3D PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB)); + if (mExtendedTsegMbytes !=3D MCH_EXT_TSEG_MB_QUERY) { + DEBUG (( + DEBUG_INFO, + "%a: %a: QEMU offers an extended TSEG (%d MB)\n", + gEfiCallerBaseName, + __FUNCTION__, + mExtendedTsegMbytes + )); + + mPreferredEsmramcTsegSzMask =3D MCH_ESMRAMC_TSEG_EXT; + return; + } + + // + // Fall back to the default TSEG size otherwise. + // + switch (FixedPcdGet8 (PcdQ35TsegDefaultMbytes)) { case 1: mPreferredEsmramcTsegSzMask =3D MCH_ESMRAMC_TSEG_1MB; break; case 2: mPreferredEsmramcTsegSzMask =3D MCH_ESMRAMC_TSEG_2MB; break; case 8: @@ -161,14 +196,23 @@ Q35TsegSizeConvertEsmramcValToMbytes ( break; case MCH_ESMRAMC_TSEG_2MB: Mbytes =3D 2; break; case MCH_ESMRAMC_TSEG_8MB: Mbytes =3D 8; break; + case MCH_ESMRAMC_TSEG_EXT: + if (mExtendedTsegMbytes !=3D MCH_EXT_TSEG_MB_QUERY) { + Mbytes =3D mExtendedTsegMbytes; + break; + } + // + // Fall through otherwise -- QEMU didn't offer an extended TSEG, so th= is + // should never happen. + // default: DEBUG (( DEBUG_ERROR, "%a: %a: unknown TsegSizeBits=3D0x%02x\n", gEfiCallerBaseName, __FUNCTION__, TsegSizeBits --=20 2.9.3 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel