In SmmAccessPeiEntryPoint(), map TSEG megabyte counts different from 1, 2
and 8 to the MCH_ESMRAMC_TSEG_EXT bit pattern (introduced in the previous
patch), for the ESMRAMC.TSEG_SZ bit-field register. (Suggested by Jordan.)

In SmramAccessGetCapabilities() -- backing both
PEI_SMM_ACCESS_PPI.GetCapabilities() and
EFI_SMM_ACCESS2_PROTOCOL.GetCapabilities() --, map the
MCH_ESMRAMC_TSEG_EXT bit pattern found in the ESMRAMC.TSEG_SZ bit-field
register to a byte count of (mQ35TsegMbytes * SIZE_1MB).

(MCH_ESMRAMC_TSEG_EXT is the only possible pattern if none of
MCH_ESMRAMC_TSEG_1MB, MCH_ESMRAMC_TSEG_2MB, and MCH_ESMRAMC_TSEG_8MB
match.)

The new code paths are not exercised just yet; for that, PlatformPei is
going to have to set PcdQ35TsegMbytes (and consequently, SmramInternal's
"mQ35TsegMbytes") to a value different from 1, 2, and 8.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
 OvmfPkg/SmmAccess/SmmAccessPei.c  | 3 ++-
 OvmfPkg/SmmAccess/SmramInternal.c | 8 +++++---
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.c b/OvmfPkg/SmmAccess/SmmAccessPei.c
index aba3aeb9f4bd..0d00140dc92f 100644
--- a/OvmfPkg/SmmAccess/SmmAccessPei.c
+++ b/OvmfPkg/SmmAccess/SmmAccessPei.c
@@ -326,15 +326,16 @@ SmmAccessPeiEntryPoint (
   // Set TSEG size, and disable TSEG visibility outside of SMM. Note that the
   // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility is
   // *restricted* to SMM.
   //
   EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;
   EsmramcVal |= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB :
                 mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB :
-                MCH_ESMRAMC_TSEG_1MB;
+                mQ35TsegMbytes == 1 ? MCH_ESMRAMC_TSEG_1MB :
+                MCH_ESMRAMC_TSEG_EXT;
   EsmramcVal |= MCH_ESMRAMC_T_EN;
   PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);
 
   //
   // TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME
   // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it.
   //
diff --git a/OvmfPkg/SmmAccess/SmramInternal.c b/OvmfPkg/SmmAccess/SmramInternal.c
index ae1e9069aca6..fa0efeda72b0 100644
--- a/OvmfPkg/SmmAccess/SmramInternal.c
+++ b/OvmfPkg/SmmAccess/SmramInternal.c
@@ -192,14 +192,16 @@ SmramAccessGetCapabilities (
   // The second region is the main one, following the first.
   //
   SmramMap[DescIdxMain].PhysicalStart =
     SmramMap[DescIdxSmmS3ResumeState].PhysicalStart +
     SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
   SmramMap[DescIdxMain].CpuStart = SmramMap[DescIdxMain].PhysicalStart;
   SmramMap[DescIdxMain].PhysicalSize =
-    (TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB :
-     TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB :
-     SIZE_1MB) - SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
+                             (TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB :
+                              TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB :
+                              TsegSizeBits == MCH_ESMRAMC_TSEG_1MB ? SIZE_1MB :
+                              mQ35TsegMbytes * SIZE_1MB) -
+                             SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
   SmramMap[DescIdxMain].RegionState = CommonRegionState;
 
   return EFI_SUCCESS;
 }
-- 
2.13.1.3.g8be5a757fa67


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