From nobody Fri Dec 27 18:25:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499187400037648.9769454866841; Tue, 4 Jul 2017 09:56:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4CDAA21CF3B88; Tue, 4 Jul 2017 09:54:58 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1404D21CF3B78 for ; Tue, 4 Jul 2017 09:54:57 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0E9E1C0587D4; Tue, 4 Jul 2017 16:56:35 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id 403ED5DC1B; Tue, 4 Jul 2017 16:56:34 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 0E9E1C0587D4 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 0E9E1C0587D4 From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 4 Jul 2017 18:56:22 +0200 Message-Id: <20170704165629.13610-2-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 04 Jul 2017 16:56:35 +0000 (UTC) Subject: [edk2] [PATCH v2 1/8] OvmfPkg: widen PcdQ35TsegMbytes to UINT16 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Widen PcdQ35TsegMbytes to UINT16, in preparation for setting it dynamically to the QEMU-advertized extended TSEG size (which is 16-bits wide). Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/OvmfPkg.dec | 2 +- OvmfPkg/PlatformPei/MemDetect.c | 6 +++--- OvmfPkg/SmmAccess/SmmAccessPei.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 5627be0bab0a..021ac2a77211 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -91,15 +91,15 @@ [PcdsFixedAtBuild] gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7 =20 ## The following setting controls how many megabytes we configure as TSE= G on # Q35, for SMRAM purposes. Permitted values are: 1, 2, 8. Other values = cause # undefined behavior. # # This PCD is only consulted if PcdSmmSmramRequire is TRUE (see below). - gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT8|0x20 + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20 =20 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|= 0x8 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|= 0x9 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|= 0xc gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|= 0xd diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index af96a04d194a..78a8e0de346c 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -344,15 +344,15 @@ PublishPeiMemory ( UINT32 PeiMemoryCap; =20 LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); if (FeaturePcdGet (PcdSmmSmramRequire)) { // // TSEG is chipped from the end of low RAM // - LowerMemorySize -=3D FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + LowerMemorySize -=3D FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB; } =20 // // If S3 is supported, then the S3 permanent PEI memory is placed next, // downwards. Its size is primarily dictated by CpuMpPei. The formula be= low // is an approximation. // @@ -452,15 +452,15 @@ QemuInitializeRam ( // Create memory HOBs // AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); =20 if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; =20 - TsegSize =3D FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + TsegSize =3D FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB; AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize, TRUE); } else { AddMemoryRangeHob (BASE_1MB, LowerMemorySize); } =20 @@ -601,15 +601,15 @@ InitializeRamRegions ( if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; =20 // // Make sure the TSEG area that we reported as a reserved memory res= ource // cannot be used for reserved memory allocations. // - TsegSize =3D FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + TsegSize =3D FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB; BuildMemoryAllocationHob ( GetSystemMemorySizeBelow4gb() - TsegSize, TsegSize, EfiReservedMemoryType ); } } diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.c b/OvmfPkg/SmmAccess/SmmAccess= Pei.c index a4ce610a4650..76790e330f65 100644 --- a/OvmfPkg/SmmAccess/SmmAccessPei.c +++ b/OvmfPkg/SmmAccess/SmmAccessPei.c @@ -315,24 +315,24 @@ SmmAccessPeiEntryPoint ( PciWrite32 (DRAMC_REGISTER_Q35 (MCH_BGSM), TopOfLowRamMb << MCH_BGSM_MB_SHIFT); =20 // // Set TSEG Memory Base. // PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB), - (TopOfLowRamMb - FixedPcdGet8 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SHI= FT); + (TopOfLowRamMb - FixedPcdGet16 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SH= IFT); =20 // // Set TSEG size, and disable TSEG visibility outside of SMM. Note that = the // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility = is // *restricted* to SMM. // EsmramcVal &=3D ~(UINT32)MCH_ESMRAMC_TSEG_MASK; - EsmramcVal |=3D FixedPcdGet8 (PcdQ35TsegMbytes) =3D=3D 8 ? MCH_ESMRAMC_T= SEG_8MB : - FixedPcdGet8 (PcdQ35TsegMbytes) =3D=3D 2 ? MCH_ESMRAMC_TSE= G_2MB : + EsmramcVal |=3D FixedPcdGet16 (PcdQ35TsegMbytes) =3D=3D 8 ? MCH_ESMRAMC_= TSEG_8MB : + FixedPcdGet16 (PcdQ35TsegMbytes) =3D=3D 2 ? MCH_ESMRAMC_TS= EG_2MB : MCH_ESMRAMC_TSEG_1MB; EsmramcVal |=3D MCH_ESMRAMC_T_EN; PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal); =20 // // TSEG should be closed (see above), but unlocked, initially. Set G_SMR= AME // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it. --=20 2.13.1.3.g8be5a757fa67 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Dec 27 18:25:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499187402465923.914359119377; Tue, 4 Jul 2017 09:56:42 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8441221CF3B8C; Tue, 4 Jul 2017 09:54:59 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 330C921CF3B86 for ; Tue, 4 Jul 2017 09:54:58 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2BD9D80462; Tue, 4 Jul 2017 16:56:36 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id 62B5D5D968; Tue, 4 Jul 2017 16:56:35 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 2BD9D80462 Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 2BD9D80462 From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 4 Jul 2017 18:56:23 +0200 Message-Id: <20170704165629.13610-3-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Tue, 04 Jul 2017 16:56:36 +0000 (UTC) Subject: [edk2] [PATCH v2 2/8] OvmfPkg/PlatformPei: prepare for PcdQ35TsegMbytes becoming dynamic X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In one of the next patches we'll turn PcdQ35TsegMbytes into a dynamic PCD, to be set by PlatformPei. Introduce the Q35TsegMbytesInitialization() function and the "mQ35TsegMbytes" global variable to support this. Q35TsegMbytesInitialization() manages the PCD and caches its final value into "mQ35TsegMbytes". Call Q35TsegMbytesInitialization() from InitializePlatform() just in time for the current PCD consumers, PublishPeiMemory(), InitializeRamRegions() and QemuInitializeRam() -- which is called from InitializeRamRegions() -- to be rebased on top of "mQ35TsegMbytes". Call Q35TsegMbytesInitialization() only when PcdSmmSmramRequire is TRUE, given that PcdQ35TsegMbytes is consumed in that case only. Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/PlatformPei/Platform.h | 5 +++++ OvmfPkg/PlatformPei/MemDetect.c | 17 ++++++++++++++--- OvmfPkg/PlatformPei/Platform.c | 4 ++++ 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 18f42c3f0ea8..d2d627b221c4 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -49,14 +49,19 @@ AddReservedMemoryBaseSizeHob ( ); =20 VOID AddressWidthInitialization ( VOID ); =20 +VOID +Q35TsegMbytesInitialization ( + VOID + ); + EFI_STATUS PublishPeiMemory ( VOID ); =20 UINT32 GetSystemMemorySizeBelow4gb ( diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 78a8e0de346c..886d23622665 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -38,14 +38,25 @@ Module Name: #include "Cmos.h" =20 UINT8 mPhysMemAddressWidth; =20 STATIC UINT32 mS3AcpiReservedMemoryBase; STATIC UINT32 mS3AcpiReservedMemorySize; =20 +STATIC UINT16 mQ35TsegMbytes; + +VOID +Q35TsegMbytesInitialization ( + VOID + ) +{ + mQ35TsegMbytes =3D PcdGet16 (PcdQ35TsegMbytes); +} + + UINT32 GetSystemMemorySizeBelow4gb ( VOID ) { UINT8 Cmos0x34; UINT8 Cmos0x35; @@ -344,15 +355,15 @@ PublishPeiMemory ( UINT32 PeiMemoryCap; =20 LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); if (FeaturePcdGet (PcdSmmSmramRequire)) { // // TSEG is chipped from the end of low RAM // - LowerMemorySize -=3D FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB; + LowerMemorySize -=3D mQ35TsegMbytes * SIZE_1MB; } =20 // // If S3 is supported, then the S3 permanent PEI memory is placed next, // downwards. Its size is primarily dictated by CpuMpPei. The formula be= low // is an approximation. // @@ -452,15 +463,15 @@ QemuInitializeRam ( // Create memory HOBs // AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); =20 if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; =20 - TsegSize =3D FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB; + TsegSize =3D mQ35TsegMbytes * SIZE_1MB; AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize, TRUE); } else { AddMemoryRangeHob (BASE_1MB, LowerMemorySize); } =20 @@ -601,15 +612,15 @@ InitializeRamRegions ( if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; =20 // // Make sure the TSEG area that we reported as a reserved memory res= ource // cannot be used for reserved memory allocations. // - TsegSize =3D FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB; + TsegSize =3D mQ35TsegMbytes * SIZE_1MB; BuildMemoryAllocationHob ( GetSystemMemorySizeBelow4gb() - TsegSize, TsegSize, EfiReservedMemoryType ); } } diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 3e9fda7c7ab0..b8a28450d6c5 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -641,14 +641,18 @@ InitializePlatform ( } =20 S3Verification (); BootModeInitialization (); AddressWidthInitialization (); MaxCpuCountInitialization (); =20 + if (FeaturePcdGet (PcdSmmSmramRequire)) { + Q35TsegMbytesInitialization (); + } + PublishPeiMemory (); =20 InitializeRamRegions (); =20 if (mXen) { DEBUG ((EFI_D_INFO, "Xen was detected\n")); InitializeXen (); --=20 2.13.1.3.g8be5a757fa67 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Dec 27 18:25:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499187405122422.80661832740475; Tue, 4 Jul 2017 09:56:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C250221CF3B8F; Tue, 4 Jul 2017 09:54:59 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4A1B021CF3B8A for ; Tue, 4 Jul 2017 09:54:59 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4677A4ACC7; Tue, 4 Jul 2017 16:56:37 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7F0F95DC1B; Tue, 4 Jul 2017 16:56:36 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 4677A4ACC7 Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 4677A4ACC7 From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 4 Jul 2017 18:56:24 +0200 Message-Id: <20170704165629.13610-4-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 04 Jul 2017 16:56:37 +0000 (UTC) Subject: [edk2] [PATCH v2 3/8] OvmfPkg/SmmAccess: prepare for PcdQ35TsegMbytes becoming dynamic X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In one of the next patches we'll turn PcdQ35TsegMbytes into a dynamic PCD, to be set by PlatformPei. Jordan suggested to use gEfiPeiMemoryDiscoveredPpiGuid as SmmAccessPei's DEPEX for making sure that PlatformPei sets the PCD before SmmAccessPei consumes it. (PlatformPei installs the permanent PEI RAM.) Such a DEPEX is supposed to mirror physical firmware, where anything related to SMRAM cannot run before said platform's physical RAM is discovered (signaled by the presence of gEfiPeiMemoryDiscoveredPpiGuid). Introduce the FetchQ35TsegMbytes() function and the "mQ35TsegMbytes" extern variable to "SmramInternal.h" and "SmramInternal.c": - Both SmmAccess modules (PEIM and DXE driver) are supposed to call FetchQ35TsegMbytes() in their respective entry point functions, saving PcdQ35TsegMbytes into "mQ35TsegMbytes". This way dynamic PCD fetches can be kept out of PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions later (when we add support for extended TSEG size). - We can thus replace the current PcdQ35TsegMbytes fetches in SmmAccessPei's entry point function as well, with reads from "mQ35TsegMbytes". Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/SmmAccess/SmmAccess2Dxe.inf | 3 +++ OvmfPkg/SmmAccess/SmmAccessPei.inf | 4 ++-- OvmfPkg/SmmAccess/SmramInternal.h | 13 +++++++++++++ OvmfPkg/SmmAccess/SmmAccess2Dxe.c | 1 + OvmfPkg/SmmAccess/SmmAccessPei.c | 7 ++++--- OvmfPkg/SmmAccess/SmramInternal.c | 17 +++++++++++++++++ 6 files changed, 40 insertions(+), 5 deletions(-) diff --git a/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf b/OvmfPkg/SmmAccess/SmmAcc= ess2Dxe.inf index 31e4dfa02991..1bc88fa050c7 100644 --- a/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf +++ b/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf @@ -50,9 +50,12 @@ [LibraryClasses] =20 [Protocols] gEfiSmmAccess2ProtocolGuid ## PRODUCES =20 [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire =20 +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes + [Depex] TRUE diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.inf b/OvmfPkg/SmmAccess/SmmAcce= ssPei.inf index 3908b085da3a..09f3b63446df 100644 --- a/OvmfPkg/SmmAccess/SmmAccessPei.inf +++ b/OvmfPkg/SmmAccess/SmmAccessPei.inf @@ -55,15 +55,15 @@ [LibraryClasses] PciLib PeiServicesLib PeimEntryPoint =20 [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire =20 -[FixedPcd] +[Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes =20 [Ppis] gPeiSmmAccessPpiGuid ## PRODUCES =20 [Depex] - TRUE + gEfiPeiMemoryDiscoveredPpiGuid diff --git a/OvmfPkg/SmmAccess/SmramInternal.h b/OvmfPkg/SmmAccess/SmramInt= ernal.h index 4e9ac05fad1c..c9c9a7a59d4b 100644 --- a/OvmfPkg/SmmAccess/SmramInternal.h +++ b/OvmfPkg/SmmAccess/SmramInternal.h @@ -27,14 +27,27 @@ // typedef enum { DescIdxSmmS3ResumeState =3D 0, DescIdxMain =3D 1, DescIdxCount =3D 2 } DESCRIPTOR_INDEX; =20 +// +// The value of PcdQ35TsegMbytes is saved into this variable at module sta= rtup. +// +extern UINT16 mQ35TsegMbytes; + +/** + Save PcdQ35TsegMbytes into mQ35TsegMbytes. +**/ +VOID +FetchQ35TsegMbytes ( + VOID + ); + /** Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL ob= ject, from the D_LCK and T_EN bits. =20 PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions can rel= y on the LockState and OpenState fields being up-to-date on entry, and they n= eed diff --git a/OvmfPkg/SmmAccess/SmmAccess2Dxe.c b/OvmfPkg/SmmAccess/SmmAcces= s2Dxe.c index d5130399b030..eaaf96e7e94b 100644 --- a/OvmfPkg/SmmAccess/SmmAccess2Dxe.c +++ b/OvmfPkg/SmmAccess/SmmAccess2Dxe.c @@ -145,12 +145,13 @@ SmmAccess2DxeEntryPoint ( ) { // // This module should only be included if SMRAM support is required. // ASSERT (FeaturePcdGet (PcdSmmSmramRequire)); =20 + FetchQ35TsegMbytes (); GetStates (&mAccess2.LockState, &mAccess2.OpenState); return gBS->InstallMultipleProtocolInterfaces (&ImageHandle, &gEfiSmmAccess2ProtocolGuid, &mAccess2, NULL); } diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.c b/OvmfPkg/SmmAccess/SmmAccess= Pei.c index 76790e330f65..aba3aeb9f4bd 100644 --- a/OvmfPkg/SmmAccess/SmmAccessPei.c +++ b/OvmfPkg/SmmAccess/SmmAccessPei.c @@ -314,25 +314,26 @@ SmmAccessPeiEntryPoint ( TopOfLowRamMb << MCH_GBSM_MB_SHIFT); PciWrite32 (DRAMC_REGISTER_Q35 (MCH_BGSM), TopOfLowRamMb << MCH_BGSM_MB_SHIFT); =20 // // Set TSEG Memory Base. // + FetchQ35TsegMbytes (); PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB), - (TopOfLowRamMb - FixedPcdGet16 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SH= IFT); + (TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT); =20 // // Set TSEG size, and disable TSEG visibility outside of SMM. Note that = the // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility = is // *restricted* to SMM. // EsmramcVal &=3D ~(UINT32)MCH_ESMRAMC_TSEG_MASK; - EsmramcVal |=3D FixedPcdGet16 (PcdQ35TsegMbytes) =3D=3D 8 ? MCH_ESMRAMC_= TSEG_8MB : - FixedPcdGet16 (PcdQ35TsegMbytes) =3D=3D 2 ? MCH_ESMRAMC_TS= EG_2MB : + EsmramcVal |=3D mQ35TsegMbytes =3D=3D 8 ? MCH_ESMRAMC_TSEG_8MB : + mQ35TsegMbytes =3D=3D 2 ? MCH_ESMRAMC_TSEG_2MB : MCH_ESMRAMC_TSEG_1MB; EsmramcVal |=3D MCH_ESMRAMC_T_EN; PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal); =20 // // TSEG should be closed (see above), but unlocked, initially. Set G_SMR= AME // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it. diff --git a/OvmfPkg/SmmAccess/SmramInternal.c b/OvmfPkg/SmmAccess/SmramInt= ernal.c index c3267ca94031..ae1e9069aca6 100644 --- a/OvmfPkg/SmmAccess/SmramInternal.c +++ b/OvmfPkg/SmmAccess/SmramInternal.c @@ -13,18 +13,35 @@ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. =20 **/ =20 #include #include #include +#include #include =20 #include "SmramInternal.h" =20 +// +// The value of PcdQ35TsegMbytes is saved into this variable at module sta= rtup. +// +UINT16 mQ35TsegMbytes; + +/** + Save PcdQ35TsegMbytes into mQ35TsegMbytes. +**/ +VOID +FetchQ35TsegMbytes ( + VOID + ) +{ + mQ35TsegMbytes =3D PcdGet16 (PcdQ35TsegMbytes); +} + /** Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL ob= ject, from the D_LCK and T_EN bits. =20 PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions can rel= y on the LockState and OpenState fields being up-to-date on entry, and they n= eed --=20 2.13.1.3.g8be5a757fa67 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Dec 27 18:25:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499187407762642.6050889443095; Tue, 4 Jul 2017 09:56:47 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 07DAC21CF3B8D; Tue, 4 Jul 2017 09:55:02 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 69FF321CF3B8D for ; Tue, 4 Jul 2017 09:55:00 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6265380F8E; Tue, 4 Jul 2017 16:56:38 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9B3D55D968; Tue, 4 Jul 2017 16:56:37 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 6265380F8E Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 6265380F8E From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 4 Jul 2017 18:56:25 +0200 Message-Id: <20170704165629.13610-5-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Tue, 04 Jul 2017 16:56:38 +0000 (UTC) Subject: [edk2] [PATCH v2 4/8] OvmfPkg: make PcdQ35TsegMbytes dynamic X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" We can now make PcdQ35TsegMbytes dynamic, in preparation for the extended TSEG size feature. At the moment we only move the declaration in OvmfPkg.dec from [PcdsFixedAtBuild] to [PcdsDynamic, PcdsDynamicEx], and provide the dynamic defaults (with the same value, 8) in the DSC files if SMM_REQUIRE is TRUE. Cc: Jordan Justen Suggested-by: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/OvmfPkg.dec | 14 +++++++------- OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 021ac2a77211..c46b72f069ef 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -86,21 +86,14 @@ [PcdsFixedAtBuild] # MaxTarget=3D255 and MaxLun=3D16383. The *inclusive* constants below l= imit # MaxTarget and MaxLun, independently, should the host report higher va= lues, # so that scanning the number of devices given by their product is still # acceptably fast. gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6 gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7 =20 - ## The following setting controls how many megabytes we configure as TSE= G on - # Q35, for SMRAM purposes. Permitted values are: 1, 2, 8. Other values = cause - # undefined behavior. - # - # This PCD is only consulted if PcdSmmSmramRequire is TRUE (see below). - gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20 - gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|= 0x8 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|= 0x9 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|= 0xc gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|= 0xd gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT3= 2|0xe @@ -131,14 +124,21 @@ [PcdsDynamic, PcdsDynamicEx] gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25 =20 ## The 64-bit MMIO aperture shared by all PCI root bridges. # gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27 =20 + ## The following setting controls how many megabytes we configure as TSE= G on + # Q35, for SMRAM purposes. Permitted values are: 1, 2, 8. Other values = cause + # undefined behavior. + # + # This PCD is only consulted if PcdSmmSmramRequire is TRUE (see below). + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20 + [PcdsFeatureFlag] gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0= x1c gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN= |0x1d =20 ## This feature flag enables SMM/SMRAM support. Note that it also requir= es # such support from the underlying QEMU instance; if that support is not # present, the firmware will reject continuing after a certain point. diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 0647f346257a..96f1b126d587 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -530,14 +530,15 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable|FALSE =20 # UefiCpuPkg PCDs related to initial AP bringup and general AP managemen= t. gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64 gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000 =20 !if $(SMM_REQUIRE) =3D=3D TRUE + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x01 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|100000 !endif =20 ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform. diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 1182b1858a7d..2815399b885a 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -538,14 +538,15 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable|FALSE =20 # UefiCpuPkg PCDs related to initial AP bringup and general AP managemen= t. gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64 gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000 =20 !if $(SMM_REQUIRE) =3D=3D TRUE + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x01 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|100000 !endif =20 ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform. diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 636dfb1b5638..b8329d33a9c4 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -537,14 +537,15 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable|FALSE =20 # UefiCpuPkg PCDs related to initial AP bringup and general AP managemen= t. gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64 gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000 =20 !if $(SMM_REQUIRE) =3D=3D TRUE + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x01 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|100000 !endif =20 ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform. --=20 2.13.1.3.g8be5a757fa67 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Dec 27 18:25:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; 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Tue, 4 Jul 2017 16:56:39 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id B64825D968; Tue, 4 Jul 2017 16:56:38 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 7D98061D12 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 7D98061D12 From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 4 Jul 2017 18:56:26 +0200 Message-Id: <20170704165629.13610-6-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 04 Jul 2017 16:56:39 +0000 (UTC) Subject: [edk2] [PATCH v2 5/8] OvmfPkg/IndustryStandard/Q35MchIch9.h: add extended TSEG size macros X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add the macros for interfacing with the QEMU feature added in QEMU commit 2f295167e0c4 ("q35/mch: implement extended TSEG sizes", 2017-06-08). Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Includ= e/IndustryStandard/Q35MchIch9.h index f480455ae432..68485bec71f7 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -29,14 +29,17 @@ #define INTEL_Q35_MCH_DEVICE_ID 0x29C0 =20 // // B/D/F/Type: 0/0/0/PCI // #define DRAMC_REGISTER_Q35(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset)) =20 +#define MCH_EXT_TSEG_MB 0x50 +#define MCH_EXT_TSEG_MB_QUERY 0xFFFF + #define MCH_GGC 0x52 #define MCH_GGC_IVD BIT1 =20 #define MCH_PCIEXBAR_LOW 0x60 #define MCH_PCIEXBAR_LOWMASK 0x0FFFFFFF #define MCH_PCIEXBAR_BUS_FF 0 #define MCH_PCIEXBAR_EN BIT0 @@ -50,14 +53,15 @@ =20 #define MCH_ESMRAMC 0x9E #define MCH_ESMRAMC_H_SMRAME BIT7 #define MCH_ESMRAMC_E_SMERR BIT6 #define MCH_ESMRAMC_SM_CACHE BIT5 #define MCH_ESMRAMC_SM_L1 BIT4 #define MCH_ESMRAMC_SM_L2 BIT3 +#define MCH_ESMRAMC_TSEG_EXT (BIT2 | BIT1) #define MCH_ESMRAMC_TSEG_8MB BIT2 #define MCH_ESMRAMC_TSEG_2MB BIT1 #define MCH_ESMRAMC_TSEG_1MB 0 #define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1) #define MCH_ESMRAMC_T_EN BIT0 =20 #define MCH_GBSM 0xA4 --=20 2.13.1.3.g8be5a757fa67 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Dec 27 18:25:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499187413761108.59204949050559; Tue, 4 Jul 2017 09:56:53 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7A64421CF3B76; Tue, 4 Jul 2017 09:55:04 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A4F5921CF3B97 for ; Tue, 4 Jul 2017 09:55:02 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id A040D285B1; Tue, 4 Jul 2017 16:56:40 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id D3E3C4FA21; Tue, 4 Jul 2017 16:56:39 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com A040D285B1 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com A040D285B1 From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 4 Jul 2017 18:56:27 +0200 Message-Id: <20170704165629.13610-7-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Tue, 04 Jul 2017 16:56:40 +0000 (UTC) Subject: [edk2] [PATCH v2 6/8] OvmfPkg/SmmAccess: support extended TSEG size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In SmmAccessPeiEntryPoint(), map TSEG megabyte counts different from 1, 2 and 8 to the MCH_ESMRAMC_TSEG_EXT bit pattern (introduced in the previous patch), for the ESMRAMC.TSEG_SZ bit-field register. (Suggested by Jordan.) In SmramAccessGetCapabilities() -- backing both PEI_SMM_ACCESS_PPI.GetCapabilities() and EFI_SMM_ACCESS2_PROTOCOL.GetCapabilities() --, map the MCH_ESMRAMC_TSEG_EXT bit pattern found in the ESMRAMC.TSEG_SZ bit-field register to a byte count of (mQ35TsegMbytes * SIZE_1MB). (MCH_ESMRAMC_TSEG_EXT is the only possible pattern if none of MCH_ESMRAMC_TSEG_1MB, MCH_ESMRAMC_TSEG_2MB, and MCH_ESMRAMC_TSEG_8MB match.) The new code paths are not exercised just yet; for that, PlatformPei is going to have to set PcdQ35TsegMbytes (and consequently, SmramInternal's "mQ35TsegMbytes") to a value different from 1, 2, and 8. Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/SmmAccess/SmmAccessPei.c | 3 ++- OvmfPkg/SmmAccess/SmramInternal.c | 8 +++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.c b/OvmfPkg/SmmAccess/SmmAccess= Pei.c index aba3aeb9f4bd..0d00140dc92f 100644 --- a/OvmfPkg/SmmAccess/SmmAccessPei.c +++ b/OvmfPkg/SmmAccess/SmmAccessPei.c @@ -326,15 +326,16 @@ SmmAccessPeiEntryPoint ( // Set TSEG size, and disable TSEG visibility outside of SMM. Note that = the // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility = is // *restricted* to SMM. // EsmramcVal &=3D ~(UINT32)MCH_ESMRAMC_TSEG_MASK; EsmramcVal |=3D mQ35TsegMbytes =3D=3D 8 ? MCH_ESMRAMC_TSEG_8MB : mQ35TsegMbytes =3D=3D 2 ? MCH_ESMRAMC_TSEG_2MB : - MCH_ESMRAMC_TSEG_1MB; + mQ35TsegMbytes =3D=3D 1 ? MCH_ESMRAMC_TSEG_1MB : + MCH_ESMRAMC_TSEG_EXT; EsmramcVal |=3D MCH_ESMRAMC_T_EN; PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal); =20 // // TSEG should be closed (see above), but unlocked, initially. Set G_SMR= AME // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it. // diff --git a/OvmfPkg/SmmAccess/SmramInternal.c b/OvmfPkg/SmmAccess/SmramInt= ernal.c index ae1e9069aca6..fa0efeda72b0 100644 --- a/OvmfPkg/SmmAccess/SmramInternal.c +++ b/OvmfPkg/SmmAccess/SmramInternal.c @@ -192,14 +192,16 @@ SmramAccessGetCapabilities ( // The second region is the main one, following the first. // SmramMap[DescIdxMain].PhysicalStart =3D SmramMap[DescIdxSmmS3ResumeState].PhysicalStart + SmramMap[DescIdxSmmS3ResumeState].PhysicalSize; SmramMap[DescIdxMain].CpuStart =3D SmramMap[DescIdxMain].PhysicalStart; SmramMap[DescIdxMain].PhysicalSize =3D - (TsegSizeBits =3D=3D MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB : - TsegSizeBits =3D=3D MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB : - SIZE_1MB) - SmramMap[DescIdxSmmS3ResumeState].PhysicalSize; + (TsegSizeBits =3D=3D MCH_ESMRAMC_TSEG_8MB ? S= IZE_8MB : + TsegSizeBits =3D=3D MCH_ESMRAMC_TSEG_2MB ? S= IZE_2MB : + TsegSizeBits =3D=3D MCH_ESMRAMC_TSEG_1MB ? S= IZE_1MB : + mQ35TsegMbytes * SIZE_1MB) - + SmramMap[DescIdxSmmS3ResumeState].PhysicalSiz= e; SmramMap[DescIdxMain].RegionState =3D CommonRegionState; =20 return EFI_SUCCESS; } --=20 2.13.1.3.g8be5a757fa67 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Dec 27 18:25:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499187416415933.1150672116173; Tue, 4 Jul 2017 09:56:56 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B2B3121C9E7A4; Tue, 4 Jul 2017 09:55:05 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C277521CF3B9D for ; Tue, 4 Jul 2017 09:55:03 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id BA4E24E4C3; Tue, 4 Jul 2017 16:56:41 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id F32F45D968; Tue, 4 Jul 2017 16:56:40 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com BA4E24E4C3 Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com BA4E24E4C3 From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 4 Jul 2017 18:56:28 +0200 Message-Id: <20170704165629.13610-8-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 04 Jul 2017 16:56:41 +0000 (UTC) Subject: [edk2] [PATCH v2 7/8] OvmfPkg/PlatformPei: honor extended TSEG in PcdQ35TsegMbytes if available X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Recognize an extended TSEG when available in Q35TsegMbytesInitialization(), and set both PcdQ35TsegMbytes (for OvmfPkg/SmmAccess) and "mQ35TsegMbytes" (for PlatformPei's own use) accordingly. The new logic interfaces with the QEMU feature added in QEMU commit 2f295167e0c4 ("q35/mch: implement extended TSEG sizes", 2017-06-08). At this point we have to explicitly restrict Q35TsegMbytesInitialization() to the Q35 board, but that's OK, because Q35TsegMbytesInitialization() is only called when PcdSmmSmramRequire is set, and for that Q35 is already an enforced requirement. Cc: Jordan Justen Suggested-by: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/PlatformPei/Platform.h | 2 + OvmfPkg/PlatformPei/MemDetect.c | 52 +++++++++++++++++++- OvmfPkg/PlatformPei/Platform.c | 10 ++-- 3 files changed, 58 insertions(+), 6 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index d2d627b221c4..ae855531c1b7 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -104,8 +104,10 @@ extern EFI_BOOT_MODE mBootMode; =20 extern BOOLEAN mS3Supported; =20 extern UINT8 mPhysMemAddressWidth; =20 extern UINT32 mMaxCpuCount; =20 +extern UINT16 mHostBridgeDevId; + #endif // _PLATFORM_PEI_H_INCLUDED_ diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 886d23622665..97f3fa5afcf5 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -15,24 +15,27 @@ Module Name: MemDetect.c =20 **/ =20 // // The package level header files this module uses // +#include #include =20 // // The Library classes this module consumes // +#include #include #include #include #include #include +#include #include #include #include #include =20 #include "Platform.h" #include "Cmos.h" @@ -45,15 +48,62 @@ STATIC UINT32 mS3AcpiReservedMemorySize; STATIC UINT16 mQ35TsegMbytes; =20 VOID Q35TsegMbytesInitialization ( VOID ) { - mQ35TsegMbytes =3D PcdGet16 (PcdQ35TsegMbytes); + UINT16 ExtendedTsegMbytes; + RETURN_STATUS PcdStatus; + + if (mHostBridgeDevId !=3D INTEL_Q35_MCH_DEVICE_ID) { + DEBUG (( + DEBUG_ERROR, + "%a: no TSEG (SMRAM) on host bridge DID=3D0x%04x; " + "only DID=3D0x%04x (Q35) is supported\n", + __FUNCTION__, + mHostBridgeDevId, + INTEL_Q35_MCH_DEVICE_ID + )); + ASSERT (FALSE); + CpuDeadLoop (); + } + + // + // Check if QEMU offers an extended TSEG. + // + // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TS= EG_MB + // register, and reading back the register. + // + // On a QEMU machine type that does not offer an extended TSEG, the init= ial + // write overwrites whatever value a malicious guest OS may have placed = in + // the (unimplemented) register, before entering S3 or rebooting. + // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged. + // + // On a QEMU machine type that offers an extended TSEG, the initial write + // triggers an update to the register. Subsequently, the value read back + // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us t= he + // number of megabytes. + // + PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY); + ExtendedTsegMbytes =3D PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB)); + if (ExtendedTsegMbytes =3D=3D MCH_EXT_TSEG_MB_QUERY) { + mQ35TsegMbytes =3D PcdGet16 (PcdQ35TsegMbytes); + return; + } + + DEBUG (( + DEBUG_INFO, + "%a: QEMU offers an extended TSEG (%d MB)\n", + __FUNCTION__, + ExtendedTsegMbytes + )); + PcdStatus =3D PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes); + ASSERT_RETURN_ERROR (PcdStatus); + mQ35TsegMbytes =3D ExtendedTsegMbytes; } =20 =20 UINT32 GetSystemMemorySizeBelow4gb ( VOID ) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index b8a28450d6c5..98cfaaa28ed1 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -641,32 +641,32 @@ InitializePlatform ( } =20 S3Verification (); BootModeInitialization (); AddressWidthInitialization (); MaxCpuCountInitialization (); =20 + // + // Query Host Bridge DID + // + mHostBridgeDevId =3D PciRead16 (OVMF_HOSTBRIDGE_DID); + if (FeaturePcdGet (PcdSmmSmramRequire)) { Q35TsegMbytesInitialization (); } =20 PublishPeiMemory (); =20 InitializeRamRegions (); =20 if (mXen) { DEBUG ((EFI_D_INFO, "Xen was detected\n")); InitializeXen (); } =20 - // - // Query Host Bridge DID - // - mHostBridgeDevId =3D PciRead16 (OVMF_HOSTBRIDGE_DID); - if (mBootMode !=3D BOOT_ON_S3_RESUME) { if (!FeaturePcdGet (PcdSmmSmramRequire)) { ReserveEmuVariableNvStore (); } PeiFvInitialization (); MemMapInitialization (); NoexecDxeInitialization (); --=20 2.13.1.3.g8be5a757fa67 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri Dec 27 18:25:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1499187419675163.32360340010086; Tue, 4 Jul 2017 09:56:59 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E825B21C9E7A8; Tue, 4 Jul 2017 09:55:05 -0700 (PDT) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DFD8B21C9E7A2 for ; Tue, 4 Jul 2017 09:55:04 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D8B8561D38; Tue, 4 Jul 2017 16:56:42 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1BC5F5D968; Tue, 4 Jul 2017 16:56:41 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com D8B8561D38 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com D8B8561D38 From: Laszlo Ersek To: edk2-devel-01 Date: Tue, 4 Jul 2017 18:56:29 +0200 Message-Id: <20170704165629.13610-9-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Tue, 04 Jul 2017 16:56:43 +0000 (UTC) Subject: [edk2] [PATCH v2 8/8] OvmfPkg: mention the extended TSEG near the PcdQ35TsegMbytes declaration X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" PlatformPei can now overwrite PcdQ35TsegMbytes; document this in "OvmfPkg/OvmfPkg.dec". Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/OvmfPkg.dec | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index c46b72f069ef..e5f74a1248ed 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -125,18 +125,19 @@ [PcdsDynamic, PcdsDynamicEx] =20 ## The 64-bit MMIO aperture shared by all PCI root bridges. # gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27 =20 ## The following setting controls how many megabytes we configure as TSE= G on - # Q35, for SMRAM purposes. Permitted values are: 1, 2, 8. Other values = cause - # undefined behavior. + # Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defau= lts + # cause undefined behavior. During boot, the PCD is updated by Platform= Pei + # to reflect the extended TSEG size, if one is advertized by QEMU. # - # This PCD is only consulted if PcdSmmSmramRequire is TRUE (see below). + # This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below). gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20 =20 [PcdsFeatureFlag] gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0= x1c gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN= |0x1d =20 ## This feature flag enables SMM/SMRAM support. Note that it also requir= es --=20 2.13.1.3.g8be5a757fa67 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel