From nobody Fri Dec 27 02:02:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 15036514588639.421420650606933; Fri, 25 Aug 2017 01:57:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 28F4A21D1E2E7; Fri, 25 Aug 2017 01:54:56 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DA9A821D1E2C4 for ; Fri, 25 Aug 2017 01:54:53 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Aug 2017 01:57:29 -0700 Received: from ray-dev.ccr.corp.intel.com ([10.239.9.2]) by orsmga004.jf.intel.com with ESMTP; 25 Aug 2017 01:57:29 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,424,1498546800"; d="scan'208";a="122500774" From: Ruiyu Ni To: edk2-devel@lists.01.org Date: Fri, 25 Aug 2017 16:57:20 +0800 Message-Id: <20170825085723.396044-3-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.12.2.windows.2 In-Reply-To: <20170825085723.396044-1-ruiyu.ni@intel.com> References: <20170825085723.396044-1-ruiyu.ni@intel.com> Subject: [edk2] [PATCH v2 2/5] MdePkg/PciExpress: Add macro PCI_ECAM_ADDRESS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Liming Gao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The patch adds new macro PCI_ECAM_ADDRESS into PciExpress21.h, to align to the PCIE spec, and also update PciExpressLib.h to redirect PCI_EXPRESS_LIB_ADDRESS to the new macro. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Liming Gao --- MdePkg/Include/IndustryStandard/PciExpress21.h | 19 ++++++++++++++++++- MdePkg/Include/Library/PciExpressLib.h | 5 ++--- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Includ= e/IndustryStandard/PciExpress21.h index 175c82c88e..ce9c06a7c6 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress21.h +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h @@ -1,7 +1,7 @@ /** @file Support for the latest PCI standard. =20 - Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
(C) Copyright 2016 Hewlett Packard Enterprise Development LP
=20 This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BS= D License =20 @@ -18,6 +18,23 @@ =20 #include =20 +/** + Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register t= o an + ECAM (Enhanced Configuration Access Mechanism) address. The unused upper= bits + of Bus, Device, Function and Register are stripped prior to the generati= on of + the address. + + @param Bus PCI Bus number. Range 0..255. + @param Device PCI Device number. Range 0..31. + @param Function PCI Function number. Range 0..7. + @param Register PCI Register number. Range 0..4095. + + @return The encode ECAM address. + +**/ +#define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \ + (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) <= < 15) | (((Bus) & 0xff) << 20)) + #pragma pack(1) /// /// PCI Express Capability Structure diff --git a/MdePkg/Include/Library/PciExpressLib.h b/MdePkg/Include/Librar= y/PciExpressLib.h index e312d57528..f65b44384f 100644 --- a/MdePkg/Include/Library/PciExpressLib.h +++ b/MdePkg/Include/Library/PciExpressLib.h @@ -5,7 +5,7 @@ configuration cycles must be through the 256 MB PCI Express MMIO window = whose base address is defined by PcdPciExpressBaseAddress. =20 -Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -35,8 +35,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. @return The encode PCI address. =20 **/ -#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \ - (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) <= < 15) | (((Bus) & 0xff) << 20)) +#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRE= SS ((Bus), (Device), (Function), (Offset)) =20 /** Registers a PCI device so PCI configuration registers may be accessed af= ter=20 --=20 2.12.2.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel