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[edk2] [PATCH edk2-platforms v2 4/4] Platform/OverdriveBoard: classify legacy INTx interrupts as level high

Ard Biesheuvel posted 4 patches 7 years, 3 months ago
[edk2] [PATCH edk2-platforms v2 4/4] Platform/OverdriveBoard: classify legacy INTx interrupts as level high
Posted by Ard Biesheuvel 7 years, 3 months ago 
Fix the trigger type of the legacy INTx interrupts. The Seattle SoC manual
classifies them as level high, not rising edge.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts | 28 ++++++++++----------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts
index e57e702029ba..2c05fdbb8b71 100644
--- a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts
+++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts
@@ -291,20 +291,20 @@
       msi-parent = <&msi>;
       reg = <0x0 0xf0000000 0x0 0x10000000>;
       interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
-      interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ_TYPE_EDGE_RISING>,
-                      <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_TYPE_EDGE_RISING>,
-                      <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_TYPE_EDGE_RISING>,
-                      <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_TYPE_EDGE_RISING>,
-
-                      <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_TYPE_EDGE_RISING>,
-                      <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_TYPE_EDGE_RISING>,
-                      <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_TYPE_EDGE_RISING>,
-                      <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_TYPE_EDGE_RISING>,
-
-                      <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_TYPE_EDGE_RISING>,
-                      <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_TYPE_EDGE_RISING>,
-                      <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_TYPE_EDGE_RISING>,
-                      <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_TYPE_EDGE_RISING>;
+      interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ_TYPE_LEVEL_HIGH>,
+                      <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_TYPE_LEVEL_HIGH>,
+                      <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_TYPE_LEVEL_HIGH>,
+                      <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_TYPE_LEVEL_HIGH>,
+
+                      <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_TYPE_LEVEL_HIGH>,
+                      <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_TYPE_LEVEL_HIGH>,
+                      <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_TYPE_LEVEL_HIGH>,
+                      <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_TYPE_LEVEL_HIGH>,
+
+                      <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_TYPE_LEVEL_HIGH>,
+                      <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_TYPE_LEVEL_HIGH>,
+                      <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_TYPE_LEVEL_HIGH>,
+                      <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_TYPE_LEVEL_HIGH>;
       dma-coherent;
       dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
       ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */
-- 
2.11.0

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Re: [edk2] [PATCH edk2-platforms v2 4/4] Platform/OverdriveBoard: classify legacy INTx interrupts as level high
Posted by Leif Lindholm 7 years, 3 months ago 
On Thu, Aug 31, 2017 at 02:08:30PM +0100, Ard Biesheuvel wrote:
> Fix the trigger type of the legacy INTx interrupts. The Seattle SoC manual
> classifies them as level high, not rising edge.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts | 28 ++++++++++----------
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts
> index e57e702029ba..2c05fdbb8b71 100644
> --- a/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts
> +++ b/Platform/AMD/OverdriveBoard/OverdriveBoardDeviceTree/OverdriveBoardDeviceTree.dts
> @@ -291,20 +291,20 @@
>        msi-parent = <&msi>;
>        reg = <0x0 0xf0000000 0x0 0x10000000>;
>        interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
> -      interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ_TYPE_EDGE_RISING>,
> -                      <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_TYPE_EDGE_RISING>,
> -                      <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_TYPE_EDGE_RISING>,
> -                      <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_TYPE_EDGE_RISING>,
> -
> -                      <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_TYPE_EDGE_RISING>,
> -                      <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_TYPE_EDGE_RISING>,
> -                      <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_TYPE_EDGE_RISING>,
> -                      <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_TYPE_EDGE_RISING>,
> -
> -                      <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_TYPE_EDGE_RISING>,
> -                      <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_TYPE_EDGE_RISING>,
> -                      <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_TYPE_EDGE_RISING>,
> -                      <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_TYPE_EDGE_RISING>;
> +      interrupt-map = <0x1100 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x120 IRQ_TYPE_LEVEL_HIGH>,
> +                      <0x1100 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x121 IRQ_TYPE_LEVEL_HIGH>,
> +                      <0x1100 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x122 IRQ_TYPE_LEVEL_HIGH>,
> +                      <0x1100 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x123 IRQ_TYPE_LEVEL_HIGH>,
> +
> +                      <0x1200 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x124 IRQ_TYPE_LEVEL_HIGH>,
> +                      <0x1200 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x125 IRQ_TYPE_LEVEL_HIGH>,
> +                      <0x1200 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x126 IRQ_TYPE_LEVEL_HIGH>,
> +                      <0x1200 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x127 IRQ_TYPE_LEVEL_HIGH>,
> +
> +                      <0x1300 0x0 0x0 0x1 &gic 0x0 0x0 GIC_SPI 0x128 IRQ_TYPE_LEVEL_HIGH>,
> +                      <0x1300 0x0 0x0 0x2 &gic 0x0 0x0 GIC_SPI 0x129 IRQ_TYPE_LEVEL_HIGH>,
> +                      <0x1300 0x0 0x0 0x3 &gic 0x0 0x0 GIC_SPI 0x12a IRQ_TYPE_LEVEL_HIGH>,
> +                      <0x1300 0x0 0x0 0x4 &gic 0x0 0x0 GIC_SPI 0x12b IRQ_TYPE_LEVEL_HIGH>;
>        dma-coherent;
>        dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;
>        ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */
> -- 
> 2.11.0
> 
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Patchew 2.1-devel-8c64711

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