From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456968968337.54374002428347; Tue, 26 Sep 2017 13:16:08 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 63C6820945BA4; Tue, 26 Sep 2017 13:12:30 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4498E21EC8D1D for ; Tue, 26 Sep 2017 13:12:26 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5Q017392; Tue, 26 Sep 2017 21:15:35 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:11 +0100 Message-Id: <20170926201529.11644-2-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 01/19] ArmPlatformPkg: Tidy LcdGraphicsOutputDxe code: Coding standard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak There is no functional modification in this change As preparation for further work, the formatting is corrected to meet the EDKII coding standard. Of specific note, some invalid include guards were fixed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf | 9 +- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf | 6 +- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf = | 4 +- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf = | 4 +- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h = | 11 +- ArmPlatformPkg/Include/Library/LcdPlatformLib.h = | 10 +- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c | 103 +++++++----- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c | 173 ++++++++++++-------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c = | 83 ++++++---- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c = | 130 ++++++++------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c = | 54 ++++-- 11 files changed, 350 insertions(+), 237 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpres= sLib/HdLcdArmVExpressLib.inf index dff17e86fd3e563b38318f696a94f2c75276b31f..4733bb8e662d64eca0976af21b2= abb7036b4424b 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= pressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= pressLib.inf @@ -1,8 +1,8 @@ -#/** @file +#/** @file HdLcdArmVExpress.inf # -# Component description file for HdLcdArmLib module +# Component description file for HdLcdArmVExpress module # -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -23,8 +23,7 @@ [Defines] LIBRARY_CLASS =3D LcdPlatformLib =20 [Sources.common] - -HdLcdArmVExpress.c + HdLcdArmVExpress.c =20 [Packages] MdePkg/MdePkg.dec diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdA= rmVExpressLib/PL111LcdArmVExpressLib.inf index 658558ab15230d07f1c04d29a8e2bf8d14f1d6a2..3fde707c33dbcbd8adbbf18bbba= 718b823194abc 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpressLib.inf @@ -1,8 +1,8 @@ -#/** @file +#/** @file PL111LcdArmVExpressLib.inf # -# Component description file for ArmVeGraphicsDxe module +# Component description file for PL111LcdArmVExpressLib module # -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutpu= tDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputD= xe.inf index 462d1fa402d7a1939b2876b74a5b76e8edf2e1f6..26e580a594fc328187407ac4c17= 87f180fbf4b17 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf @@ -1,8 +1,8 @@ -#/** @file +#/** @file HdLcdGraphicsOutputDxe.inf # # Component description file for HDLCD module # -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOu= tputDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsO= utputDxe.inf index 003cc2ffa912b39d6f1342c92445eefce94b1f8b..ad0348500326c4567f0e1b235c8= 4b694e61306bf 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe= .inf +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe= .inf @@ -1,8 +1,8 @@ -#/** @file +#/** @file PL111LcdGraphicsOutputDxe.inf # # Component description file for PL111LcdGraphicsOutputDxe module # -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
# This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputD= xe.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h index 8856b79901b632071ae4c4081b69e5188daa23ed..85e918de66624d61c6d0e05c5a6= 7c516cd7619aa 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h @@ -1,6 +1,6 @@ -/** @file +/** @file LcdGraphicsOutputDxe.h =20 - Copyright (c) 2011, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -11,8 +11,8 @@ =20 **/ =20 -#ifndef __ARM_VE_GRAPHICS_DXE_H__ -#define __ARM_VE_GRAPHICS_DXE_H__ +#ifndef LCD_GRAPHICS_OUTPUT_DXE_H_ +#define LCD_GRAPHICS_OUTPUT_DXE_H_ =20 =20 #include @@ -124,5 +124,4 @@ VOID LcdShutdown ( VOID ); - -#endif /* __ARM_VE_GRAPHICS_DXE_H__ */ +#endif /* LCD_GRAPHICS_OUTPUT_DXE_H_ */ diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformP= kg/Include/Library/LcdPlatformLib.h index b9bdf471e2d65dba7a0fcb0f7ecc352bd576b46b..72ebcd02ddb321ee0dad51c87ac= 8ee876d9ca21c 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -1,6 +1,6 @@ -/** @file +/** @file LcdPlatformLib.h =20 - Copyright (c) 2011, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD= License which accompanies this distribution. The full text of the license may be= found at @@ -11,8 +11,8 @@ =20 **/ =20 -#ifndef __LCDPLATFORMLIB_H -#define __LCDPLATFORMLIB_H +#ifndef LCD_PLATFORM_LIB_H_ +#define LCD_PLATFORM_LIB_H_ =20 #include =20 @@ -218,4 +218,4 @@ LcdPlatformGetBpp ( OUT LCD_BPP* Bpp ); =20 -#endif +#endif // LCD_PLATFORM_LIB_H_ diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/= HdLcdArmVExpress.c index b1106ee19b98cebac01820924514eac79b97d0d5..2041de5f63c72de6f0ce4047420= c282507a1d04a 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c @@ -1,6 +1,6 @@ -/** +/** @file HdLcdArmVExpress.c =20 - Copyright (c) 2012, ARM Ltd. All rights reserved. + Copyright (c) 2012-2017, ARM Ltd. All rights reserved. =20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -47,32 +47,38 @@ typedef struct { =20 LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OS= C_FREQUENCY, + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA_OSC_FREQUENCY, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVG= A_OSC_FREQUENCY, + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA_OSC_FREQUENCY, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OS= C_FREQUENCY, + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA_OSC_FREQUENCY, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SX= GA_OSC_FREQUENCY/2), + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (SXGA_OSC_FREQUENCY/2), SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UX= GA_OSC_FREQUENCY/2), + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (UXGA_OSC_FREQUENCY/2), UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_F= REQUENCY/2), + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (HD_OSC_FREQUENCY/2), HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH } @@ -95,19 +101,25 @@ LcdPlatformInitializeDisplay ( { EFI_STATUS Status; =20 - // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); - if (EFI_ERROR(Status)) { + /* Set the FPGA multiplexer to select the video output from the + * motherboard or the daughterboard */ + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_MUXFPGA, + ARM_VE_DAUGHTERBOARD_1_SITE + ); + if (EFI_ERROR (Status)) { return Status; } =20 // Install the EDID Protocols Status =3D gBS->InstallMultipleProtocolInterfaces ( - &Handle, - &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, - &gEfiEdidActiveProtocolGuid, &mEdidActive, - NULL - ); + &Handle, + &gEfiEdidDiscoveredProtocolGuid, + &mEdidDiscovered, + &gEfiEdidActiveProtocolGuid, + &mEdidActive, + NULL + ); =20 return Status; } @@ -132,16 +144,25 @@ LcdPlatformGetVram ( } else { AllocationType =3D AllocateAddress; } - Status =3D gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_= SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); - if (EFI_ERROR(Status)) { + Status =3D gBS->AllocatePages ( + AllocationType, + EfiBootServicesData, + EFI_SIZE_TO_PAGES (((UINTN)LCD_VRAM_SIZE)), + VramBaseAddress + ); + if (EFI_ERROR (Status)) { return Status; } =20 - // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which = is cacheable. - Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, - EFI_MEMORY_WC); - ASSERT_EFI_ERROR(Status); - if (EFI_ERROR(Status)) { + /* Mark the VRAM as write-combining. + * The VRAM is inside the DRAM, which is cacheable. */ + Status =3D gDS->SetMemorySpaceAttributes ( + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } @@ -150,15 +171,11 @@ LcdPlatformGetVram ( } =20 UINT32 -LcdPlatformGetMaxMode ( - VOID - ) +LcdPlatformGetMaxMode(VOID) { - // - // The following line will report correctly the total number of graphics= modes - // that could be supported by the graphics driver: - // - return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION)); + /* The following line will report correctly the total number of graphics= modes + * that could be supported by the graphics driver: */ + return (sizeof (mResolutions) / sizeof (LCD_RESOLUTION)); } =20 EFI_STATUS @@ -174,25 +191,35 @@ LcdPlatformSetMode ( =20 // Set the video mode oscillator do { - Status =3D ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(= PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq); + Status =3D ArmPlatformSysConfigSetDevice ( + SYS_CFG_OSC_SITE1, + PcdGet32 (PcdHdLcdVideoModeOscId), + mResolutions[ModeNumber].OscFreq + ); } while (Status =3D=3D EFI_TIMEOUT); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } =20 // Set the DVI into the new mode do { - Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mode= Number].Mode); + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_DVIMODE, + mResolutions[ModeNumber].Mode + ); } while (Status =3D=3D EFI_TIMEOUT); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } =20 // Set the multiplexer - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); - if (EFI_ERROR(Status)) { + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_MUXFPGA, + ARM_VE_DAUGHTERBOARD_1_SITE + ); + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -233,7 +260,7 @@ LcdPlatformQueryMode ( case LCD_BITS_PER_PIXEL_1: default: // These are not supported - ASSERT(FALSE); + ASSERT (FALSE); break; } =20 diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVEx= pressLib/PL111LcdArmVExpress.c index 3f3ceb3d2fa82f614e0c6dac8455c117745cf3a6..8d046816454f642bced00e29c4e= 02093b74afd24 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c @@ -1,6 +1,6 @@ -/** @file +/** @file PL111LcdArmVExpress.c =20 - Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -43,83 +43,99 @@ typedef struct { =20 =20 LCD_RESOLUTION mResolutions[] =3D { - { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_= OSC_FREQUENCY, + { // Mode 0 : VGA : 640 x 480 x 24 bpp + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA_OSC_FREQUENCY, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, - { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, S= VGA_OSC_FREQUENCY, + { // Mode 1 : SVGA : 800 x 600 x 24 bpp + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA_OSC_FREQUENCY, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, - { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_= OSC_FREQUENCY, + { // Mode 2 : XGA : 1024 x 768 x 24 bpp + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA_OSC_FREQUENCY, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, - { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= SXGA_OSC_FREQUENCY/2), + { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (SXGA_OSC_FREQUENCY/2), SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH }, - { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= UXGA_OSC_FREQUENCY/2), + { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (UXGA_OSC_FREQUENCY/2), UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH }, - { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC= _FREQUENCY/2), + { // Mode 5 : HD : 1920 x 1080 x 24 bpp + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + (HD_OSC_FREQUENCY/2), HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH }, - { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = VGA_OSC_FREQUENCY, + { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode) + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + VGA_OSC_FREQUENCY, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, - { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_56= 5, SVGA_OSC_FREQUENCY, + { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode) + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_56= 5, + SVGA_OSC_FREQUENCY, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, - { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = XGA_OSC_FREQUENCY, + { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode) + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + XGA_OSC_FREQUENCY, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, - { // Mode 9 : VGA : 640 x 480 x 15 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = VGA_OSC_FREQUENCY, + { // Mode 9 : VGA : 640 x 480 x 15 bpp + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + VGA_OSC_FREQUENCY, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, - { // Mode 10 : SVGA : 800 x 600 x 15 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_55= 5, SVGA_OSC_FREQUENCY, + { // Mode 10 : SVGA : 800 x 600 x 15 bpp + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_55= 5, + SVGA_OSC_FREQUENCY, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, - { // Mode 11 : XGA : 1024 x 768 x 15 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = XGA_OSC_FREQUENCY, + { // Mode 11 : XGA : 1024 x 768 x 15 bpp + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + XGA_OSC_FREQUENCY, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, - { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derive= d from Linux Kernel Driver Settings - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = 63500000, + { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is deri= ved from Linux Kernel Driver Settings + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + 63500000, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH }, - { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = VGA_OSC_FREQUENCY, + { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode) + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + VGA_OSC_FREQUENCY, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH }, - { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_44= 4, SVGA_OSC_FREQUENCY, + { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode) + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_44= 4, + SVGA_OSC_FREQUENCY, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH }, - { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = XGA_OSC_FREQUENCY, + { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode) + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + XGA_OSC_FREQUENCY, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH } @@ -145,14 +161,16 @@ LcdPlatformInitializeDisplay ( =20 // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE); - if (!EFI_ERROR(Status)) { + if (!EFI_ERROR (Status)) { // Install the EDID Protocols - Status =3D gBS->InstallMultipleProtocolInterfaces( - &Handle, - &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, - &gEfiEdidActiveProtocolGuid, &mEdidActive, - NULL - ); + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiEdidDiscoveredProtocolGuid, + &mEdidDiscovered, + &gEfiEdidActiveProtocolGuid, + &mEdidActive, + NULL + ); } =20 return Status; @@ -169,29 +187,38 @@ LcdPlatformGetVram ( Status =3D EFI_SUCCESS; =20 // Is it on the motherboard or on the daughterboard? - switch(PL111_CLCD_SITE) { + switch (PL111_CLCD_SITE) { =20 case ARM_VE_MOTHERBOARD_SITE: - *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOAR= D_BASE; + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)PL111_CLCD_VRAM_MOTHERBOARD= _BASE; *VramSize =3D LCD_VRAM_SIZE; break; =20 case ARM_VE_DAUGHTERBOARD_1_SITE: - *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE; + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE; *VramSize =3D LCD_VRAM_SIZE; =20 // Allocate the VRAM from the DRAM so that nobody else uses it. - Status =3D gBS->AllocatePages( AllocateAddress, EfiBootServicesData, E= FI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); - if (EFI_ERROR(Status)) { + Status =3D gBS->AllocatePages ( + AllocateAddress, + EfiBootServicesData, + EFI_SIZE_TO_PAGES (((UINTN)LCD_VRAM_SIZE)), + VramBaseAddress + ); + if (EFI_ERROR (Status)) { return Status; } =20 - // Mark the VRAM as write-combining. The VRAM is inside the DRAM, whic= h is cacheable. - Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, - EFI_MEMORY_WC); - ASSERT_EFI_ERROR(Status); - if (EFI_ERROR(Status)) { - gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize)); + // Mark the VRAM as write-combining. + // The VRAM is inside the DRAM, which is cacheable. + Status =3D gDS->SetMemorySpaceAttributes ( + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } break; @@ -206,19 +233,20 @@ LcdPlatformGetVram ( } =20 UINT32 -LcdPlatformGetMaxMode ( - VOID - ) +LcdPlatformGetMaxMode(VOID) { - // The following line will report correctly the total number of graphics= modes - // supported by the PL111CLCD. - //return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1; + /* The following line would correctly reports the total number + * of graphics modes supported by the PL111CLCD. + * return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1; + */ =20 - // However, on some platforms it is desirable to ignore some graphics mo= des. - // This could be because the specific implementation of PL111 has certai= n limitations. + /* However, on some platforms it is desirable to ignore some graphics mo= des. + * This could be because the specific implementation of PL111 has + * certain limitations. + */ =20 // Set the maximum mode allowed - return (PcdGet32(PcdPL111LcdMaxMode)); + return (PcdGet32 (PcdPL111LcdMaxMode)); } =20 EFI_STATUS @@ -238,22 +266,26 @@ LcdPlatformSetMode ( =20 LcdSite =3D PL111_CLCD_SITE; =20 - switch(LcdSite) { + switch (LcdSite) { case ARM_VE_MOTHERBOARD_SITE: Function =3D SYS_CFG_OSC; OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; break; case ARM_VE_DAUGHTERBOARD_1_SITE: Function =3D SYS_CFG_OSC_SITE1; - OscillatorId =3D (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId); + OscillatorId =3D (UINT32)PcdGet32 (PcdPL111LcdVideoModeOscId); break; default: return EFI_UNSUPPORTED; } =20 // Set the video mode oscillator - Status =3D ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResol= utions[ModeNumber].OscFreq); - if (EFI_ERROR(Status)) { + Status =3D ArmPlatformSysConfigSetDevice ( + Function, + OscillatorId, + mResolutions[ModeNumber].OscFreq + ); + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -267,8 +299,11 @@ LcdPlatformSetMode ( SysId &=3D ~ARM_FVP_SYS_ID_VARIANT_MASK; if (SysId !=3D ARM_FVP_BASE_BOARD_SYS_ID) { // Set the DVI into the new mode - Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mo= deNumber].Mode); - if (EFI_ERROR(Status)) { + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_DVIMODE, + mResolutions[ModeNumber].Mode + ); + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -277,7 +312,7 @@ LcdPlatformSetMode ( =20 // Set the multiplexer Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } @@ -318,7 +353,7 @@ LcdPlatformQueryMode ( case LCD_BITS_PER_PIXEL_1: default: // These are not supported - ASSERT(FALSE); + ASSERT (FALSE); break; } =20 diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatf= ormPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c index 2bfe2c0fe2dcd05f4983eea57542cfe3d30bf1ce..eb0b6fb3fbbc1cb605469433f6c= 6dcb85bac668c 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c @@ -1,6 +1,6 @@ -/** @file Lcd.c +/** @file HdLcd.c =20 - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -35,21 +35,34 @@ LcdInitialize ( ) { // Disable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); + MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); =20 // Disable all interrupts - MmioWrite32(HDLCD_REG_INT_MASK, 0); + MmioWrite32 (HDLCD_REG_INT_MASK, 0); =20 // Define start of the VRAM. This never changes for any graphics mode - MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress); + MmioWrite32 (HDLCD_REG_FB_BASE, (UINT32)VramBaseAddress); =20 // Setup various registers that never change - MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8); - MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | = HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH); - MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_P= ER_PIXEL); - MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0)); - MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8)); - MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16)); + MmioWrite32 (HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8); + + MmioWrite32 ( + HDLCD_REG_POLARITIES, + HDLCD_PXCLK_LOW + | HDLCD_DATA_HIGH + | HDLCD_DATEN_HIGH + | HDLCD_HSYNC_LOW + | HDLCD_VSYNC_HIGH + ); + + MmioWrite32 ( + HDLCD_REG_PIXEL_FORMAT, + HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL + ); + + MmioWrite32 (HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0)); + MmioWrite32 (HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8)); + MmioWrite32 (HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16)); =20 return EFI_SUCCESS; } @@ -73,44 +86,52 @@ LcdSetMode ( =20 =20 // Set the video mode timings and other relevant information - Status =3D LcdPlatformGetTimings (ModeNumber, - &HRes,&HSync,&HBackPorch,&HFrontPorch, - &VRes,&VSync,&VBackPorch,&VFrontPorch); + Status =3D LcdPlatformGetTimings ( + ModeNumber, + &HRes, + &HSync, + &HBackPorch, + &HFrontPorch, + &VRes, + &VSync, + &VBackPorch, + &VFrontPorch + ); ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { + if (EFI_ERROR (Status)) { return EFI_DEVICE_ERROR; } =20 - Status =3D LcdPlatformGetBpp (ModeNumber,&LcdBpp); + Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { + if (EFI_ERROR (Status)) { return EFI_DEVICE_ERROR; } =20 - BytesPerPixel =3D GetBytesPerPixel(LcdBpp); + BytesPerPixel =3D GetBytesPerPixel (LcdBpp); =20 // Disable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); + MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); =20 // Update the frame buffer information with the new settings - MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel); - MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel); - MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1); + MmioWrite32 (HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel); + MmioWrite32 (HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel); + MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, VRes - 1); =20 // Set the vertical timing information - MmioWrite32(HDLCD_REG_V_SYNC, VSync); - MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch); - MmioWrite32(HDLCD_REG_V_DATA, VRes - 1); - MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch); + MmioWrite32 (HDLCD_REG_V_SYNC, VSync); + MmioWrite32 (HDLCD_REG_V_BACK_PORCH, VBackPorch); + MmioWrite32 (HDLCD_REG_V_DATA, VRes - 1); + MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, VFrontPorch); =20 // Set the horizontal timing information - MmioWrite32(HDLCD_REG_H_SYNC, HSync); - MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch); - MmioWrite32(HDLCD_REG_H_DATA, HRes - 1); - MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch); + MmioWrite32 (HDLCD_REG_H_SYNC, HSync); + MmioWrite32 (HDLCD_REG_H_BACK_PORCH, HBackPorch); + MmioWrite32 (HDLCD_REG_H_DATA, HRes - 1); + MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, HFrontPorch); =20 // Enable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE); + MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_ENABLE); =20 return EFI_SUCCESS; } diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputD= xe.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c index b721061fc1df5695092e8c71da97ae0b9af46b3f..2dd8f39873f77b1c211bff407ca= be90c1795b121 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c @@ -1,6 +1,6 @@ -/** @file +/** @file LcdGraphicsOutputDxe.c =20 - Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD= License which accompanies this distribution. The full text of the license may be= found at @@ -9,7 +9,7 @@ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. =20 - **/ +**/ =20 #include #include @@ -64,7 +64,9 @@ LCD_INSTANCE mLcdTemplate =3D { { { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, - { (UINT8) (sizeof(VENDOR_DEVICE_PATH)), (UINT8) ((sizeof(VENDOR_DE= VICE_PATH)) >> 8) }, + { (UINT8)(sizeof (VENDOR_DEVICE_PATH)), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + }, }, // Hardware Device Path for Lcd EFI_CALLER_ID_GUID // Use the driver's GUID @@ -73,7 +75,7 @@ LCD_INSTANCE mLcdTemplate =3D { { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, - { sizeof(EFI_DEVICE_PATH_PROTOCOL), 0 } + { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } } }, (EFI_EVENT) NULL // ExitBootServicesEvent @@ -86,7 +88,7 @@ LcdInstanceContructor ( { LCD_INSTANCE* Instance; =20 - Instance =3D AllocateCopyPool (sizeof(LCD_INSTANCE), &mLcdTemplate); + Instance =3D AllocateCopyPool (sizeof (LCD_INSTANCE), &mLcdTemplate); if (Instance =3D=3D NULL) { return EFI_OUT_OF_RESOURCES; } @@ -113,23 +115,23 @@ InitializeDisplay ( UINTN VramSize; =20 Status =3D LcdPlatformGetVram (&VramBaseAddress, &VramSize); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { return Status; } =20 // Setup the LCD Status =3D LcdInitialize (VramBaseAddress); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { goto EXIT_ERROR_LCD_SHUTDOWN; } =20 Status =3D LcdPlatformInitializeDisplay (Instance->Handle); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { goto EXIT_ERROR_LCD_SHUTDOWN; } =20 // Setup all the relevant mode information - Instance->Gop.Mode->SizeOfInfo =3D sizeof(EFI_GRAPHICS_OUTPUT_MODE_= INFORMATION); + Instance->Gop.Mode->SizeOfInfo =3D sizeof (EFI_GRAPHICS_OUTPUT_MODE= _INFORMATION); Instance->Gop.Mode->FrameBufferBase =3D VramBaseAddress; =20 // Set the flag before changing the mode, to avoid infinite loops @@ -139,7 +141,8 @@ InitializeDisplay ( goto EXIT; =20 EXIT_ERROR_LCD_SHUTDOWN: - DEBUG((DEBUG_ERROR, "InitializeDisplay: ERROR - Can not initialise the d= isplay. Exit Status=3D%r\n", Status)); + DEBUG ((DEBUG_ERROR, "InitializeDisplay: ERROR - Can not initialise the = display. Exit Status=3D%r\n", Status)); + LcdShutdown (); =20 EXIT: @@ -157,40 +160,44 @@ LcdGraphicsOutputDxeInitialize ( LCD_INSTANCE* Instance; =20 Status =3D LcdIdentify (); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { goto EXIT; } =20 Status =3D LcdInstanceContructor (&Instance); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { goto EXIT; } =20 // Install the Graphics Output Protocol and the Device Path - Status =3D gBS->InstallMultipleProtocolInterfaces( - &Instance->Handle, - &gEfiGraphicsOutputProtocolGuid, &Instance->Gop, - &gEfiDevicePathProtocolGuid, &Instance->DevicePath, - NULL - ); + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Instance->Handle, + &gEfiGraphicsOutputProtocolGuid, + &Instance->Gop, + &gEfiDevicePathProtocolGuid, + &Instance->DevicePath, + NULL + ); =20 - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the = protocol. Exit Status=3D%r\n", Status)); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "LcdGraphicsOutputDxeInitialize: Can not install = the protocol. Exit Status=3D%r\n", Status)); goto EXIT; } =20 - // Register for an ExitBootServicesEvent - // When ExitBootServices starts, this function here will make sure that = the graphics driver will shut down properly, - // i.e. it will free up all allocated memory and perform any necessary h= ardware re-configuration. + /* Register for an ExitBootServicesEvent + * When ExitBootServices starts, this function will make sure that the + * graphics driver shuts down properly, i.e. it will free up all + * allocated memory and perform any necessary hardware re-configuration.= */ Status =3D gBS->CreateEvent ( EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, - LcdGraphicsExitBootServicesEvent, NULL, + LcdGraphicsExitBootServicesEvent, + NULL, &Instance->ExitBootServicesEvent ); =20 - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the = ExitBootServicesEvent handler. Exit Status=3D%r\n", Status)); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "LcdGraphicsOutputDxeInitialize: Can not install = the ExitBootServicesEvent handler. Exit Status=3D%r\n", Status)); goto EXIT_ERROR_UNINSTALL_PROTOCOL; } =20 @@ -204,11 +211,13 @@ EXIT_ERROR_UNINSTALL_PROTOCOL: * the Status variable, even it fails to uninstall the protocol. */ gBS->UninstallMultipleProtocolInterfaces ( - Instance->Handle, - &gEfiGraphicsOutputProtocolGuid, &Instance->Gop, // Uninstall Graphics= Output protocol - &gEfiDevicePathProtocolGuid, &Instance->DevicePath, // Uninsta= ll device path - NULL - ); + Instance->Handle, + &gEfiGraphicsOutputProtocolGuid, + &Instance->Gop, // Uninstall Graphics Output protocol + &gEfiDevicePathProtocolGuid, + &Instance->DevicePath, // Uninstall device path + NULL + ); =20 EXIT: return Status; @@ -227,9 +236,9 @@ LcdGraphicsExitBootServicesEvent ( IN VOID *Context ) { - // By default, this PCD is FALSE. But if a platform starts a predefined = OS that - // does not use a framebuffer then we might want to disable the display = controller - // to avoid to display corrupted information on the screen. + /* By default, this PCD is FALSE. But if a platform starts a predefined = OS + * that does not use a framebuffer then we might want to disable the dis= play + * controller to avoid to display corrupted information on the screen. */ if (FeaturePcdGet (PcdGopDisableOnExitBootServices)) { // Turn-off the Display controller LcdShutdown (); @@ -252,19 +261,22 @@ LcdGraphicsQueryMode ( EFI_STATUS Status =3D EFI_SUCCESS; LCD_INSTANCE *Instance; =20 - Instance =3D LCD_INSTANCE_FROM_GOP_THIS(This); + Instance =3D LCD_INSTANCE_FROM_GOP_THIS (This); =20 // Setup the hardware if not already done - if( !mDisplayInitialized ) { - Status =3D InitializeDisplay(Instance); - if (EFI_ERROR(Status)) { + if (!mDisplayInitialized) { + Status =3D InitializeDisplay (Instance); + if (EFI_ERROR (Status)) { goto EXIT; } } =20 // Error checking - if ( (This =3D=3D NULL) || (Info =3D=3D NULL) || (SizeOfInfo =3D=3D NULL= ) || (ModeNumber >=3D This->Mode->MaxMode) ) { - DEBUG((DEBUG_ERROR, "LcdGraphicsQueryMode: ERROR - For mode number %d = : Invalid Parameter.\n", ModeNumber )); + if ( (This =3D=3D NULL) + || (Info =3D=3D NULL) + || (SizeOfInfo =3D=3D NULL) + || (ModeNumber >=3D This->Mode->MaxMode)) { + DEBUG ((DEBUG_ERROR, "LcdGraphicsQueryMode: ERROR - For mode number %d= : Invalid Parameter.\n", ModeNumber)); Status =3D EFI_INVALID_PARAMETER; goto EXIT; } @@ -275,11 +287,11 @@ LcdGraphicsQueryMode ( goto EXIT; } =20 - *SizeOfInfo =3D sizeof( EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); + *SizeOfInfo =3D sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); =20 - Status =3D LcdPlatformQueryMode (ModeNumber,*Info); - if (EFI_ERROR(Status)) { - FreePool(*Info); + Status =3D LcdPlatformQueryMode (ModeNumber, *Info); + if (EFI_ERROR (Status)) { + FreePool (*Info); } =20 EXIT: @@ -305,47 +317,48 @@ LcdGraphicsSetMode ( Instance =3D LCD_INSTANCE_FROM_GOP_THIS (This); =20 // Setup the hardware if not already done - if(!mDisplayInitialized) { + if (!mDisplayInitialized) { Status =3D InitializeDisplay (Instance); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { goto EXIT; } } =20 // Check if this mode is supported - if( ModeNumber >=3D This->Mode->MaxMode ) { - DEBUG((DEBUG_ERROR, "LcdGraphicsSetMode: ERROR - Unsupported mode numb= er %d .\n", ModeNumber )); + if (ModeNumber >=3D This->Mode->MaxMode) { + DEBUG ((DEBUG_ERROR, "LcdGraphicsSetMode: ERROR - Unsupported mode num= ber %d .\n", ModeNumber)); Status =3D EFI_UNSUPPORTED; goto EXIT; } =20 // Set the oscillator frequency to support the new mode Status =3D LcdPlatformSetMode (ModeNumber); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { Status =3D EFI_DEVICE_ERROR; goto EXIT; } =20 // Update the UEFI mode information This->Mode->Mode =3D ModeNumber; - LcdPlatformQueryMode (ModeNumber,&Instance->ModeInfo); - Status =3D LcdPlatformGetBpp(ModeNumber, &Bpp); - if (EFI_ERROR(Status)) { + LcdPlatformQueryMode (ModeNumber, &Instance->ModeInfo); + Status =3D LcdPlatformGetBpp (ModeNumber, &Bpp); + if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "LcdGraphicsSetMode: ERROR - Couldn't get bytes p= er pixel, status: %r\n", Status)); goto EXIT; } This->Mode->FrameBufferSize =3D Instance->ModeInfo.VerticalResolution * Instance->ModeInfo.PixelsPerScanLine - * GetBytesPerPixel(Bpp); + * GetBytesPerPixel (Bpp); =20 // Set the hardware to the new mode Status =3D LcdSetMode (ModeNumber); - if (EFI_ERROR(Status)) { + if (EFI_ERROR (Status)) { Status =3D EFI_DEVICE_ERROR; goto EXIT; } =20 - // The UEFI spec requires that we now clear the visible portions of the = output display to black. + // The UEFI spec requires that we now clear the visible portions of the + // output display to black. =20 // Set the fill colour to black SetMem (&FillColour, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0); @@ -361,7 +374,8 @@ LcdGraphicsSetMode ( 0, This->Mode->Info->HorizontalResolution, This->Mode->Info->VerticalResolution, - 0); + 0 + ); =20 EXIT: return Status; @@ -372,7 +386,7 @@ GetBytesPerPixel ( IN LCD_BPP Bpp ) { - switch(Bpp) { + switch (Bpp) { case LCD_BITS_PER_PIXEL_24: return 4; =20 diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPl= atformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c index b5e113b844d4e4df2e35ccd880c01344b4b8b9d7..0b0c4204fbc44bc9e90dce3d7b4= 10ce167d9f40c 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c @@ -1,6 +1,6 @@ /** @file PL111Lcd.c =20 - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -54,11 +54,11 @@ LcdInitialize ( ) { // Define start of the VRAM. This never changes for any graphics mode - MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress); - MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buff= er + MmioWrite32 (PL111_REG_LCD_UP_BASE, (UINT32)VramBaseAddress); + MmioWrite32 (PL111_REG_LCD_LP_BASE, 0); // We are not using a double buf= fer =20 // Disable all interrupts from the PL111 - MmioWrite32(PL111_REG_LCD_IMSC, 0); + MmioWrite32 (PL111_REG_LCD_IMSC, 0); =20 return EFI_SUCCESS; } @@ -81,37 +81,55 @@ LcdSetMode ( LCD_BPP LcdBpp; =20 // Set the video mode timings and other relevant information - Status =3D LcdPlatformGetTimings (ModeNumber, - &HRes,&HSync,&HBackPorch,&HFrontPorch, - &VRes,&VSync,&VBackPorch,&VFrontPorch); + Status =3D LcdPlatformGetTimings ( + ModeNumber, + &HRes, + &HSync, + &HBackPorch, + &HFrontPorch, + &VRes, + &VSync, + &VBackPorch, + &VFrontPorch + ); ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { + if (EFI_ERROR (Status)) { return EFI_DEVICE_ERROR; } =20 - Status =3D LcdPlatformGetBpp (ModeNumber,&LcdBpp); + Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { + if (EFI_ERROR (Status)) { return EFI_DEVICE_ERROR; } =20 // Disable the CLCD_LcdEn bit - LcdControl =3D MmioRead32( PL111_REG_LCD_CONTROL); - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1); + LcdControl =3D MmioRead32 (PL111_REG_LCD_CONTROL); + MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl & ~1); =20 // Set Timings - MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPo= rch, HSync, HRes)); - MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPo= rch, VSync, VRes)); - MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes)); + MmioWrite32 ( + PL111_REG_LCD_TIMING_0, + HOR_AXIS_PANEL (HBackPorch, HFrontPorch, HSync, HRes) + ); + + MmioWrite32 ( + PL111_REG_LCD_TIMING_1, + VER_AXIS_PANEL (VBackPorch, VFrontPorch, VSync, VRes) + ); + + MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY (HRes)); MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); =20 // PL111_REG_LCD_CONTROL - LcdControl =3D PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CT= RL_LCD_TFT | PL111_CTRL_BGR; - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); + LcdControl =3D PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP (LcdBpp) + | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR; + + MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl); =20 // Turn on power to the LCD Panel LcdControl |=3D PL111_CTRL_LCD_PWR; - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); + MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl); =20 return EFI_SUCCESS; } --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456962192395.735234804255; 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receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:12 +0100 Message-Id: <20170926201529.11644-3-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 02/19] ArmPlatformPkg: Tidy LcdGraphicsOutputDxe code: Added comments X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak There is no functional modification in this change As preparation for a Change (Rejig of LcdGraphicsOutPutDxe), some comments are modified and a few new comments are added. This is to prevent mixing formatting changes with functional changes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/Include/Library/LcdPlatformLib.h = | 80 +++++++++++++++----- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c | 63 ++++++++++++++- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c | 68 ++++++++++++++++- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c = | 20 +++++ ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c = | 4 +- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c = | 22 +++++- 6 files changed, 231 insertions(+), 26 deletions(-) diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformP= kg/Include/Library/LcdPlatformLib.h index 72ebcd02ddb321ee0dad51c87ac8ee876d9ca21c..48bdd8a51411137df040aa797fc= ff272785f7a35 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -18,9 +18,7 @@ =20 #define LCD_VRAM_SIZE SIZE_8MB =20 -// // Modes definitions -// #define VGA 0 #define SVGA 1 #define XGA 2 @@ -29,9 +27,7 @@ #define UXGA 5 #define HD 6 =20 -// // VGA Mode: 640 x 480 -// #define VGA_H_RES_PIXELS 640 #define VGA_V_RES_PIXELS 480 #define VGA_OSC_FREQUENCY 23750000 /* 0x016A6570 */ @@ -44,9 +40,7 @@ #define VGA_V_FRONT_PORCH ( 3 - 1) #define VGA_V_BACK_PORCH ( 13 - 1) =20 -// // SVGA Mode: 800 x 600 -// #define SVGA_H_RES_PIXELS 800 #define SVGA_V_RES_PIXELS 600 #define SVGA_OSC_FREQUENCY 38250000 /* 0x0247A610 */ @@ -59,9 +53,7 @@ #define SVGA_V_FRONT_PORCH ( 3 - 1) #define SVGA_V_BACK_PORCH ( 17 - 1) =20 -// // XGA Mode: 1024 x 768 -// #define XGA_H_RES_PIXELS 1024 #define XGA_V_RES_PIXELS 768 #define XGA_OSC_FREQUENCY 63500000 /* 0x03C8EEE0 */ @@ -74,9 +66,7 @@ #define XGA_V_FRONT_PORCH ( 3 - 1) #define XGA_V_BACK_PORCH ( 23 - 1) =20 -// // SXGA Mode: 1280 x 1024 -// #define SXGA_H_RES_PIXELS 1280 #define SXGA_V_RES_PIXELS 1024 #define SXGA_OSC_FREQUENCY 109000000 /* 0x067F3540 */ @@ -89,9 +79,7 @@ #define SXGA_V_FRONT_PORCH ( 3 - 1) #define SXGA_V_BACK_PORCH ( 29 - 1) =20 -// // WSXGA+ Mode: 1680 x 1050 -// #define WSXGA_H_RES_PIXELS 1680 #define WSXGA_V_RES_PIXELS 1050 #define WSXGA_OSC_FREQUENCY 147000000 /* 0x08C30AC0 */ @@ -104,9 +92,7 @@ #define WSXGA_V_FRONT_PORCH ( 4 - 1) #define WSXGA_V_BACK_PORCH ( 41 - 1) =20 -// // UXGA Mode: 1600 x 1200 -// #define UXGA_H_RES_PIXELS 1600 #define UXGA_V_RES_PIXELS 1200 #define UXGA_OSC_FREQUENCY 161000000 /* 0x0998AA40 */ @@ -119,9 +105,7 @@ #define UXGA_V_FRONT_PORCH ( 3 - 1) #define UXGA_V_BACK_PORCH ( 38 - 1) =20 -// // HD Mode: 1920 x 1080 -// #define HD_H_RES_PIXELS 1920 #define HD_V_RES_PIXELS 1080 #define HD_OSC_FREQUENCY 165000000 /* 0x09D5B340 */ @@ -134,10 +118,7 @@ #define HD_V_FRONT_PORCH ( 3 - 1) #define HD_V_BACK_PORCH ( 32 - 1) =20 -// // Colour Masks -// - #define LCD_24BPP_RED_MASK 0x00FF0000 #define LCD_24BPP_GREEN_MASK 0x0000FF00 #define LCD_24BPP_BLUE_MASK 0x000000FF @@ -171,34 +152,85 @@ typedef enum { LCD_BITS_PER_PIXEL_12_444 } LCD_BPP; =20 - +/** Platform related initialization function. + * + * @param IN Handle Handle to the LCD device instance. + * + * @retval EFI_SUCCESS Platform initialization success. + * @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformInitializeDisplay ( IN EFI_HANDLE Handle ); =20 +/** Reserve VRAM memory in DRAM for the frame buffer + * (unless it is reserved already). + * + * The allocated address can be used to set the frame buffer. + * @param OUT VramBaseAddress A pointer to the frame buffer address. + * @param OUT VramSize A pointer to the size of the frame + * buffer in bytes + * + * @retval EFI_SUCCESS Frame buffer memory allocation success. + * @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformGetVram ( OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, OUT UINTN* VramSize ); =20 +/** Return total number of modes. + * + * @retval UINT32 Mode Number. +**/ UINT32 LcdPlatformGetMaxMode ( VOID ); =20 +/** Set the requested display mode. + * + * @param IN ModeNumber Mode Number. + * @retval EFI_SUCCESS Set mode success. + * @retval EFI_INVALID_PARAMTER Requested mode not found. +**/ EFI_STATUS LcdPlatformSetMode ( IN UINT32 ModeNumber ); =20 +/** Return information for the requested mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT Info Pointer for returned mode information + * (on success). + * + * @retval EFI_SUCCESS Success if the requested mode is found. + * @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformQueryMode ( IN UINT32 ModeNumber, OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info ); =20 +/** Returns the display timing information for the requested mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT HRes Pointer to horizontal resolution. + * @param OUT HSync Pointer to horizontal sync width. + * @param OUT HBackPorch Pointer to horizontal back porch. + * @param OUT HFrontPorch Pointer to horizontal front porch. + * @param OUT VRes Pointer to vertical resolution. + * @param OUT VSync Pointer to vertical sync width. + * @param OUT VBackPorch Pointer to vertical back porch. + * @param OUT VFrontPorch Pointer to vertical front porch. + + * @retval EFI_SUCCESS Success if the requested mode is found. + * @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetTimings ( IN UINT32 ModeNumber, @@ -212,6 +244,14 @@ LcdPlatformGetTimings ( OUT UINT32* VFrontPorch ); =20 +/** Return bits per pixel information for a mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT Bpp Pointer to value Bytes Per Pixel. + * + * @retval EFI_SUCCESS The requested mode is found. + * @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetBpp ( IN UINT32 ModeNumber, diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/= HdLcdArmVExpress.c index 2041de5f63c72de6f0ce4047420c282507a1d04a..cfe3259d3c737de240350e8c3ea= b867b80c40948 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c @@ -44,7 +44,8 @@ typedef struct { UINT32 VFrontPorch; } LCD_RESOLUTION; =20 - +/** The display modes supported by the platform. +**/ LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, @@ -94,6 +95,11 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { NULL }; =20 +/** HDLCD Platform specific initialization function. + * + * @retval EFI_SUCCESS Plaform library initialization success. + * @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformInitializeDisplay ( IN EFI_HANDLE Handle @@ -124,6 +130,18 @@ LcdPlatformInitializeDisplay ( return Status; } =20 +/** Reserve VRAM memory in DRAM for the frame buffer + * (unless it is reserved already). + * + * The allocated address can be used to set the frame buffer. + * + * @param OUT VramBaseAddress A pointer to the frame buffer address. + * @param OUT VramSize A pointer to the size of the frame + * buffer in bytes + * + * @retval EFI_SUCCESS Frame buffer memory allocation success. + * @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformGetVram ( OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, @@ -170,6 +188,13 @@ LcdPlatformGetVram ( return EFI_SUCCESS; } =20 +/** Return total number of modes supported. + * + * Note: Valid mode numbers are 0 to MaxMode - 1 + * See Section 11.9 of the UEFI Specification 2.6 Errata A (Jan 2017) + * + * @retval UINT32 Mode Number. +**/ UINT32 LcdPlatformGetMaxMode(VOID) { @@ -178,6 +203,10 @@ LcdPlatformGetMaxMode(VOID) return (sizeof (mResolutions) / sizeof (LCD_RESOLUTION)); } =20 +/** Set the requested display mode. + * + * @param IN ModeNumber Mode Number. +**/ EFI_STATUS LcdPlatformSetMode ( IN UINT32 ModeNumber @@ -227,6 +256,15 @@ LcdPlatformSetMode ( return Status; } =20 +/** Return information for the requested mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT Info Pointer for returned mode information + * (on success). + * + * @retval EFI_SUCCESS Success if the requested mode is found. + * @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformQueryMode ( IN UINT32 ModeNumber, @@ -267,6 +305,21 @@ LcdPlatformQueryMode ( return EFI_SUCCESS; } =20 +/** Returns the display timing information for the requested mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT HRes Pointer to horizontal resolution. + * @param OUT HSync Pointer to horizontal sync width. + * @param OUT HBackPorch Pointer to horizontal back porch. + * @param OUT HFrontPorch Pointer to horizontal front porch. + * @param OUT VRes Pointer to vertical resolution. + * @param OUT VSync Pointer to vertical sync width. + * @param OUT VBackPorch Pointer to vertical back porch. + * @param OUT VFrontPorch Pointer to vertical front porch. + * + * @retval EFI_SUCCESS Success if the requested mode is found. + * @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetTimings ( IN UINT32 ModeNumber, @@ -296,6 +349,14 @@ LcdPlatformGetTimings ( return EFI_SUCCESS; } =20 +/** Return bits per pixel for a mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT Bpp Pointer to value Bits Per Pixel. + * + * @retval EFI_SUCCESS The requested mode is found. + * @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetBpp ( IN UINT32 ModeNumber, diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVEx= pressLib/PL111LcdArmVExpress.c index 8d046816454f642bced00e29c4e02093b74afd24..84880e5fd1dfe6f824b27e53926= f9bb32ff6cdf7 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c @@ -41,7 +41,8 @@ typedef struct { UINT32 VFrontPorch; } LCD_RESOLUTION; =20 - +/** The display modes supported by the platform. +**/ LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, @@ -151,7 +152,11 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { NULL }; =20 - +/** PL111 Platform specific initialization function. + * + * @retval EFI_SUCCESS Plaform library initialization success. + * @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformInitializeDisplay ( IN EFI_HANDLE Handle @@ -176,6 +181,18 @@ LcdPlatformInitializeDisplay ( return Status; } =20 +/** Reserve VRAM memory in DRAM for the frame buffer + * (unless it is reserved already). + * + * The allocated address can be used to set the frame buffer. + * + * @param OUT VramBaseAddress A pointer to the frame buffer address. + * @param OUT VramSize A pointer to the size of the frame + * buffer in bytes + * + * @retval EFI_SUCCESS Frame buffer memory allocation success. + * @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformGetVram ( OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, @@ -232,6 +249,13 @@ LcdPlatformGetVram ( return Status; } =20 +/** Return total number of modes supported. + * + * Note: Valid mode numbers are 0 to MaxMode - 1 + * See Section 11.9 of the UEFI Specification 2.6 Errata A (Jan 2017) + * + * @retval UINT32 Mode Number. +**/ UINT32 LcdPlatformGetMaxMode(VOID) { @@ -249,6 +273,14 @@ LcdPlatformGetMaxMode(VOID) return (PcdGet32 (PcdPL111LcdMaxMode)); } =20 +/** Set the requested display mode. + * + * @param IN ModeNumber Mode Number. + * + * @retval EFI_INVALID_PARAMETER Requested mode not found. + * @retval EFI_UNSUPPORTED PLL111 configuration not supported. + * @retval !(EFI_SUCCESS) Other errors. +**/ EFI_STATUS LcdPlatformSetMode ( IN UINT32 ModeNumber @@ -320,6 +352,15 @@ LcdPlatformSetMode ( return Status; } =20 +/** Return information for the requested mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT Info Pointer for returned mode information + * (on success). + * + * @retval EFI_SUCCESS Success if the requested mode is found. + * @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformQueryMode ( IN UINT32 ModeNumber, @@ -360,6 +401,21 @@ LcdPlatformQueryMode ( return EFI_SUCCESS; } =20 +/** Returns the display timing information for the requested mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT HRes Pointer to horizontal resolution. + * @param OUT HSync Pointer to horizontal sync width. + * @param OUT HBackPorch Pointer to horizontal back porch. + * @param OUT HFrontPorch Pointer to horizontal front porch. + * @param OUT VRes Pointer to vertical resolution. + * @param OUT VSync Pointer to vertical sync width. + * @param OUT VBackPorch Pointer to vertical back porch. + * @param OUT VFrontPorch Pointer to vertical front porch. + * + * @retval EFI_SUCCESS Success if the requested mode is found. + * @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetTimings ( IN UINT32 ModeNumber, @@ -389,6 +445,14 @@ LcdPlatformGetTimings ( return EFI_SUCCESS; } =20 +/** Return bits per pixel for a mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT Bpp Pointer to value Bits Per Pixel. + * + * @retval EFI_SUCCESS The requested mode is found. + * @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ EFI_STATUS LcdPlatformGetBpp ( IN UINT32 ModeNumber, diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatf= ormPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c index eb0b6fb3fbbc1cb605469433f6c6dcb85bac668c..744dd3d556b5071defc6bcad5a9= a30881bcb4b6f 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c @@ -29,6 +29,12 @@ * **********************************************************************/ =20 +/** Initialize display. + * + * @param VramBaseAddress Address of the frame buffer. + * + * @retval EFI_SUCCESS Display initialization success. +**/ EFI_STATUS LcdInitialize ( IN EFI_PHYSICAL_ADDRESS VramBaseAddress @@ -67,6 +73,12 @@ LcdInitialize ( return EFI_SUCCESS; } =20 +/** Set requested mode of the display. + * + * @param ModeNumber Display mode number. + * @retval EFI_SUCCESS Display set mode success. + * @retval EFI_DEVICE_ERROR If mode not found/supported. +**/ EFI_STATUS LcdSetMode ( IN UINT32 ModeNumber @@ -136,6 +148,8 @@ LcdSetMode ( return EFI_SUCCESS; } =20 +/** De-initializes the display. +**/ VOID LcdShutdown ( VOID @@ -145,6 +159,12 @@ LcdShutdown ( MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); } =20 +/** Check for presence of HDLCD. + * + * @retval EFI_SUCCESS Platform implements HDLCD. + * @retval EFI_NOT_FOUND HDLCD display controller not + * found. +**/ EFI_STATUS LcdIdentify ( VOID diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputD= xe.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c index 2dd8f39873f77b1c211bff407cabe90c1795b121..c40c8e0fa6f4b5f7798aeb3c8bf= 3f261f14cb67b 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c @@ -357,8 +357,8 @@ LcdGraphicsSetMode ( goto EXIT; } =20 - // The UEFI spec requires that we now clear the visible portions of the - // output display to black. + /* The UEFI spec requires that we now clear the visible portions of the + * output display to black. */ =20 // Set the fill colour to black SetMem (&FillColour, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0); diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPl= atformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c index 0b0c4204fbc44bc9e90dce3d7b410ce167d9f40c..f8a3c1f8266c0a11f111c374768= 8defc0d49877c 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c @@ -26,6 +26,12 @@ * **********************************************************************/ =20 +/** Check for presence of PL111. + * + * @retval EFI_SUCCESS Platform implements PL111. + * @retval EFI_NOT_FOUND PL111 display controller not + * found. +**/ EFI_STATUS LcdIdentify ( VOID @@ -48,6 +54,12 @@ LcdIdentify ( return EFI_NOT_FOUND; } =20 +/** Initialize display. + * + * @param VramBaseAddress Address of the frame buffer. + * + * @retval EFI_SUCCESS Display initialization success. +**/ EFI_STATUS LcdInitialize ( IN EFI_PHYSICAL_ADDRESS VramBaseAddress @@ -63,6 +75,12 @@ LcdInitialize ( return EFI_SUCCESS; } =20 +/** Set requested mode of the display. + * + * @param ModeNumber Display mode number. + * @retval EFI_SUCCESS Display set mode success. + * @retval EFI_DEVICE_ERROR If mode not found/supported. +**/ EFI_STATUS LcdSetMode ( IN UINT32 ModeNumber @@ -123,7 +141,7 @@ LcdSetMode ( =20 // PL111_REG_LCD_CONTROL LcdControl =3D PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP (LcdBpp) - | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR; + | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR; =20 MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl); =20 @@ -134,6 +152,8 @@ LcdSetMode ( return EFI_SUCCESS; } =20 +/** De-initializes the display. +*/ VOID LcdShutdown ( VOID --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456959216416.81014996068336; Tue, 26 Sep 2017 13:15:59 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B77992095E516; Tue, 26 Sep 2017 13:12:29 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 41C9E21EC8D1B for ; Tue, 26 Sep 2017 13:12:25 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5S017392; Tue, 26 Sep 2017 21:15:35 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:13 +0100 Message-Id: <20170926201529.11644-4-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 03/19] ArmPlatformPkg: PL111 and HDLCD: add const qualifier X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds some STATIC and CONST qualifiers (mainly to arguments of functions) in PL111 and HdLcd modules. It doesn't add or modify any functionality. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c | 34 ++++++++++---------- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c | 34 ++++++++++---------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c = | 4 +-- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c = | 4 +-- 4 files changed, 38 insertions(+), 38 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/= HdLcdArmVExpress.c index cfe3259d3c737de240350e8c3eab867b80c40948..b9859a56988f7e5be0adbaa4904= 8a683fe586bfe 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c @@ -46,7 +46,7 @@ typedef struct { =20 /** The display modes supported by the platform. **/ -LCD_RESOLUTION mResolutions[] =3D { +STATIC CONST LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY, @@ -144,8 +144,8 @@ LcdPlatformInitializeDisplay ( **/ EFI_STATUS LcdPlatformGetVram ( - OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, - OUT UINTN* VramSize + OUT EFI_PHYSICAL_ADDRESS * CONST VramBaseAddress, + OUT UINTN * CONST VramSize ) { EFI_STATUS Status; @@ -209,7 +209,7 @@ LcdPlatformGetMaxMode(VOID) **/ EFI_STATUS LcdPlatformSetMode ( - IN UINT32 ModeNumber + IN CONST UINT32 ModeNumber ) { EFI_STATUS Status; @@ -267,8 +267,8 @@ LcdPlatformSetMode ( **/ EFI_STATUS LcdPlatformQueryMode ( - IN UINT32 ModeNumber, - OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info + IN CONST UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * CONST Info ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { @@ -322,15 +322,15 @@ LcdPlatformQueryMode ( **/ EFI_STATUS LcdPlatformGetTimings ( - IN UINT32 ModeNumber, - OUT UINT32* HRes, - OUT UINT32* HSync, - OUT UINT32* HBackPorch, - OUT UINT32* HFrontPorch, - OUT UINT32* VRes, - OUT UINT32* VSync, - OUT UINT32* VBackPorch, - OUT UINT32* VFrontPorch + IN CONST UINT32 ModeNumber, + OUT UINT32 * CONST HRes, + OUT UINT32 * CONST HSync, + OUT UINT32 * CONST HBackPorch, + OUT UINT32 * CONST HFrontPorch, + OUT UINT32 * CONST VRes, + OUT UINT32 * CONST VSync, + OUT UINT32 * CONST VBackPorch, + OUT UINT32 * CONST VFrontPorch ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { @@ -359,8 +359,8 @@ LcdPlatformGetTimings ( **/ EFI_STATUS LcdPlatformGetBpp ( - IN UINT32 ModeNumber, - OUT LCD_BPP * Bpp + IN CONST UINT32 ModeNumber, + OUT LCD_BPP * CONST Bpp ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVEx= pressLib/PL111LcdArmVExpress.c index 84880e5fd1dfe6f824b27e53926f9bb32ff6cdf7..6ae13f06d8b396ea1c67f0bcd73= 5a9d70f476400 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c @@ -43,7 +43,7 @@ typedef struct { =20 /** The display modes supported by the platform. **/ -LCD_RESOLUTION mResolutions[] =3D { +STATIC CONST LCD_RESOLUTION mResolutions[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY, @@ -195,8 +195,8 @@ LcdPlatformInitializeDisplay ( **/ EFI_STATUS LcdPlatformGetVram ( - OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, - OUT UINTN* VramSize + OUT EFI_PHYSICAL_ADDRESS * CONST VramBaseAddress, + OUT UINTN * CONST VramSize ) { EFI_STATUS Status; @@ -283,7 +283,7 @@ LcdPlatformGetMaxMode(VOID) **/ EFI_STATUS LcdPlatformSetMode ( - IN UINT32 ModeNumber + IN CONST UINT32 ModeNumber ) { EFI_STATUS Status; @@ -363,8 +363,8 @@ LcdPlatformSetMode ( **/ EFI_STATUS LcdPlatformQueryMode ( - IN UINT32 ModeNumber, - OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info + IN CONST UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * CONST Info ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { @@ -418,15 +418,15 @@ LcdPlatformQueryMode ( **/ EFI_STATUS LcdPlatformGetTimings ( - IN UINT32 ModeNumber, - OUT UINT32* HRes, - OUT UINT32* HSync, - OUT UINT32* HBackPorch, - OUT UINT32* HFrontPorch, - OUT UINT32* VRes, - OUT UINT32* VSync, - OUT UINT32* VBackPorch, - OUT UINT32* VFrontPorch + IN CONST UINT32 ModeNumber, + OUT UINT32 * CONST HRes, + OUT UINT32 * CONST HSync, + OUT UINT32 * CONST HBackPorch, + OUT UINT32 * CONST HFrontPorch, + OUT UINT32 * CONST VRes, + OUT UINT32 * CONST VSync, + OUT UINT32 * CONST VBackPorch, + OUT UINT32 * CONST VFrontPorch ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { @@ -455,8 +455,8 @@ LcdPlatformGetTimings ( **/ EFI_STATUS LcdPlatformGetBpp ( - IN UINT32 ModeNumber, - OUT LCD_BPP * Bpp + IN CONST UINT32 ModeNumber, + OUT LCD_BPP * CONST Bpp ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatf= ormPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c index 744dd3d556b5071defc6bcad5a9a30881bcb4b6f..5f950579720fb69e0a481f697a5= cc4038158b409 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c @@ -37,7 +37,7 @@ **/ EFI_STATUS LcdInitialize ( - IN EFI_PHYSICAL_ADDRESS VramBaseAddress + IN CONST EFI_PHYSICAL_ADDRESS VramBaseAddress ) { // Disable the controller @@ -81,7 +81,7 @@ LcdInitialize ( **/ EFI_STATUS LcdSetMode ( - IN UINT32 ModeNumber + IN CONST UINT32 ModeNumber ) { EFI_STATUS Status; diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPl= atformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c index f8a3c1f8266c0a11f111c3747688defc0d49877c..386e6140a69b045f77ee7fa60c4= 587d8bf4e7d54 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c @@ -62,7 +62,7 @@ LcdIdentify ( **/ EFI_STATUS LcdInitialize ( - IN EFI_PHYSICAL_ADDRESS VramBaseAddress + IN CONST EFI_PHYSICAL_ADDRESS VramBaseAddress ) { // Define start of the VRAM. This never changes for any graphics mode @@ -83,7 +83,7 @@ LcdInitialize ( **/ EFI_STATUS LcdSetMode ( - IN UINT32 ModeNumber + IN CONST UINT32 ModeNumber ) { EFI_STATUS Status; --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456955777413.2891198182675; Tue, 26 Sep 2017 13:15:55 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 832E321EC8D19; Tue, 26 Sep 2017 13:12:29 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3F22B21EC8D19 for ; Tue, 26 Sep 2017 13:12:25 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5T017392; Tue, 26 Sep 2017 21:15:35 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:14 +0100 Message-Id: <20170926201529.11644-5-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 04/19] ArmPlatformPkg: LcdGraphicsOurputDxe: Add debug asserts X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds some debug assertions e.g to catch NULL pointer errors missing in PL11Lcd and HdLcd modules. This change also improves related error handling code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c | 44 ++++++++++++++++++-- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c | 43 ++++++++++++++++++- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c = | 8 ++-- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c = | 8 ++-- 4 files changed, 90 insertions(+), 13 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/= HdLcdArmVExpress.c index b9859a56988f7e5be0adbaa49048a683fe586bfe..58dd9f0c77e1bc9af559a71d0c7= cce72d71c6da5 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c @@ -140,6 +140,7 @@ LcdPlatformInitializeDisplay ( * buffer in bytes * * @retval EFI_SUCCESS Frame buffer memory allocation success. + * @retval EFI_INVALID_PARAMETER VramBaseAddress or VramSize are NULL. * @retval !(EFI_SUCCESS) Other errors. **/ EFI_STATUS @@ -151,6 +152,13 @@ LcdPlatformGetVram ( EFI_STATUS Status; EFI_ALLOCATE_TYPE AllocationType; =20 + // Check VramBaseAddress and VramSize are not NULL. + if (VramBaseAddress =3D=3D NULL || VramSize =3D=3D NULL) { + ASSERT (VramBaseAddress !=3D NULL); + ASSERT (VramSize !=3D NULL); + return EFI_INVALID_PARAMETER; + } + // Set the vram size *VramSize =3D LCD_VRAM_SIZE; =20 @@ -169,6 +177,7 @@ LcdPlatformGetVram ( VramBaseAddress ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } =20 @@ -179,8 +188,8 @@ LcdPlatformGetVram ( *VramSize, EFI_MEMORY_WC ); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } @@ -215,6 +224,7 @@ LcdPlatformSetMode ( EFI_STATUS Status; =20 if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (ModeNumber < LcdPlatformGetMaxMode ()); return EFI_INVALID_PARAMETER; } =20 @@ -264,6 +274,7 @@ LcdPlatformSetMode ( * * @retval EFI_SUCCESS Success if the requested mode is found. * @retval EFI_INVALID_PARAMETER Requested mode not found. + * @retval EFI_INVALID_PARAMETER Info is NULL. **/ EFI_STATUS LcdPlatformQueryMode ( @@ -271,7 +282,9 @@ LcdPlatformQueryMode ( OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * CONST Info ) { - if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + if (ModeNumber >=3D LcdPlatformGetMaxMode () || Info =3D=3D NULL) { + ASSERT (ModeNumber < LcdPlatformGetMaxMode ()); + ASSERT (Info !=3D NULL); return EFI_INVALID_PARAMETER; } =20 @@ -334,6 +347,28 @@ LcdPlatformGetTimings ( ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (ModeNumber < LcdPlatformGetMaxMode ()); + return EFI_INVALID_PARAMETER; + } + + if (HRes =3D=3D NULL + || HSync =3D=3D NULL + || HBackPorch =3D=3D NULL + || HFrontPorch =3D=3D NULL + || VRes =3D=3D NULL + || VSync =3D=3D NULL + || VBackPorch =3D=3D NULL + || VFrontPorch =3D=3D NULL) + { + // One of the pointers is NULL + ASSERT (HRes !=3D NULL); + ASSERT (HSync !=3D NULL); + ASSERT (HBackPorch !=3D NULL); + ASSERT (HFrontPorch !=3D NULL); + ASSERT (VRes !=3D NULL); + ASSERT (VSync !=3D NULL); + ASSERT (VBackPorch !=3D NULL); + ASSERT (VFrontPorch !=3D NULL); return EFI_INVALID_PARAMETER; } =20 @@ -356,6 +391,7 @@ LcdPlatformGetTimings ( * * @retval EFI_SUCCESS The requested mode is found. * @retval EFI_INVALID_PARAMETER Requested mode not found. + * @retval EFI_INVALID_PARAMETER Bpp is NULL. **/ EFI_STATUS LcdPlatformGetBpp ( @@ -363,7 +399,9 @@ LcdPlatformGetBpp ( OUT LCD_BPP * CONST Bpp ) { - if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + if (ModeNumber >=3D LcdPlatformGetMaxMode () || Bpp =3D=3D NULL) { + ASSERT (ModeNumber < LcdPlatformGetMaxMode ()); + ASSERT (Bpp !=3D NULL); return EFI_INVALID_PARAMETER; } =20 diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVEx= pressLib/PL111LcdArmVExpress.c index 6ae13f06d8b396ea1c67f0bcd735a9d70f476400..5a4abd4c6f9e84d3d690af7233c= 1cebfe1ad339b 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c @@ -191,6 +191,7 @@ LcdPlatformInitializeDisplay ( * buffer in bytes * * @retval EFI_SUCCESS Frame buffer memory allocation success. + * @retval EFI_INVALID_PARAMETER VramBaseAddress or VramSize is NULL. * @retval !(EFI_SUCCESS) Other errors. **/ EFI_STATUS @@ -203,6 +204,13 @@ LcdPlatformGetVram ( =20 Status =3D EFI_SUCCESS; =20 + // Check VramBaseAddress and VramSize are not NULL. + if (VramBaseAddress =3D=3D NULL || VramSize =3D=3D NULL) { + ASSERT (VramBaseAddress !=3D NULL); + ASSERT (VramSize !=3D NULL); + return EFI_INVALID_PARAMETER; + } + // Is it on the motherboard or on the daughterboard? switch (PL111_CLCD_SITE) { =20 @@ -223,6 +231,7 @@ LcdPlatformGetVram ( VramBaseAddress ); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); return Status; } =20 @@ -233,8 +242,8 @@ LcdPlatformGetVram ( *VramSize, EFI_MEMORY_WC ); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); return Status; } @@ -293,6 +302,7 @@ LcdPlatformSetMode ( UINT32 SysId; =20 if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (ModeNumber < LcdPlatformGetMaxMode ()); return EFI_INVALID_PARAMETER; } =20 @@ -359,6 +369,7 @@ LcdPlatformSetMode ( * (on success). * * @retval EFI_SUCCESS Success if the requested mode is found. + * @retval EFI_INVALID_PARAMETER Info is NULL. * @retval EFI_INVALID_PARAMETER Requested mode not found. **/ EFI_STATUS @@ -367,7 +378,9 @@ LcdPlatformQueryMode ( OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * CONST Info ) { - if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + if (ModeNumber >=3D LcdPlatformGetMaxMode () || Info =3D=3D NULL) { + ASSERT (ModeNumber < LcdPlatformGetMaxMode ()); + ASSERT (Info !=3D NULL); return EFI_INVALID_PARAMETER; } =20 @@ -415,6 +428,7 @@ LcdPlatformQueryMode ( * * @retval EFI_SUCCESS Success if the requested mode is found. * @retval EFI_INVALID_PARAMETER Requested mode not found. + * @retval EFI_INVALID_PARAMETER One of the OUT parameters is NULL. **/ EFI_STATUS LcdPlatformGetTimings ( @@ -430,6 +444,28 @@ LcdPlatformGetTimings ( ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (ModeNumber < LcdPlatformGetMaxMode ()); + return EFI_INVALID_PARAMETER; + } + + if (HRes =3D=3D NULL + || HSync =3D=3D NULL + || HBackPorch =3D=3D NULL + || HFrontPorch =3D=3D NULL + || VRes =3D=3D NULL + || VSync =3D=3D NULL + || VBackPorch =3D=3D NULL + || VFrontPorch =3D=3D NULL) + { + // One of the pointers is NULL + ASSERT (HRes !=3D NULL); + ASSERT (HSync !=3D NULL); + ASSERT (HBackPorch !=3D NULL); + ASSERT (HFrontPorch !=3D NULL); + ASSERT (VRes !=3D NULL); + ASSERT (VSync !=3D NULL); + ASSERT (VBackPorch !=3D NULL); + ASSERT (VFrontPorch !=3D NULL); return EFI_INVALID_PARAMETER; } =20 @@ -452,6 +488,7 @@ LcdPlatformGetTimings ( * * @retval EFI_SUCCESS The requested mode is found. * @retval EFI_INVALID_PARAMETER Requested mode not found. + * @retval EFI_INVALID_PARAMETER Bpp is NULL. **/ EFI_STATUS LcdPlatformGetBpp ( @@ -460,6 +497,8 @@ LcdPlatformGetBpp ( ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + ASSERT (ModeNumber < LcdPlatformGetMaxMode ()); + ASSERT (Bpp !=3D NULL); return EFI_INVALID_PARAMETER; } =20 diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatf= ormPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c index 5f950579720fb69e0a481f697a5cc4038158b409..a266671a26f01d31e8ddb0cf7cb= fe59d2f4dc49c 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c @@ -109,15 +109,15 @@ LcdSetMode ( &VBackPorch, &VFrontPorch ); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { - return EFI_DEVICE_ERROR; + ASSERT_EFI_ERROR (Status); + return Status; } =20 Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { - return EFI_DEVICE_ERROR; + ASSERT_EFI_ERROR (Status); + return Status; } =20 BytesPerPixel =3D GetBytesPerPixel (LcdBpp); diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPl= atformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c index 386e6140a69b045f77ee7fa60c4587d8bf4e7d54..f432c8d802614e8a0e4ddab3898= f6e0dbf9a1572 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c @@ -110,15 +110,15 @@ LcdSetMode ( &VBackPorch, &VFrontPorch ); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { - return EFI_DEVICE_ERROR; + ASSERT_EFI_ERROR (Status); + return Status; } =20 Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); - ASSERT_EFI_ERROR (Status); if (EFI_ERROR (Status)) { - return EFI_DEVICE_ERROR; + ASSERT_EFI_ERROR (Status); + return Status; } =20 // Disable the CLCD_LcdEn bit --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456942811685.1274538590952; Tue, 26 Sep 2017 13:15:42 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3BF3921EC8D1B; Tue, 26 Sep 2017 13:12:28 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3C78221EC8D16 for ; Tue, 26 Sep 2017 13:12:25 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5U017392; Tue, 26 Sep 2017 21:15:36 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:15 +0100 Message-Id: <20170926201529.11644-6-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 05/19] ArmPlatformPkg: PL111LcdArmVExpressLib: Minor code cleanup X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This minor change removes some unecessary initializations and variables in PL111LcdArmVExpress.c Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVEx= pressLib/PL111LcdArmVExpress.c index 5a4abd4c6f9e84d3d690af7233c1cebfe1ad339b..b25a1ba93dbfd8f6450dbdf9719= 4c15c30defa20 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c @@ -202,8 +202,6 @@ LcdPlatformGetVram ( { EFI_STATUS Status; =20 - Status =3D EFI_SUCCESS; - // Check VramBaseAddress and VramSize are not NULL. if (VramBaseAddress =3D=3D NULL || VramSize =3D=3D NULL) { ASSERT (VramBaseAddress !=3D NULL); @@ -217,6 +215,7 @@ LcdPlatformGetVram ( case ARM_VE_MOTHERBOARD_SITE: *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)PL111_CLCD_VRAM_MOTHERBOARD= _BASE; *VramSize =3D LCD_VRAM_SIZE; + Status =3D EFI_SUCCESS; break; =20 case ARM_VE_DAUGHTERBOARD_1_SITE: @@ -245,7 +244,6 @@ LcdPlatformGetVram ( if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); - return Status; } break; =20 @@ -296,7 +294,6 @@ LcdPlatformSetMode ( ) { EFI_STATUS Status; - UINT32 LcdSite; UINT32 OscillatorId; SYS_CONFIG_FUNCTION Function; UINT32 SysId; @@ -306,9 +303,7 @@ LcdPlatformSetMode ( return EFI_INVALID_PARAMETER; } =20 - LcdSite =3D PL111_CLCD_SITE; - - switch (LcdSite) { + switch (PL111_CLCD_SITE) { case ARM_VE_MOTHERBOARD_SITE: Function =3D SYS_CFG_OSC; OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; @@ -353,7 +348,7 @@ LcdPlatformSetMode ( } =20 // Set the multiplexer - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite); + Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456952627769.5790139040895; Tue, 26 Sep 2017 13:15:52 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 465C221E87996; Tue, 26 Sep 2017 13:12:29 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 435D321EC8D1C for ; Tue, 26 Sep 2017 13:12:25 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5V017392; Tue, 26 Sep 2017 21:15:36 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:16 +0100 Message-Id: <20170926201529.11644-7-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 06/19] ArmPlatformPkg: PL111Lcd: Replace magic number with macro X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak Minor code change, replaces magic number with macro in LCD disable. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPl= atformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c index f432c8d802614e8a0e4ddab3898f6e0dbf9a1572..12db9d910ed1d7874095a5f79fe= 588491811f75a 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c @@ -122,8 +122,7 @@ LcdSetMode ( } =20 // Disable the CLCD_LcdEn bit - LcdControl =3D MmioRead32 (PL111_REG_LCD_CONTROL); - MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl & ~1); + MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); =20 // Set Timings MmioWrite32 ( --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456949731854.5535150900473; Tue, 26 Sep 2017 13:15:49 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 04C0221E43B59; Tue, 26 Sep 2017 13:12:29 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3B31A21EC8CF4 for ; Tue, 26 Sep 2017 13:12:25 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5W017392; Tue, 26 Sep 2017 21:15:36 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:17 +0100 Message-Id: <20170926201529.11644-8-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 07/19] ArmPlatformPkg: PL111LcdArmVExpressLib: Use FixedPcdGet32 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak PcdPL111LcdVideoModeOscId and PcdPL111LcdMaxMode are declared as fixed PCDs. However code uses PcdGet32 call to get these values. This change replaces PcdGet32 with FixedPcdGet32. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf | 2 +- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdA= rmVExpressLib/PL111LcdArmVExpressLib.inf index 3fde707c33dbcbd8adbbf18bbba718b823194abc..1a044baf4698aa6bfa5cd6038f0= 1e84f7a633ea9 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpressLib.inf @@ -39,6 +39,6 @@ [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced gEfiEdidActiveProtocolGuid # Produced =20 -[Pcd] +[FixedPcd] gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVEx= pressLib/PL111LcdArmVExpress.c index b25a1ba93dbfd8f6450dbdf97194c15c30defa20..59006c4cfd771fdd7ca1dab9172= 8d4dafe2fe831 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c @@ -277,7 +277,7 @@ LcdPlatformGetMaxMode(VOID) */ =20 // Set the maximum mode allowed - return (PcdGet32 (PcdPL111LcdMaxMode)); + return (FixedPcdGet32 (PcdPL111LcdMaxMode)); } =20 /** Set the requested display mode. @@ -310,7 +310,7 @@ LcdPlatformSetMode ( break; case ARM_VE_DAUGHTERBOARD_1_SITE: Function =3D SYS_CFG_OSC_SITE1; - OscillatorId =3D (UINT32)PcdGet32 (PcdPL111LcdVideoModeOscId); + OscillatorId =3D FixedPcdGet32 (PcdPL111LcdVideoModeOscId); break; default: return EFI_UNSUPPORTED; --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456943941606.6847061574905; Tue, 26 Sep 2017 13:15:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7B05320945BAC; Tue, 26 Sep 2017 13:12:28 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3DCEF21EC8D17 for ; Tue, 26 Sep 2017 13:12:25 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5X017392; Tue, 26 Sep 2017 21:15:36 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:18 +0100 Message-Id: <20170926201529.11644-9-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 08/19] ArmPlatformPkg: PL11LcdArmVExpressLib: Improvement conditional X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak PL111_CLCD_SITE and ARM_VE_MOTHERBOARD_SITE are both constants and available at build time. Use conditional compilation to process the code based on the value of PL111_CLCD_SITE, instead of selecting code in a switch statement at runtime. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c | 40 +++++++------------- 1 file changed, 14 insertions(+), 26 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVEx= pressLib/PL111LcdArmVExpress.c index 59006c4cfd771fdd7ca1dab91728d4dafe2fe831..aa5a1ff9c1c25c51796b75230ca= 149ae3a92db4a 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c @@ -209,16 +209,11 @@ LcdPlatformGetVram ( return EFI_INVALID_PARAMETER; } =20 - // Is it on the motherboard or on the daughterboard? - switch (PL111_CLCD_SITE) { - - case ARM_VE_MOTHERBOARD_SITE: +#if (PL111_CLCD_SITE =3D=3D ARM_VE_MOTHERBOARD_SITE) *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)PL111_CLCD_VRAM_MOTHERBOARD= _BASE; *VramSize =3D LCD_VRAM_SIZE; Status =3D EFI_SUCCESS; - break; - - case ARM_VE_DAUGHTERBOARD_1_SITE: +#elif (PL111_CLCD_SITE =3D=3D ARM_VE_DAUGHTERBOARD_1_SITE) *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE; *VramSize =3D LCD_VRAM_SIZE; =20 @@ -245,13 +240,9 @@ LcdPlatformGetVram ( ASSERT_EFI_ERROR (Status); gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); } - break; - - default: - // Unsupported site - Status =3D EFI_UNSUPPORTED; - break; - } +#else +#error PL111LcdVExpressLib: Unsupported PL111_CLCD_SITE +#endif // (PL111_CLCD_SITE =3D=3D ARM_VE_MOTHERBOARD_SITE) =20 return Status; } @@ -303,18 +294,15 @@ LcdPlatformSetMode ( return EFI_INVALID_PARAMETER; } =20 - switch (PL111_CLCD_SITE) { - case ARM_VE_MOTHERBOARD_SITE: - Function =3D SYS_CFG_OSC; - OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; - break; - case ARM_VE_DAUGHTERBOARD_1_SITE: - Function =3D SYS_CFG_OSC_SITE1; - OscillatorId =3D FixedPcdGet32 (PcdPL111LcdVideoModeOscId); - break; - default: - return EFI_UNSUPPORTED; - } +#if (PL111_CLCD_SITE =3D=3D ARM_VE_MOTHERBOARD_SITE) + Function =3D SYS_CFG_OSC; + OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; +#elif (PL111_CLCD_SITE =3D=3D ARM_VE_DAUGHTERBOARD_1_SITE) + Function =3D SYS_CFG_OSC_SITE1; + OscillatorId =3D FixedPcdGet32 (PcdPL111LcdVideoModeOscId); +#else +#error PL111LcdVExpressLib: Unsupported PL111_CLCD_SITE +#endif // (PL111_CLCD_SITE =3D=3D ARM_VE_MOTHERBOARD_SITE) =20 // Set the video mode oscillator Status =3D ArmPlatformSysConfigSetDevice ( --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456965505107.47605475835314; Tue, 26 Sep 2017 13:16:05 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 260D621EC8D1C; Tue, 26 Sep 2017 13:12:30 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8035221EC8D1E for ; Tue, 26 Sep 2017 13:12:26 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5Y017392; Tue, 26 Sep 2017 21:15:37 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:19 +0100 Message-Id: <20170926201529.11644-10-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 09/19] ArmPlatformPkg: HdLcdArmVExpressLib: Use FixedPcdGet32 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak PcdHdLcdVideoModeOscId is declared as a fixed PCD. However code uses the PcdGet32 call to get this value. This change replaces PcdGet32 with FixedPcdGet32. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf | 2 +- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpres= sLib/HdLcdArmVExpressLib.inf index 4733bb8e662d64eca0976af21b2abb7036b4424b..bba851c9bd6089cee748b45f405= 99b24c1293785 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= pressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= pressLib.inf @@ -39,6 +39,6 @@ [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced gEfiEdidActiveProtocolGuid # Produced =20 -[Pcd] +[FixedPcd] gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/= HdLcdArmVExpress.c index 58dd9f0c77e1bc9af559a71d0c7cce72d71c6da5..7b258f1fc9291ed2086da1e32dd= 5d0c7e4818dbd 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c @@ -230,11 +230,11 @@ LcdPlatformSetMode ( =20 // Set the video mode oscillator do { - Status =3D ArmPlatformSysConfigSetDevice ( - SYS_CFG_OSC_SITE1, - PcdGet32 (PcdHdLcdVideoModeOscId), - mResolutions[ModeNumber].OscFreq - ); + Status =3D ArmPlatformSysConfigSetDevice ( + SYS_CFG_OSC_SITE1, + FixedPcdGet32 (PcdHdLcdVideoModeOscId), + mResolutions[ModeNumber].OscFreq + ); } while (Status =3D=3D EFI_TIMEOUT); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456976190602.414288417958; Tue, 26 Sep 2017 13:16:16 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D1CEB20945BBE; Tue, 26 Sep 2017 13:12:30 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id ACBB721E1B75A for ; Tue, 26 Sep 2017 13:12:26 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5Z017392; Tue, 26 Sep 2017 21:15:37 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:20 +0100 Message-Id: <20170926201529.11644-11-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 10/19] ArmPlatformPkg: HdLcdArmVExpressLib: Remove status check EFI_TIMEOUT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak None of the ArmPlatformSys* functions return EFI_TIMEOUT. Hence checking this in the do {} while loop in LcdPlatformSetMode is wrong. Therefore remove this comparision and as a result remove the do {} while loop. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/= HdLcdArmVExpress.c index 7b258f1fc9291ed2086da1e32dd5d0c7e4818dbd..a6c4f414685db907a3fbc9a0099= 69be8a09f7415 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c @@ -229,25 +229,21 @@ LcdPlatformSetMode ( } =20 // Set the video mode oscillator - do { Status =3D ArmPlatformSysConfigSetDevice ( SYS_CFG_OSC_SITE1, FixedPcdGet32 (PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq ); - } while (Status =3D=3D EFI_TIMEOUT); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } =20 // Set the DVI into the new mode - do { - Status =3D ArmPlatformSysConfigSet ( - SYS_CFG_DVIMODE, - mResolutions[ModeNumber].Mode - ); - } while (Status =3D=3D EFI_TIMEOUT); + Status =3D ArmPlatformSysConfigSet ( + SYS_CFG_DVIMODE, + mResolutions[ModeNumber].Mode + ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456972666137.60500556333523; Tue, 26 Sep 2017 13:16:12 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9BD7320945BBA; Tue, 26 Sep 2017 13:12:30 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A224F21EC8D16 for ; Tue, 26 Sep 2017 13:12:26 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5a017392; Tue, 26 Sep 2017 21:15:37 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:21 +0100 Message-Id: <20170926201529.11644-12-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 11/19] ArmPlatformPkg: Implement LcdIdentify function for HDLCD GOP X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak LcdIdentify function does not currently check presence of HDLCD controller. Implement this functionality by reading HDLCD_REG_VERSION and checking against the PRODUCT_ID field to detect presence of HDLCD controller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- ArmPlatformPkg/Include/Drivers/HdLcd.h | 4 +++- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c | 22 +++++++++++++++++= ++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/ArmPlatformPkg/Include/Drivers/HdLcd.h b/ArmPlatformPkg/Includ= e/Drivers/HdLcd.h index 6df97a9dfee60e9fda615cf3bea1b6a164a42333..69b47cd720bae86081753affe2f= 3fafc8aa6c4d0 100644 --- a/ArmPlatformPkg/Include/Drivers/HdLcd.h +++ b/ArmPlatformPkg/Include/Drivers/HdLcd.h @@ -1,6 +1,6 @@ /** @file HDLcd.h =20 - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD= License @@ -86,4 +86,6 @@ // Number of bytes per pixel #define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3) =20 +#define HDLCD_PRODUCT_ID 0x1CDC + #endif /* _HDLCD_H_ */ diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatf= ormPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c index a266671a26f01d31e8ddb0cf7cbfe59d2f4dc49c..33c555e75cafaf9affddd0992c4= bd9f9289f6703 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c @@ -159,6 +159,22 @@ LcdShutdown ( MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); } =20 +/** Get the HDLCD Product Id (from the version register). +**/ +STATIC +UINT32 GetHdlcdProductId(VOID) +{ + return ((MmioRead32 (HDLCD_REG_VERSION)) >> 16) ; +} + +/** Check if an HDLCD is present. +**/ +STATIC +BOOLEAN HdlcdPresent(VOID) +{ + return (GetHdlcdProductId() =3D=3D HDLCD_PRODUCT_ID); +} + /** Check for presence of HDLCD. * * @retval EFI_SUCCESS Platform implements HDLCD. @@ -170,5 +186,9 @@ LcdIdentify ( VOID ) { - return EFI_SUCCESS; + if (HdlcdPresent()) { + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; } --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456986427695.1268201481429; Tue, 26 Sep 2017 13:16:26 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8C0DC20945BCA; Tue, 26 Sep 2017 13:12:41 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7891221EC8D1A for ; Tue, 26 Sep 2017 13:12:27 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5b017392; Tue, 26 Sep 2017 21:15:37 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:22 +0100 Message-Id: <20170926201529.11644-13-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 12/19] ArmPlatformPkg: Redefine LcdPlatformGetTimings function X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak The LcdPlatformGetTimings interface function takes similar sets of multiple parameters for horizontal and vertical timings which can be aggregated in a common data type. This change defines a structure SCAN_TIMINGS for this which can be used to describe both horizontal and vertical scan timings, and accordingly redefines the LcdPlatformGetTiming interface, greatly reducing the amount of data passed about. Similarly the mode definition tables are also changed to use this data type and thus enable pass through access. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/Include/Library/LcdPlatformLib.h = | 32 ++-- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c | 122 +++++--------- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c | 177 ++++++++------------ ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c = | 55 +++--- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c = | 48 +++--- 5 files changed, 180 insertions(+), 254 deletions(-) diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformP= kg/Include/Library/LcdPlatformLib.h index 48bdd8a51411137df040aa797fcff272785f7a35..f2f345b18fd15f2cde159fd42d3= 208a28f598a1f 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -152,6 +152,14 @@ typedef enum { LCD_BITS_PER_PIXEL_12_444 } LCD_BPP; =20 +// Display timing settings. +typedef struct { + UINT32 Resolution; + UINT32 Sync; + UINT32 BackPorch; + UINT32 FrontPorch; +} SCAN_TIMINGS; + /** Platform related initialization function. * * @param IN Handle Handle to the LCD device instance. @@ -219,29 +227,19 @@ LcdPlatformQueryMode ( /** Returns the display timing information for the requested mode number. * * @param IN ModeNumber Mode Number. - * @param OUT HRes Pointer to horizontal resolution. - * @param OUT HSync Pointer to horizontal sync width. - * @param OUT HBackPorch Pointer to horizontal back porch. - * @param OUT HFrontPorch Pointer to horizontal front porch. - * @param OUT VRes Pointer to vertical resolution. - * @param OUT VSync Pointer to vertical sync width. - * @param OUT VBackPorch Pointer to vertical back porch. - * @param OUT VFrontPorch Pointer to vertical front porch. - + * @param OUT Horizontal Pointer to horizontal timing parameter= s. + * (Resolution, Sync, Back porch, Front p= orch) + * @param OUT Vertical Pointer to vertical timing parameters. + * (Resolution, Sync, Back porch, Front p= orch) + * * @retval EFI_SUCCESS Success if the requested mode is found. * @retval EFI_INVALID_PARAMETER Requested mode not found. **/ EFI_STATUS LcdPlatformGetTimings ( IN UINT32 ModeNumber, - OUT UINT32* HRes, - OUT UINT32* HSync, - OUT UINT32* HBackPorch, - OUT UINT32* HFrontPorch, - OUT UINT32* VRes, - OUT UINT32* VSync, - OUT UINT32* VBackPorch, - OUT UINT32* VFrontPorch + OUT CONST SCAN_TIMINGS **Horizontal, + OUT CONST SCAN_TIMINGS **Vertical ); =20 /** Return bits per pixel information for a mode number. diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/= HdLcdArmVExpress.c index a6c4f414685db907a3fbc9a009969be8a09f7415..dc2c5fb89923304c46d137ec8ea= efc9418548d06 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c @@ -30,58 +30,52 @@ =20 typedef struct { UINT32 Mode; - UINT32 HorizontalResolution; - UINT32 VerticalResolution; LCD_BPP Bpp; UINT32 OscFreq; =20 // These are used by HDLCD - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; -} LCD_RESOLUTION; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; +} DISPLAY_MODE; =20 /** The display modes supported by the platform. **/ -STATIC CONST LCD_RESOLUTION mResolutions[] =3D { +STATIC CONST DISPLAY_MODE mDisplayModes[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SXGA, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2), - SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, - SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH= }, + {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH} }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + UXGA, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2), - UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, - UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + {UXGA_H_RES_PIXELS, UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH= }, + {UXGA_V_RES_PIXELS, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH} }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + HD, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2), - HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, - HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + {HD_H_RES_PIXELS, HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH}, + {HD_V_RES_PIXELS, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH} } }; =20 @@ -209,7 +203,7 @@ LcdPlatformGetMaxMode(VOID) { /* The following line will report correctly the total number of graphics= modes * that could be supported by the graphics driver: */ - return (sizeof (mResolutions) / sizeof (LCD_RESOLUTION)); + return (sizeof (mDisplayModes) / sizeof (DISPLAY_MODE)); } =20 /** Set the requested display mode. @@ -232,7 +226,7 @@ LcdPlatformSetMode ( Status =3D ArmPlatformSysConfigSetDevice ( SYS_CFG_OSC_SITE1, FixedPcdGet32 (PcdHdLcdVideoModeOscId), - mResolutions[ModeNumber].OscFreq + mDisplayModes[ModeNumber].OscFreq ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); @@ -242,7 +236,7 @@ LcdPlatformSetMode ( // Set the DVI into the new mode Status =3D ArmPlatformSysConfigSet ( SYS_CFG_DVIMODE, - mResolutions[ModeNumber].Mode + mDisplayModes[ModeNumber].Mode ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); @@ -285,11 +279,11 @@ LcdPlatformQueryMode ( } =20 Info->Version =3D 0; - Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; - Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; - Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; + Info->HorizontalResolution =3D mDisplayModes[ModeNumber].Horizontal.Reso= lution; + Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; + Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 - switch (mResolutions[ModeNumber].Bpp) { + switch (mDisplayModes[ModeNumber].Bpp) { case LCD_BITS_PER_PIXEL_24: Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; @@ -317,29 +311,20 @@ LcdPlatformQueryMode ( /** Returns the display timing information for the requested mode number. * * @param IN ModeNumber Mode Number. - * @param OUT HRes Pointer to horizontal resolution. - * @param OUT HSync Pointer to horizontal sync width. - * @param OUT HBackPorch Pointer to horizontal back porch. - * @param OUT HFrontPorch Pointer to horizontal front porch. - * @param OUT VRes Pointer to vertical resolution. - * @param OUT VSync Pointer to vertical sync width. - * @param OUT VBackPorch Pointer to vertical back porch. - * @param OUT VFrontPorch Pointer to vertical front porch. + * @param OUT Horizontal Pointer to horizontal timing parameter= s. + * (Resolution, Sync, Back porch, Front p= orch) + * @param OUT Vertical Pointer to vertical timing parameters. + * (Resolution, Sync, Back porch, Front p= orch) + * * @retval EFI_SUCCESS Success if the requested mode is found. * @retval EFI_INVALID_PARAMETER Requested mode not found. **/ EFI_STATUS LcdPlatformGetTimings ( - IN CONST UINT32 ModeNumber, - OUT UINT32 * CONST HRes, - OUT UINT32 * CONST HSync, - OUT UINT32 * CONST HBackPorch, - OUT UINT32 * CONST HFrontPorch, - OUT UINT32 * CONST VRes, - OUT UINT32 * CONST VSync, - OUT UINT32 * CONST VBackPorch, - OUT UINT32 * CONST VFrontPorch + IN CONST UINT32 ModeNumber, + OUT CONST SCAN_TIMINGS ** Horizontal, + OUT CONST SCAN_TIMINGS ** Vertical ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { @@ -347,35 +332,14 @@ LcdPlatformGetTimings ( return EFI_INVALID_PARAMETER; } =20 - if (HRes =3D=3D NULL - || HSync =3D=3D NULL - || HBackPorch =3D=3D NULL - || HFrontPorch =3D=3D NULL - || VRes =3D=3D NULL - || VSync =3D=3D NULL - || VBackPorch =3D=3D NULL - || VFrontPorch =3D=3D NULL) - { - // One of the pointers is NULL - ASSERT (HRes !=3D NULL); - ASSERT (HSync !=3D NULL); - ASSERT (HBackPorch !=3D NULL); - ASSERT (HFrontPorch !=3D NULL); - ASSERT (VRes !=3D NULL); - ASSERT (VSync !=3D NULL); - ASSERT (VBackPorch !=3D NULL); - ASSERT (VFrontPorch !=3D NULL); + if (Horizontal =3D=3D NULL || Vertical =3D=3D NULL) { + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); return EFI_INVALID_PARAMETER; } =20 - *HRes =3D mResolutions[ModeNumber].HorizontalResolution; - *HSync =3D mResolutions[ModeNumber].HSync; - *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; - *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; - *VRes =3D mResolutions[ModeNumber].VerticalResolution; - *VSync =3D mResolutions[ModeNumber].VSync; - *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; - *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; + *Horizontal =3D &mDisplayModes[ModeNumber].Horizontal; + *Vertical =3D &mDisplayModes[ModeNumber].Vertical; =20 return EFI_SUCCESS; } @@ -401,7 +365,7 @@ LcdPlatformGetBpp ( return EFI_INVALID_PARAMETER; } =20 - *Bpp =3D mResolutions[ModeNumber].Bpp; + *Bpp =3D mDisplayModes[ModeNumber].Bpp; =20 return EFI_SUCCESS; } diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVEx= pressLib/PL111LcdArmVExpress.c index aa5a1ff9c1c25c51796b75230ca149ae3a92db4a..753c5b615361f83625cdd4f0506= 909721da014b6 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c @@ -28,117 +28,111 @@ =20 typedef struct { UINT32 Mode; - UINT32 HorizontalResolution; - UINT32 VerticalResolution; LCD_BPP Bpp; UINT32 OscFreq; =20 - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; -} LCD_RESOLUTION; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; +} DISPLAY_MODE; =20 /** The display modes supported by the platform. **/ -STATIC CONST LCD_RESOLUTION mResolutions[] =3D { +STATIC CONST DISPLAY_MODE mDisplayModes[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + VGA, LCD_BITS_PER_PIXEL_24, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SVGA, LCD_BITS_PER_PIXEL_24, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_POR= CH}, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_POR= CH} }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + XGA, LCD_BITS_PER_PIXEL_24, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + SXGA, LCD_BITS_PER_PIXEL_24, (SXGA_OSC_FREQUENCY/2), - SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, - SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_POR= CH}, + {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_POR= CH} }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + UXGA, LCD_BITS_PER_PIXEL_24, (UXGA_OSC_FREQUENCY/2), - UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, - UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + {UXGA_H_RES_PIXELS, UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_POR= CH}, + {UXGA_V_RES_PIXELS, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_POR= CH} }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, + HD, LCD_BITS_PER_PIXEL_24, (HD_OSC_FREQUENCY/2), - HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, - HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + {HD_H_RES_PIXELS, HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH}, + {HD_V_RES_PIXELS, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH} }, { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + VGA, LCD_BITS_PER_PIXEL_16_565, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_56= 5, + SVGA, LCD_BITS_PER_PIXEL_16_565, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_POR= CH}, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_POR= CH} }, { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, + XGA, LCD_BITS_PER_PIXEL_16_565, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 9 : VGA : 640 x 480 x 15 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + VGA, LCD_BITS_PER_PIXEL_16_555, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 10 : SVGA : 800 x 600 x 15 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_55= 5, + SVGA, LCD_BITS_PER_PIXEL_16_555, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_POR= CH}, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_POR= CH} }, { // Mode 11 : XGA : 1024 x 768 x 15 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + XGA, LCD_BITS_PER_PIXEL_16_555, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is deri= ved from Linux Kernel Driver Settings - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, + XGA, LCD_BITS_PER_PIXEL_16_555, 63500000, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + VGA, LCD_BITS_PER_PIXEL_12_444, VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_44= 4, + SVGA, LCD_BITS_PER_PIXEL_12_444, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_POR= CH}, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_POR= CH} }, { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, + XGA, LCD_BITS_PER_PIXEL_12_444, XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} } }; =20 @@ -308,7 +302,7 @@ LcdPlatformSetMode ( Status =3D ArmPlatformSysConfigSetDevice ( Function, OscillatorId, - mResolutions[ModeNumber].OscFreq + mDisplayModes[ModeNumber].OscFreq ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); @@ -326,7 +320,7 @@ LcdPlatformSetMode ( // Set the DVI into the new mode Status =3D ArmPlatformSysConfigSet ( SYS_CFG_DVIMODE, - mResolutions[ModeNumber].Mode + mDisplayModes[ModeNumber].Mode ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); @@ -368,11 +362,11 @@ LcdPlatformQueryMode ( } =20 Info->Version =3D 0; - Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; - Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; - Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; + Info->HorizontalResolution =3D mDisplayModes[ModeNumber].Horizontal.Reso= lution; + Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; + Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 - switch (mResolutions[ModeNumber].Bpp) { + switch (mDisplayModes[ModeNumber].Bpp) { case LCD_BITS_PER_PIXEL_24: Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; @@ -400,14 +394,10 @@ LcdPlatformQueryMode ( /** Returns the display timing information for the requested mode number. * * @param IN ModeNumber Mode Number. - * @param OUT HRes Pointer to horizontal resolution. - * @param OUT HSync Pointer to horizontal sync width. - * @param OUT HBackPorch Pointer to horizontal back porch. - * @param OUT HFrontPorch Pointer to horizontal front porch. - * @param OUT VRes Pointer to vertical resolution. - * @param OUT VSync Pointer to vertical sync width. - * @param OUT VBackPorch Pointer to vertical back porch. - * @param OUT VFrontPorch Pointer to vertical front porch. + * @param OUT Horizontal Pointer to horizontal timing parameter= s. + * (Resolution, Sync, Back porch, Front p= orch) + * @param OUT Vertical Pointer to vertical timing parameters. + * (Resolution, Sync, Back porch, Front p= orch) * * @retval EFI_SUCCESS Success if the requested mode is found. * @retval EFI_INVALID_PARAMETER Requested mode not found. @@ -415,15 +405,9 @@ LcdPlatformQueryMode ( **/ EFI_STATUS LcdPlatformGetTimings ( - IN CONST UINT32 ModeNumber, - OUT UINT32 * CONST HRes, - OUT UINT32 * CONST HSync, - OUT UINT32 * CONST HBackPorch, - OUT UINT32 * CONST HFrontPorch, - OUT UINT32 * CONST VRes, - OUT UINT32 * CONST VSync, - OUT UINT32 * CONST VBackPorch, - OUT UINT32 * CONST VFrontPorch + IN CONST UINT32 ModeNumber, + OUT CONST SCAN_TIMINGS ** Horizontal, + OUT CONST SCAN_TIMINGS ** Vertical ) { if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { @@ -431,35 +415,16 @@ LcdPlatformGetTimings ( return EFI_INVALID_PARAMETER; } =20 - if (HRes =3D=3D NULL - || HSync =3D=3D NULL - || HBackPorch =3D=3D NULL - || HFrontPorch =3D=3D NULL - || VRes =3D=3D NULL - || VSync =3D=3D NULL - || VBackPorch =3D=3D NULL - || VFrontPorch =3D=3D NULL) + if (Horizontal =3D=3D NULL || Vertical =3D=3D NULL) { // One of the pointers is NULL - ASSERT (HRes !=3D NULL); - ASSERT (HSync !=3D NULL); - ASSERT (HBackPorch !=3D NULL); - ASSERT (HFrontPorch !=3D NULL); - ASSERT (VRes !=3D NULL); - ASSERT (VSync !=3D NULL); - ASSERT (VBackPorch !=3D NULL); - ASSERT (VFrontPorch !=3D NULL); + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); return EFI_INVALID_PARAMETER; } =20 - *HRes =3D mResolutions[ModeNumber].HorizontalResolution; - *HSync =3D mResolutions[ModeNumber].HSync; - *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; - *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; - *VRes =3D mResolutions[ModeNumber].VerticalResolution; - *VSync =3D mResolutions[ModeNumber].VSync; - *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; - *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; + *Horizontal =3D &mDisplayModes[ModeNumber].Horizontal; + *Vertical =3D &mDisplayModes[ModeNumber].Vertical; =20 return EFI_SUCCESS; } @@ -485,7 +450,7 @@ LcdPlatformGetBpp ( return EFI_INVALID_PARAMETER; } =20 - *Bpp =3D mResolutions[ModeNumber].Bpp; + *Bpp =3D mDisplayModes[ModeNumber].Bpp; =20 return EFI_SUCCESS; } diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatf= ormPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c index 33c555e75cafaf9affddd0992c4bd9f9289f6703..03153c06d314cb497c91889386c= a6075c0c9f718 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c @@ -84,35 +84,25 @@ LcdSetMode ( IN CONST UINT32 ModeNumber ) { - EFI_STATUS Status; - UINT32 HRes; - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VRes; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; - UINT32 BytesPerPixel; - LCD_BPP LcdBpp; + EFI_STATUS Status; + CONST SCAN_TIMINGS *Horizontal; + CONST SCAN_TIMINGS *Vertical; + UINT32 BytesPerPixel; + LCD_BPP LcdBpp; =20 =20 // Set the video mode timings and other relevant information Status =3D LcdPlatformGetTimings ( ModeNumber, - &HRes, - &HSync, - &HBackPorch, - &HFrontPorch, - &VRes, - &VSync, - &VBackPorch, - &VFrontPorch + &Horizontal, + &Vertical ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); =20 Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); if (EFI_ERROR (Status)) { @@ -126,21 +116,26 @@ LcdSetMode ( MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); =20 // Update the frame buffer information with the new settings - MmioWrite32 (HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel); - MmioWrite32 (HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel); - MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, VRes - 1); + MmioWrite32 ( + HDLCD_REG_FB_LINE_LENGTH, + Horizontal->Resolution * BytesPerPixel + ); + + MmioWrite32 (HDLCD_REG_FB_LINE_PITCH, Horizontal->Resolution * BytesPerP= ixel); + + MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, Vertical->Resolution - 1); =20 // Set the vertical timing information - MmioWrite32 (HDLCD_REG_V_SYNC, VSync); - MmioWrite32 (HDLCD_REG_V_BACK_PORCH, VBackPorch); - MmioWrite32 (HDLCD_REG_V_DATA, VRes - 1); - MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, VFrontPorch); + MmioWrite32 (HDLCD_REG_V_SYNC, Vertical->Sync); + MmioWrite32 (HDLCD_REG_V_BACK_PORCH, Vertical->BackPorch); + MmioWrite32 (HDLCD_REG_V_DATA, Vertical->Resolution - 1); + MmioWrite32 (HDLCD_REG_V_FRONT_PORCH, Vertical->FrontPorch); =20 // Set the horizontal timing information - MmioWrite32 (HDLCD_REG_H_SYNC, HSync); - MmioWrite32 (HDLCD_REG_H_BACK_PORCH, HBackPorch); - MmioWrite32 (HDLCD_REG_H_DATA, HRes - 1); - MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, HFrontPorch); + MmioWrite32 (HDLCD_REG_H_SYNC, Horizontal->Sync); + MmioWrite32 (HDLCD_REG_H_BACK_PORCH, Horizontal->BackPorch); + MmioWrite32 (HDLCD_REG_H_DATA, Horizontal->Resolution - 1); + MmioWrite32 (HDLCD_REG_H_FRONT_PORCH, Horizontal->FrontPorch); =20 // Enable the controller MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_ENABLE); diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPl= atformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c index 12db9d910ed1d7874095a5f79fe588491811f75a..6de60491e9fd0c5bca71e743aac= 2862ff85f6e7e 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c @@ -86,34 +86,24 @@ LcdSetMode ( IN CONST UINT32 ModeNumber ) { - EFI_STATUS Status; - UINT32 HRes; - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VRes; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; - UINT32 LcdControl; - LCD_BPP LcdBpp; + EFI_STATUS Status; + CONST SCAN_TIMINGS *Horizontal; + CONST SCAN_TIMINGS *Vertical; + UINT32 LcdControl; + LCD_BPP LcdBpp; =20 // Set the video mode timings and other relevant information Status =3D LcdPlatformGetTimings ( ModeNumber, - &HRes, - &HSync, - &HBackPorch, - &HFrontPorch, - &VRes, - &VSync, - &VBackPorch, - &VFrontPorch + &Horizontal, + &Vertical ); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); =20 Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); if (EFI_ERROR (Status)) { @@ -127,15 +117,29 @@ LcdSetMode ( // Set Timings MmioWrite32 ( PL111_REG_LCD_TIMING_0, - HOR_AXIS_PANEL (HBackPorch, HFrontPorch, HSync, HRes) + HOR_AXIS_PANEL ( + Horizontal->BackPorch, + Horizontal->FrontPorch, + Horizontal->Sync, + Horizontal->Resolution + ) ); =20 MmioWrite32 ( PL111_REG_LCD_TIMING_1, - VER_AXIS_PANEL (VBackPorch, VFrontPorch, VSync, VRes) + VER_AXIS_PANEL ( + Vertical->BackPorch, + Vertical->FrontPorch, + Vertical->Sync, + Vertical->Resolution + ) + ); + + MmioWrite32 ( + PL111_REG_LCD_TIMING_2, + CLK_SIG_POLARITY (Horizontal->Resolution) ); =20 - MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY (HRes)); MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); =20 // PL111_REG_LCD_CONTROL --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456979042589.3809526386342; Tue, 26 Sep 2017 13:16:19 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 16BDA20945BBD; Tue, 26 Sep 2017 13:12:41 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7897221EC8D1B for ; Tue, 26 Sep 2017 13:12:27 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5c017392; Tue, 26 Sep 2017 21:15:37 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:23 +0100 Message-Id: <20170926201529.11644-14-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 13/19] ArmPlatformPkg: HdLcd Remove redundant Bpp X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: EvanLloyd Because of copy/paste effects, HdLcdArmVExpress.c contained a table entry "LCD_BPP Bpp;" specifying the Bits per Pixel for each mode. However, all modes are LCD_BITS_PER_PIXEL_24. This change removes the table entry and related use of the field. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c | 42 ++++++-------------- 1 file changed, 13 insertions(+), 29 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/= HdLcdArmVExpress.c index dc2c5fb89923304c46d137ec8eaefc9418548d06..2401cdb30cb7252964ce1f363aa= 26d99933c09be 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c @@ -30,7 +30,6 @@ =20 typedef struct { UINT32 Mode; - LCD_BPP Bpp; UINT32 OscFreq; =20 // These are used by HDLCD @@ -42,37 +41,37 @@ typedef struct { **/ STATIC CONST DISPLAY_MODE mDisplayModes[] =3D { { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, LCD_BITS_PER_PIXEL_24, + VGA, VGA_OSC_FREQUENCY, {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} }, { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, LCD_BITS_PER_PIXEL_24, + SVGA, SVGA_OSC_FREQUENCY, {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} }, { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, LCD_BITS_PER_PIXEL_24, + XGA, XGA_OSC_FREQUENCY, {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} }, { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, LCD_BITS_PER_PIXEL_24, + SXGA, (SXGA_OSC_FREQUENCY/2), {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH= }, {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH} }, { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, LCD_BITS_PER_PIXEL_24, + UXGA, (UXGA_OSC_FREQUENCY/2), {UXGA_H_RES_PIXELS, UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH= }, {UXGA_V_RES_PIXELS, UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH} }, { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, LCD_BITS_PER_PIXEL_24, + HD, (HD_OSC_FREQUENCY/2), {HD_H_RES_PIXELS, HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH}, {HD_V_RES_PIXELS, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH} @@ -283,27 +282,12 @@ LcdPlatformQueryMode ( Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 - switch (mDisplayModes[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; - - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT (FALSE); - break; - } + /* Bits per Pixel is always LCD_BITS_PER_PIXEL_24 */ + Info->PixelFormat =3D PixelRedGreenBlueReserved8BitPer= Color; + Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; =20 return EFI_SUCCESS; } @@ -365,7 +349,7 @@ LcdPlatformGetBpp ( return EFI_INVALID_PARAMETER; } =20 - *Bpp =3D mDisplayModes[ModeNumber].Bpp; + *Bpp =3D LCD_BITS_PER_PIXEL_24; =20 return EFI_SUCCESS; } --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456990873880.5716091866216; Tue, 26 Sep 2017 13:16:30 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C6D0821E43B4C; Tue, 26 Sep 2017 13:12:41 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9D30C2007D1EB for ; Tue, 26 Sep 2017 13:12:27 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5d017392; Tue, 26 Sep 2017 21:15:38 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:24 +0100 Message-Id: <20170926201529.11644-15-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 14/19] ArmPlatformPkg: Add PCD to select pixel format X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak Current HDLCD and PL111 platform libraries do not support display modes with PixelBlueGreenRedReserved8BitPerColor format. i.e. because of historical confusion, they do not support the UEFI default! In LcdPlatformLib for PL111, LcdPlatformQueryMode returns the pixel format as PixelRedGreenBlueReserved8BitPerColor which is wrong, because that does not match the display controller's pixel format which is set to BGR in PL111Lcd GOP driver. Also it is not possible to configure pixel format as RGB/BGR for the display modes for a platform at build time. This change adds PcdGopPixelFormat to configure pixel format as PixelRedGreenBlueReserved8BitPerColor or PixelBlueGreenRedReserved8BitPerColor or PixelBitMask. With this change, pixel format can be selected in the platform specific .dsc file for all supported display modes. Support for PixelBitMask is not implemented in PL111 or HDLCD GOP driver, hence HDLCD and PL111 platform libraries will return error EFI_UNSUPPORTED if PcdGopPixelFormat is set to PixelBitMask. Indeed, it is not clear what selecting PixelBitMask might mean, but the option is allowed as it might suit a custom platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmPlatformPkg.dec = | 9 ++++- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf | 1 + ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf | 1 + ArmPlatformPkg/Include/Library/LcdPlatformLib.h = | 6 +++- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c | 23 ++++++++---- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c | 37 +++++++++----------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c = | 32 +++++++++++------ ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c = | 16 ++++++++- 8 files changed, 83 insertions(+), 42 deletions(-) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatform= Pkg.dec index b8a6b131632dc6788b73a034a41b9e3176dffafa..548d2b211753275337c6973e052= 27cee8451c185 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -1,6 +1,6 @@ #/** @file # -# Copyright (c) 2011-2016, ARM Limited. All rights reserved. +# Copyright (c) 2011-2017, ARM Limited. All rights reserved. # Copyright (c) 2015, Intel Corporation. All rights reserved. # # This program and the accompanying materials @@ -126,6 +126,13 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C =20 + # Graphics Output Pixel format + # 0 : PixelRedGreenBlueReserved8BitPerColor + # 1 : PixelBlueGreenRedReserved8BitPerColor + # 2 : PixelBitMask + # Default is set to UEFI console font format PixelBlueGreenRedReserved8B= itPerColor + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat|0x00000001|UINT32|0x00000040 + [PcdsFixedAtBuild.common,PcdsDynamic.common] ## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpres= sLib/HdLcdArmVExpressLib.inf index bba851c9bd6089cee748b45f40599b24c1293785..37756481596c7e978ed9ed0a932= eeb2aa0a3b657 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= pressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= pressLib.inf @@ -42,3 +42,4 @@ [Protocols] [FixedPcd] gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdA= rmVExpressLib/PL111LcdArmVExpressLib.inf index 1a044baf4698aa6bfa5cd6038f01e84f7a633ea9..6f1cb3b55ff814d007718b5597f= 821dd20100477 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpressLib.inf @@ -42,3 +42,4 @@ [Protocols] [FixedPcd] gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformP= kg/Include/Library/LcdPlatformLib.h index f2f345b18fd15f2cde159fd42d3208a28f598a1f..d357c22c46b62966859793372c4= 47883e12e1e80 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -139,7 +139,6 @@ #define LCD_12BPP_444_BLUE_MASK 0x0000000F #define LCD_12BPP_444_RESERVED_MASK 0x0000F000 =20 - // The enumeration indexes maps the PL111 LcdBpp values used in the LCD Co= ntrol Register typedef enum { LCD_BITS_PER_PIXEL_1 =3D 0, @@ -165,6 +164,10 @@ typedef struct { * @param IN Handle Handle to the LCD device instance. * * @retval EFI_SUCCESS Platform initialization success. + * @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + * PixelRedGreenBlueReserved8BitPerColor OR + * PixelBlueGreenRedReserved8BitPerColor + * any other format is not supported. * @retval !(EFI_SUCCESS) Other errors. **/ EFI_STATUS @@ -216,6 +219,7 @@ LcdPlatformSetMode ( * (on success). * * @retval EFI_SUCCESS Success if the requested mode is found. + * @retval EFI_INVALID_PARAMETER Info is NULL. * @retval EFI_INVALID_PARAMETER Requested mode not found. **/ EFI_STATUS diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/= HdLcdArmVExpress.c index 2401cdb30cb7252964ce1f363aa26d99933c09be..07730ed0d7a84b3fb64047bd101= 3fbc97301db53 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c @@ -15,7 +15,6 @@ #include =20 #include -#include #include #include #include @@ -91,6 +90,10 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { /** HDLCD Platform specific initialization function. * * @retval EFI_SUCCESS Plaform library initialization success. + * @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + * PixelRedGreenBlueReserved8BitPerColor OR + * PixelBlueGreenRedReserved8BitPerColor + * any other format is not supported. * @retval !(EFI_SUCCESS) Other errors. **/ EFI_STATUS @@ -99,6 +102,7 @@ LcdPlatformInitializeDisplay ( ) { EFI_STATUS Status; + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; =20 /* Set the FPGA multiplexer to select the video output from the * motherboard or the daughterboard */ @@ -120,6 +124,16 @@ LcdPlatformInitializeDisplay ( NULL ); =20 + // PixelBitMask and PixelBltOnly pixel formats are not supported + PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + if (PixelFormat !=3D PixelRedGreenBlueReserved8BitPerColor + && PixelFormat !=3D PixelBlueGreenRedReserved8BitPerColor) { + + ASSERT (PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor + || PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor); + return EFI_UNSUPPORTED; + } + return Status; } =20 @@ -282,12 +296,7 @@ LcdPlatformQueryMode ( Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 - /* Bits per Pixel is always LCD_BITS_PER_PIXEL_24 */ - Info->PixelFormat =3D PixelRedGreenBlueReserved8BitPer= Color; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; + Info->PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); =20 return EFI_SUCCESS; } diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVEx= pressLib/PL111LcdArmVExpress.c index 753c5b615361f83625cdd4f0506909721da014b6..31d5e037e42a51f1c08e5bf2fa2= 2eeb7be23e45f 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c @@ -149,6 +149,10 @@ EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { /** PL111 Platform specific initialization function. * * @retval EFI_SUCCESS Plaform library initialization success. + * @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + * PixelRedGreenBlueReserved8BitPerColor OR + * PixelBlueGreenRedReserved8BitPerColor + * any other format is not supported * @retval !(EFI_SUCCESS) Other errors. **/ EFI_STATUS @@ -157,6 +161,7 @@ LcdPlatformInitializeDisplay ( ) { EFI_STATUS Status; + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; =20 // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE); @@ -172,6 +177,16 @@ LcdPlatformInitializeDisplay ( ); } =20 + // PixelBitMask and PixelBltOnly pixel formats are not supported + PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + if (PixelFormat !=3D PixelRedGreenBlueReserved8BitPerColor + && PixelFormat !=3D PixelBlueGreenRedReserved8BitPerColor) { + + ASSERT (PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor + || PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor); + return EFI_UNSUPPORTED; + } + return Status; } =20 @@ -366,27 +381,7 @@ LcdPlatformQueryMode ( Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; =20 - switch (mDisplayModes[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; - - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT (FALSE); - break; - } + Info->PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); =20 return EFI_SUCCESS; } diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatf= ormPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c index 03153c06d314cb497c91889386ca6075c0c9f718..3ea7feca439e7ae9a610b6b3139= ddbfad3ac6f9c 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c @@ -22,6 +22,8 @@ =20 #include "LcdGraphicsOutputDxe.h" =20 +#define BYTES_PER_PIXEL 4 + /********************************************************************** * * This file contains all the bits of the Lcd that are @@ -66,10 +68,6 @@ LcdInitialize ( HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL ); =20 - MmioWrite32 (HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0)); - MmioWrite32 (HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8)); - MmioWrite32 (HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16)); - return EFI_SUCCESS; } =20 @@ -77,7 +75,8 @@ LcdInitialize ( * * @param ModeNumber Display mode number. * @retval EFI_SUCCESS Display set mode success. - * @retval EFI_DEVICE_ERROR If mode not found/supported. + * @retval EFI_DEVICE_ERROR Mode not found/supported. + * @retval !EFI_SUCCESS Other errors. **/ EFI_STATUS LcdSetMode ( @@ -87,9 +86,8 @@ LcdSetMode ( EFI_STATUS Status; CONST SCAN_TIMINGS *Horizontal; CONST SCAN_TIMINGS *Vertical; - UINT32 BytesPerPixel; - LCD_BPP LcdBpp; =20 + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; =20 // Set the video mode timings and other relevant information Status =3D LcdPlatformGetTimings ( @@ -104,13 +102,22 @@ LcdSetMode ( ASSERT (Horizontal !=3D NULL); ASSERT (Vertical !=3D NULL); =20 - Status =3D LcdPlatformGetBpp (ModeNumber, &LcdBpp); + // Get the pixel format information. + Status =3D LcdPlatformQueryMode (ModeNumber, &ModeInfo); if (EFI_ERROR (Status)) { ASSERT_EFI_ERROR (Status); return Status; } =20 - BytesPerPixel =3D GetBytesPerPixel (LcdBpp); + if (ModeInfo.PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor) { + MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8 | 16)); + MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8 | 0)); + } else { + MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8 | 16)); + MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8 | 0)); + } + + MmioWrite32 (HDLCD_REG_GREEN_SELECT, (8 << 8 | 8)); =20 // Disable the controller MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); @@ -118,10 +125,13 @@ LcdSetMode ( // Update the frame buffer information with the new settings MmioWrite32 ( HDLCD_REG_FB_LINE_LENGTH, - Horizontal->Resolution * BytesPerPixel + Horizontal->Resolution * BYTES_PER_PIXEL ); =20 - MmioWrite32 (HDLCD_REG_FB_LINE_PITCH, Horizontal->Resolution * BytesPerP= ixel); + MmioWrite32 ( + HDLCD_REG_FB_LINE_PITCH, + Horizontal->Resolution * BYTES_PER_PIXEL + ); =20 MmioWrite32 (HDLCD_REG_FB_LINE_COUNT, Vertical->Resolution - 1); =20 diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPl= atformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c index 6de60491e9fd0c5bca71e743aac2862ff85f6e7e..4bad2367982e16d5d23c4eab2e6= d91bf7db1c031 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c @@ -80,6 +80,7 @@ LcdInitialize ( * @param ModeNumber Display mode number. * @retval EFI_SUCCESS Display set mode success. * @retval EFI_DEVICE_ERROR If mode not found/supported. + @retval !EFI_SUCCESS Other errors. **/ EFI_STATUS LcdSetMode ( @@ -92,6 +93,8 @@ LcdSetMode ( UINT32 LcdControl; LCD_BPP LcdBpp; =20 + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; + // Set the video mode timings and other relevant information Status =3D LcdPlatformGetTimings ( ModeNumber, @@ -111,6 +114,13 @@ LcdSetMode ( return Status; } =20 + // Get the pixel format information. + Status =3D LcdPlatformQueryMode (ModeNumber, &ModeInfo); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + // Disable the CLCD_LcdEn bit MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); =20 @@ -144,7 +154,11 @@ LcdSetMode ( =20 // PL111_REG_LCD_CONTROL LcdControl =3D PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP (LcdBpp) - | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR; + | PL111_CTRL_LCD_TFT; + + if (ModeInfo.PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor) { + LcdControl |=3D PL111_CTRL_BGR; + } =20 MmioWrite32 (PL111_REG_LCD_CONTROL, LcdControl); =20 --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506456982551553.0428628244914; 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receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:25 +0100 Message-Id: <20170926201529.11644-16-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 15/19] ArmPlatformPkg: PCD to swap red/blue format for HDLCD X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds a new PCD PcdArmHdlcdSwapBlueRedSelect to swap values for HDLCD RED_SELECT and BLUE_SELECT registers on platforms where blue and red hardware lines are swapped. If set to TRUE in the platform dsc, HDLCD driver will swap the values while setting RED_SELECT and BLUE_SELECT registers. The default value of the PCD is FALSE. NOTE: The motive for this is that a discrepancy in the Red/Blue lines exists between some VersatileExpress platforms. Rather than have divergent code, this build switch allows a simple, pragmatic solution. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmPlatformPkg.dec | 3= +++ ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf | 1= + ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c | 4= ++++ 3 files changed, 8 insertions(+) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatform= Pkg.dec index 548d2b211753275337c6973e05227cee8451c185..77eb789ad8fe4ddcbf25abefad2= e7b7d3d5e1722 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -133,6 +133,9 @@ [PcdsFixedAtBuild.common] # Default is set to UEFI console font format PixelBlueGreenRedReserved8B= itPerColor gArmPlatformTokenSpaceGuid.PcdGopPixelFormat|0x00000001|UINT32|0x00000040 =20 + ## If set, this will swap settings for HDLCD RED_SELECT and BLUE_SELECT = registers + gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect|FALSE|BOOLEAN|0x= 00000045 + [PcdsFixedAtBuild.common,PcdsDynamic.common] ## PL031 RealTimeClock gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024 diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutpu= tDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputD= xe.inf index 26e580a594fc328187407ac4c1787f180fbf4b17..b050add98e3f9cf62ac33588319= 3b9d0928c3dc9 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf @@ -55,6 +55,7 @@ [Protocols] =20 [FixedPcd] gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase + gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect =20 [FeaturePcd] gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatf= ormPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c index 3ea7feca439e7ae9a610b6b3139ddbfad3ac6f9c..8f83d6ecba290994dbced1c11df= db6d705323c03 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c @@ -109,7 +109,11 @@ LcdSetMode ( return Status; } =20 +#if (!FixedPcdGetBool (PcdArmHdLcdSwapBlueRedSelect)) if (ModeInfo.PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor) { +#else + if (ModeInfo.PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor) { +#endif MmioWrite32 (HDLCD_REG_RED_SELECT, (8 << 8 | 16)); MmioWrite32 (HDLCD_REG_BLUE_SELECT, (8 << 8 | 0)); } else { --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506457007618539.4512270662821; Tue, 26 Sep 2017 13:16:47 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 72EC720945BD1; Tue, 26 Sep 2017 13:12:42 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5AD9120945BA4 for ; Tue, 26 Sep 2017 13:12:27 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5f017392; Tue, 26 Sep 2017 21:15:38 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:26 +0100 Message-Id: <20170926201529.11644-17-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 16/19] ArmPlatformPkg: Reorganize Lcd Graphics Output X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak Currently for ArmPlatformPkg, the UEFI Graphics Output Protocol is implemented using platform specific Libraries ((PL111|Hd)LcdArmVExpressLib) and DXE drivers ((PL111|Hd)LcdGraphicsOutputDxe). The platform library handles variations such as platform supported display modes, memory management of the frame buffer, and clock/mux setting. The DXE driver implements the GOP protocol and manages the respective display controller. Although this implementation works for current platforms, we think the way the current DXE driver sources are linked is sub-optimal and needs to be improved, before additions. This change effectively partitions HdLcd.c and PL111Lcd.c from LcdGraphicsOutputProtocol and creates two libraries of type LcdHwLib which can be selected in the platform specific .dsc file. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf | 3 +- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf | 2 +- ArmPlatformPkg/Drivers/{LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf = =3D> HdLcd/HdLcd.inf} | 25 +------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/{PL111LcdGraphicsOutputDxe.inf= =3D> LcdGraphicsOutputDxe.inf} | 15 ++--- ArmPlatformPkg/Drivers/{LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf= =3D> PL111Lcd/PL111Lcd.inf} | 28 ++------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h = | 21 ------- ArmPlatformPkg/Include/Drivers/LcdHw.h = | 64 ++++++++++++++++++++ ArmPlatformPkg/Include/Library/LcdPlatformLib.h = | 1 + ArmPlatformPkg/Drivers/{LcdGraphicsOutputDxe =3D> HdLcd}/HdLcd.c = | 3 +- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c = | 2 + ArmPlatformPkg/Drivers/{LcdGraphicsOutputDxe =3D> PL111Lcd}/PL111Lcd.c = | 5 +- 11 files changed, 85 insertions(+), 84 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpres= sLib/HdLcdArmVExpressLib.inf index 37756481596c7e978ed9ed0a932eeb2aa0a3b657..1fe93a53f81c46955c62383a2ba= d0e19a9662015 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= pressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= pressLib.inf @@ -18,7 +18,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D HdLcdArmVExpress FILE_GUID =3D 535a720e-06c0-4bb9-b563-452216abbed4 - MODULE_TYPE =3D DXE_DRIVER + MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D LcdPlatformLib =20 @@ -40,6 +40,5 @@ [Protocols] gEfiEdidActiveProtocolGuid # Produced =20 [FixedPcd] - gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId gArmPlatformTokenSpaceGuid.PcdGopPixelFormat diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdA= rmVExpressLib/PL111LcdArmVExpressLib.inf index 6f1cb3b55ff814d007718b5597f821dd20100477..f6d5bf76dd375d97bac63ca427c= c231792b9e52b 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpressLib.inf @@ -18,7 +18,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D PL111LcdArmVExpressLib FILE_GUID =3D b7f06f20-496f-11e0-a8e8-0002a5d5c51b - MODULE_TYPE =3D DXE_DRIVER + MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D LcdPlatformLib =20 diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutpu= tDxe.inf b/ArmPlatformPkg/Drivers/HdLcd/HdLcd.inf similarity index 59% rename from ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutput= Dxe.inf rename to ArmPlatformPkg/Drivers/HdLcd/HdLcd.inf index b050add98e3f9cf62ac335883193b9d0928c3dc9..e43c894538cfd7985862997aaa1= b8a381cb6423a 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf +++ b/ArmPlatformPkg/Drivers/HdLcd/HdLcd.inf @@ -16,15 +16,13 @@ =20 [Defines] INF_VERSION =3D 0x00010005 - BASE_NAME =3D HdLcdGraphicsDxe + BASE_NAME =3D HdLcd FILE_GUID =3D ce660500-824d-11e0-ac72-0002a5d5c51b - MODULE_TYPE =3D DXE_DRIVER + MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 - ENTRY_POINT =3D LcdGraphicsOutputDxeInitialize + LIBRARY_CLASS =3D LcdHwLib =20 [Sources.common] - LcdGraphicsOutputDxe.c - LcdGraphicsOutputBlt.c HdLcd.c =20 [Packages] @@ -39,26 +37,9 @@ [LibraryClasses] UefiLib BaseLib DebugLib - TimerLib - UefiDriverEntryPoint - UefiBootServicesTableLib IoLib - BaseMemoryLib - LcdPlatformLib - -[Protocols] - gEfiDevicePathProtocolGuid - gEfiGraphicsOutputProtocolGuid # Produced - gEfiEdidDiscoveredProtocolGuid # Produced - gEfiEdidActiveProtocolGuid # Produced - gEfiEdidOverrideProtocolGuid # Produced =20 [FixedPcd] gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect =20 -[FeaturePcd] - gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices - -[Depex] - gEfiCpuArchProtocolGuid diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOu= tputDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutput= Dxe.inf similarity index 78% copy from ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutpu= tDxe.inf copy to ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf index ad0348500326c4567f0e1b235c84b694e61306bf..edd03c7eb1c39e397c72a4c22e7= d05ab21b53def 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe= .inf +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf @@ -2,7 +2,7 @@ # # Component description file for PL111LcdGraphicsOutputDxe module # -# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
+# Copyright (c) 2017, ARM Ltd. All rights reserved.
# This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License # which accompanies this distribution. The full text of the license may = be found at @@ -15,8 +15,8 @@ =20 [Defines] INF_VERSION =3D 0x00010005 - BASE_NAME =3D PL111LcdGraphicsDxe - FILE_GUID =3D 407B4008-BF5B-11DF-9547-CF16E0D72085 + BASE_NAME =3D LcdGraphicsDxe + FILE_GUID =3D 89464DAE-8DAA-41FE-A4C8-40D2175AF1E9 MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 ENTRY_POINT =3D LcdGraphicsOutputDxeInitialize @@ -24,7 +24,6 @@ [Defines] [Sources.common] LcdGraphicsOutputDxe.c LcdGraphicsOutputBlt.c - PL111Lcd.c =20 [Packages] MdePkg/MdePkg.dec @@ -38,22 +37,18 @@ [LibraryClasses] UefiLib BaseLib DebugLib - TimerLib UefiDriverEntryPoint UefiBootServicesTableLib - IoLib BaseMemoryLib LcdPlatformLib + LcdHwLib =20 [Protocols] gEfiDevicePathProtocolGuid gEfiGraphicsOutputProtocolGuid =20 -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdPL111LcdBase - [FeaturePcd] gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices =20 [Depex] - gEfiCpuArchProtocolGuid + TRUE diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOu= tputDxe.inf b/ArmPlatformPkg/Drivers/PL111Lcd/PL111Lcd.inf similarity index 59% rename from ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOut= putDxe.inf rename to ArmPlatformPkg/Drivers/PL111Lcd/PL111Lcd.inf index ad0348500326c4567f0e1b235c84b694e61306bf..8e571a02476142af787db90c0ee= 240a784b74a63 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe= .inf +++ b/ArmPlatformPkg/Drivers/PL111Lcd/PL111Lcd.inf @@ -1,6 +1,6 @@ -#/** @file PL111LcdGraphicsOutputDxe.inf +#/** @file PL111Lcd.inf # -# Component description file for PL111LcdGraphicsOutputDxe module +# Component description file for PL111Lcd module # # Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
# This program and the accompanying materials @@ -15,15 +15,13 @@ =20 [Defines] INF_VERSION =3D 0x00010005 - BASE_NAME =3D PL111LcdGraphicsDxe + BASE_NAME =3D PL111Lcd FILE_GUID =3D 407B4008-BF5B-11DF-9547-CF16E0D72085 - MODULE_TYPE =3D DXE_DRIVER + MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 - ENTRY_POINT =3D LcdGraphicsOutputDxeInitialize + LIBRARY_CLASS =3D LcdHwLib =20 [Sources.common] - LcdGraphicsOutputDxe.c - LcdGraphicsOutputBlt.c PL111Lcd.c =20 [Packages] @@ -34,26 +32,10 @@ [Packages] ArmPlatformPkg/ArmPlatformPkg.dec =20 [LibraryClasses] - ArmLib UefiLib BaseLib DebugLib - TimerLib - UefiDriverEntryPoint - UefiBootServicesTableLib IoLib - BaseMemoryLib - LcdPlatformLib - -[Protocols] - gEfiDevicePathProtocolGuid - gEfiGraphicsOutputProtocolGuid =20 [FixedPcd] gArmPlatformTokenSpaceGuid.PcdPL111LcdBase - -[FeaturePcd] - gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices - -[Depex] - gEfiCpuArchProtocolGuid diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputD= xe.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h index 85e918de66624d61c6d0e05c5a67c516cd7619aa..76a710fda59279a6642dc2408c7= 90afcf49360b8 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h @@ -19,7 +19,6 @@ =20 #include #include -#include #include =20 #include @@ -92,7 +91,6 @@ UINTN GetBytesPerPixel ( IN LCD_BPP Bpp ); - EFI_STATUS EFIAPI GraphicsOutputDxeInitialize ( @@ -105,23 +103,4 @@ InitializeDisplay ( IN LCD_INSTANCE* Instance ); =20 -EFI_STATUS -LcdIdentify ( - VOID -); - -EFI_STATUS -LcdInitialize ( - EFI_PHYSICAL_ADDRESS VramBaseAddress -); - -EFI_STATUS -LcdSetMode ( - IN UINT32 ModeNumber -); - -VOID -LcdShutdown ( - VOID -); #endif /* LCD_GRAPHICS_OUTPUT_DXE_H_ */ diff --git a/ArmPlatformPkg/Include/Drivers/LcdHw.h b/ArmPlatformPkg/Includ= e/Drivers/LcdHw.h new file mode 100644 index 0000000000000000000000000000000000000000..1f5b9c0b7e7decbf1136614b5b1= b482ccd805604 --- /dev/null +++ b/ArmPlatformPkg/Include/Drivers/LcdHw.h @@ -0,0 +1,64 @@ +/** @file LcdHw.h + + This file contains interface functions for LcdHwLib of ArmPlatformPkg + + Copyright (c) 2017, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef LCD_HW_H_ +#define LCD_HW_H_ + +#include + +/** Check for presence of display + * + * @retval EFI_SUCCESS Platform implements display. + * @retval EFI_NOT_FOUND Display not found on the platform. + */ +EFI_STATUS +LcdIdentify ( + VOID +); + +/** Initialize display. + * + * @param FrameBaseAddress Address of the frame buffer. + * @retval EFI_SUCCESS Display initialization success. + * @retval !(EFI_SUCCESS) Display initialization failure. + * +**/ +EFI_STATUS +LcdInitialize ( + EFI_PHYSICAL_ADDRESS FrameBaseAddress +); + +/** Set requested mode of the display. + * + * @param ModeNumber Display mode number. + * @retval EFI_SUCCESS Display set mode success. + * @retval EFI_DEVICE_ERROR If mode not found/supported. + * +**/ +EFI_STATUS +LcdSetMode ( + IN UINT32 ModeNumber +); + + +/** De-initializes the display. + * +**/ +VOID +LcdShutdown ( + VOID +); + +#endif /* LCD_HW_H_ */ diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformP= kg/Include/Library/LcdPlatformLib.h index d357c22c46b62966859793372c447883e12e1e80..78b1780d82b8b698924cc55a292= c30728a3e7060 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -14,6 +14,7 @@ #ifndef LCD_PLATFORM_LIB_H_ #define LCD_PLATFORM_LIB_H_ =20 +#include #include =20 #define LCD_VRAM_SIZE SIZE_8MB diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatf= ormPkg/Drivers/HdLcd/HdLcd.c similarity index 95% rename from ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c rename to ArmPlatformPkg/Drivers/HdLcd/HdLcd.c index 8f83d6ecba290994dbced1c11dfdb6d705323c03..d0f678acc7ac539f4e05a9b35ce= 28baded6c7244 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ b/ArmPlatformPkg/Drivers/HdLcd/HdLcd.c @@ -19,8 +19,7 @@ #include =20 #include - -#include "LcdGraphicsOutputDxe.h" +#include =20 #define BYTES_PER_PIXEL 4 =20 diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputD= xe.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c index c40c8e0fa6f4b5f7798aeb3c8bf3f261f14cb67b..e47142319045783cf98243a1372= d933d89718922 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c @@ -20,6 +20,8 @@ =20 #include =20 +#include + #include "LcdGraphicsOutputDxe.h" =20 /********************************************************************** diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPl= atformPkg/Drivers/PL111Lcd/PL111Lcd.c similarity index 95% rename from ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c rename to ArmPlatformPkg/Drivers/PL111Lcd/PL111Lcd.c index 4bad2367982e16d5d23c4eab2e6d91bf7db1c031..439f4f9c1fd7c6339cfa75287f3= fa3718de34d92 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c +++ b/ArmPlatformPkg/Drivers/PL111Lcd/PL111Lcd.c @@ -11,13 +11,12 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 **/ - +#include #include #include =20 #include - -#include "LcdGraphicsOutputDxe.h" +#include =20 /********************************************************************** * --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:27 +0100 Message-Id: <20170926201529.11644-18-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 17/19] ArmPlatformPkg: Additional display modes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak Add definitions for new display modes such as HD 720. This has no effect on existing display drivers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- ArmPlatformPkg/Include/Library/LcdPlatformLib.h | 60 ++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h b/ArmPlatformP= kg/Include/Library/LcdPlatformLib.h index 78b1780d82b8b698924cc55a292c30728a3e7060..c5d90bd4faff2dadc6b36440249= ee8e0733616e0 100644 --- a/ArmPlatformPkg/Include/Library/LcdPlatformLib.h +++ b/ArmPlatformPkg/Include/Library/LcdPlatformLib.h @@ -27,6 +27,11 @@ #define WSXGA 4 #define UXGA 5 #define HD 6 +#define WVGA 7 +#define QHD 8 +#define WSVGA 9 +#define HD720 10 +#define WXGA 11 =20 // VGA Mode: 640 x 480 #define VGA_H_RES_PIXELS 640 @@ -119,6 +124,61 @@ #define HD_V_FRONT_PORCH ( 3 - 1) #define HD_V_BACK_PORCH ( 32 - 1) =20 +// WVGA Mode: 800 x 480 +#define WVGA_H_RES_PIXELS 800 +#define WVGA_V_RES_PIXELS 480 +#define WVGA_OSC_FREQUENCY 29500000 /* 0x01C22260 */ +#define WVGA_H_SYNC ( 72 - 1) +#define WVGA_H_FRONT_PORCH ( 24 - 1) +#define WVGA_H_BACK_PORCH ( 96 - 1) +#define WVGA_V_SYNC ( 7 - 1) +#define WVGA_V_FRONT_PORCH ( 3 - 1) +#define WVGA_V_BACK_PORCH ( 10 - 1) + +// QHD Mode: 960 x 540 +#define QHD_H_RES_PIXELS 960 +#define QHD_V_RES_PIXELS 540 +#define QHD_OSC_FREQUENCY 40750000 /* 0x026DCBB0 */ +#define QHD_H_SYNC ( 96 - 1) +#define QHD_H_FRONT_PORCH ( 32 - 1) +#define QHD_H_BACK_PORCH (128 - 1) +#define QHD_V_SYNC ( 5 - 1) +#define QHD_V_FRONT_PORCH ( 3 - 1) +#define QHD_V_BACK_PORCH ( 14 - 1) + +// WSVGA Mode: 1024 x 600 +#define WSVGA_H_RES_PIXELS 1024 +#define WSVGA_V_RES_PIXELS 600 +#define WSVGA_OSC_FREQUENCY 49000000 /* 0x02EBAE40 */ +#define WSVGA_H_SYNC (104 - 1) +#define WSVGA_H_FRONT_PORCH ( 40 - 1) +#define WSVGA_H_BACK_PORCH (144 - 1) +#define WSVGA_V_SYNC ( 10 - 1) +#define WSVGA_V_FRONT_PORCH ( 3 - 1) +#define WSVGA_V_BACK_PORCH ( 11 - 1) + +// HD720 Mode: 1280 x 720 +#define HD720_H_RES_PIXELS 1280 +#define HD720_V_RES_PIXELS 720 +#define HD720_OSC_FREQUENCY 74500000 /* 0x0470C7A0 */ +#define HD720_H_SYNC (128 - 1) +#define HD720_H_FRONT_PORCH ( 64 - 1) +#define HD720_H_BACK_PORCH (192 - 1) +#define HD720_V_SYNC ( 5 - 1) +#define HD720_V_FRONT_PORCH ( 3 - 1) +#define HD720_V_BACK_PORCH ( 20 - 1) + +// WXGA Mode: 1280 x 800 +#define WXGA_H_RES_PIXELS 1280 +#define WXGA_V_RES_PIXELS 800 +#define WXGA_OSC_FREQUENCY 83500000 /* 0x04FA1BE0 */ +#define WXGA_H_SYNC (128 - 1) +#define WXGA_H_FRONT_PORCH ( 72 - 1) +#define WXGA_H_BACK_PORCH (200 - 1) +#define WXGA_V_SYNC ( 6 - 1) +#define WXGA_V_FRONT_PORCH ( 3 - 1) +#define WXGA_V_BACK_PORCH ( 22 - 1) + // Colour Masks #define LCD_24BPP_RED_MASK 0x00FF0000 #define LCD_24BPP_GREEN_MASK 0x0000FF00 --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506457000849252.87174585742423; Tue, 26 Sep 2017 13:16:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3BEFE21EC8D1F; Tue, 26 Sep 2017 13:12:42 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5AC512007D1EB for ; Tue, 26 Sep 2017 13:12:28 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5h017392; Tue, 26 Sep 2017 21:15:38 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:28 +0100 Message-Id: <20170926201529.11644-19-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 18/19] ArmPlatformPkg: Reserving framebuffer at build X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak Currently frame buffer memory is either reserved in special VRAM or dynamically allocated using boot services memory allocation functions. When allocated using boot services calls the memory has to be allocated as EfiBootServicesData. Unfortunately failures have been seen with this case. There is also an unfortunate lack of control on the placement of the frmae buffer. This change introduces two PCDs, PcdArmLcdFrameBufferBase and PcdArmLcdFrameBufferSize which enable build time reservation of the frame buffer, avoiding the need to allocate dynamically. This allows the frame buffer to appear as "I/O memory" outside of the normal RAM map, which is similar to the "VRAM" case. This change has no impact on current code, only enables the option of build time reservation of frame buffers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Reviewed-by: Leif Lindholm --- ArmPlatformPkg/ArmPlatformPkg.dec = | 4 ++++ ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.in= f | 4 +++- ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c = | 21 ++++++++++++++++++-- 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatform= Pkg.dec index 77eb789ad8fe4ddcbf25abefad2e7b7d3d5e1722..0174f63e77f5b8430e106289366= feb9a6577fb99 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -111,6 +111,10 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027 =20 + ## If set, frame buffer memory will be reserved and mapped in the system= RAM + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x0|UINT32|0x0000= 0033 + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x0000= 0034 + ## PL180 MCI gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x= 00000028 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00= 000029 diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVE= xpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Ar= mVExpressLib.inf index 9b16f7f0c4731ab72bfb1008a073e81842bae82b..60789e9b8ff1b936db04953a765= fb164b0e85a40 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressL= ib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressL= ib.inf @@ -1,5 +1,5 @@ #/* @file -# Copyright (c) 2011-2014, ARM Limited. All rights reserved. +# Copyright (c) 2011-2017, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -57,6 +57,8 @@ [FixedPcd] gArmTokenSpaceGuid.PcdArmPrimaryCore =20 gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize =20 [Ppis] gArmMpCoreInfoPpiGuid diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMM= em.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c index 6379e81751fca5e7972c5c30f305be65fd1ae71d..5cd529750a3d2d3b0d381b58d87= 5d378afaba2c2 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011-2016, ARM Limited. All rights reserved. +* Copyright (c) 2011-2017, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the B= SD License @@ -20,8 +20,10 @@ #include #include =20 +#define FRAME_BUFFER_DESCRIPTOR ((FixedPcdGet64 (PcdArmLcdDdrFrameBufferBa= se) !=3D 0) ? 1 : 0) + // Number of Virtual Memory Map Descriptors -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (9 + FRAME_BUFFER_DESCRIPTOR) =20 // DDR attributes #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK @@ -142,6 +144,21 @@ ArmPlatformGetVirtualMemoryMap ( // VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_UNC= ACHED_UNBUFFERED; =20 + // Map region for the frame buffer in the system RAM +#if (FixedPcdGet32 (PcdArmLcdDdrFrameBufferSize) !=3D 0) + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdArmLcdDdr= FrameBufferBase); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdArmLcdDdrFra= meBufferBase); + VirtualMemoryTable[Index].Length =3D FixedPcdGet32 (PcdArmLcdDdrFrameBuf= ferSize); + /* Map as Normal Non-Cacheable memory, so that we can use the accelerated + * SetMem/CopyMem routines that may use unaligned accesses or + * DC ZVA instructions. If mapped as device memory, these routine may ca= use + * alignment faults. + * NOTE: The attribute value is misleading, it indicates memory map type= as + * an un-cached, un-buffered but allows buffering and reordering. + */ + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_UNC= ACHED_UNBUFFERED; +#endif + // Map sparse memory region if present if (HasSparseMemory) { VirtualMemoryTable[++Index].PhysicalBase =3D SparseMemoryBase; --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu Dec 26 01:04:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506457015135109.56045472546543; Tue, 26 Sep 2017 13:16:55 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id AD54020945BDC; Tue, 26 Sep 2017 13:12:42 -0700 (PDT) Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BB95521E43B4C for ; Tue, 26 Sep 2017 13:12:28 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.27.40]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v8QKFY5i017392; Tue, 26 Sep 2017 21:15:39 +0100 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.96.140; helo=cam-smtp0.cambridge.arm.com; envelope-from=evan.lloyd@arm.com; receiver=edk2-devel@lists.01.org From: evan.lloyd@arm.com To: edk2-devel@lists.01.org Date: Tue, 26 Sep 2017 21:15:29 +0100 Message-Id: <20170926201529.11644-20-evan.lloyd@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170926201529.11644-1-evan.lloyd@arm.com> References: <20170926201529.11644-1-evan.lloyd@arm.com> Subject: [edk2] [PATCH 19/19] ArmPlatformPkg: New DP500/DP550/DP650 GOP driver. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ard.biesheuvel@linaro.org"@arm.com, "leif.lindholm@linaro.org"@arm.com, "nd@arm.com"@arm.com, "Matteo.Carlini@arm.com"@arm.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Girish Pathak This change adds support for the ARM Mali DP500/DP500/DP650 display processors using the GOP protocol. It has been tested on FVP base models + DP550 support. This change does not modify functionality provided by PL111 or HDLCD. The driver should be suitable for those platforms that implement ARM Mali DP500/DP550/DP650 replacing PL111/HDLCD. Only "Layer Graphics" of the ARM Mali DP is configured for rendering the RGB/BGR format frame buffer to satisfy the UEFI GOP requirements Other layers e.g. video layers are not configured. NOTE: This change implements the Mali DP on models. Versions for actual hardware are liable to require extra handling for clock input changes, etc. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd --- ArmPlatformPkg/ArmPlatformPkg.dec = | 4 + ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec = | 4 +- ArmPlatformPkg/ArmVExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.inf = | 45 +++ ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.in= f | 3 + ArmPlatformPkg/Drivers/ArmMaliDp/ArmMaliDp.inf = | 44 +++ ArmPlatformPkg/Include/Drivers/ArmMaliDp.h = | 249 ++++++++++++ ArmPlatformPkg/ArmVExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.c = | 377 ++++++++++++++++++ ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c = | 10 +- ArmPlatformPkg/Drivers/ArmMaliDp/ArmMaliDp.c = | 412 ++++++++++++++++++++ 9 files changed, 1146 insertions(+), 2 deletions(-) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatform= Pkg.dec index 0174f63e77f5b8430e106289366feb9a6577fb99..3be236413cb8e12ce32e6349732= d2767fe0f3024 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -111,6 +111,10 @@ [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027 =20 + ## ARM Mali Display Processor DP500/DP550/DP650 + gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase|0x0|UINT64|0x00000050 + gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength|0x0|UINT32|0x0= 0000051 + ## If set, frame buffer memory will be reserved and mapped in the system= RAM gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x0|UINT32|0x0000= 0033 gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x0000= 0034 diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec b/ArmPlatform= Pkg/ArmVExpressPkg/ArmVExpressPkg.dec index 3814513c2241c03a8c45fda92d571c65368f64b4..1a55b0434ab4bc53d631be2bffd= 313684bcea9c4 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec @@ -1,7 +1,7 @@ #/** @file # Arm Versatile Express package. # -# Copyright (c) 2012-2015, ARM Limited. All rights reserved. +# Copyright (c) 2012-2017, ARM Limited. All rights reserved. # # This program and the accompanying materials are licensed and made avail= able # under the terms and conditions of the BSD License which accompanies this @@ -47,6 +47,8 @@ [PcdsFixedAtBuild.common] gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000002 gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|0|UINT32|0x00000003 =20 + gArmVExpressTokenSpaceGuid.PcdArmMaliDpMaxMode|0x0|UINT32|0x00000005 + # # Device path of block device on which Fastboot will flash partitions # diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLi= b.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.inf new file mode 100644 index 0000000000000000000000000000000000000000..b85205a8ac6bfbd8befdd8634a7= df89e213175bc --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.inf @@ -0,0 +1,45 @@ +#/** @file ArmMaliDpLib.inf +# +# Component description file for ArmMaliDpLib module +# +# Copyright (c) 2017, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ArmMaliDpLib + FILE_GUID =3D 36C47FED-2F3F-49C7-89CE-31B13F0431D8 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdPlatformLib + +[Sources.common] + ArmMaliDpLib.c + +[Packages] + MdePkg/MdePkg.dec + ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + BaseLib + DxeServicesTableLib + +[FixedPcd.common] + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase + gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize + gArmPlatformTokenSpaceGuid.PcdGopPixelFormat + + # MaxMode must be one number higher than the actual max mode, + # i.e. for actual maximum mode 2, set the value to 3. + # See Section 11.9 of the UEFI Specification 2.6 Errata A (Jan 2017) + gArmVExpressTokenSpaceGuid.PcdArmMaliDpMaxMode + diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVE= xpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Ar= mVExpressLib.inf index 60789e9b8ff1b936db04953a765fb164b0e85a40..6ad7d94c8c76404c8a84345b5f9= 92884ab5aca36 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressL= ib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressL= ib.inf @@ -60,5 +60,8 @@ [FixedPcd] gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize =20 + gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase + gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength + [Ppis] gArmMpCoreInfoPpiGuid diff --git a/ArmPlatformPkg/Drivers/ArmMaliDp/ArmMaliDp.inf b/ArmPlatformPk= g/Drivers/ArmMaliDp/ArmMaliDp.inf new file mode 100644 index 0000000000000000000000000000000000000000..69155a123ef71ecf5361ab29e0a= e71454c7ec6cd --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmMaliDp/ArmMaliDp.inf @@ -0,0 +1,44 @@ +#/** @file ArmMaliDp.inf +# +# Component description file for ArmMaliDp module +# +# Copyright (c) 2017, ARM Ltd. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ArmMaliDp + FILE_GUID =3D E724AAF7-19E2-40A3-BAE1-D82A7C8B7A76 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdHwLib + +[Sources.common] + ArmMaliDp.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + UefiLib + BaseLib + DebugLib + IoLib + BaseMemoryLib + LcdPlatformLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase + diff --git a/ArmPlatformPkg/Include/Drivers/ArmMaliDp.h b/ArmPlatformPkg/In= clude/Drivers/ArmMaliDp.h new file mode 100644 index 0000000000000000000000000000000000000000..4955176800ea59f352399d9c6b5= 90195d4ccfa41 --- /dev/null +++ b/ArmPlatformPkg/Include/Drivers/ArmMaliDp.h @@ -0,0 +1,249 @@ +/** @file ArmMaliDp.h + + File defines registers and other flags of ARM Mali DP display controller + + Copyright (c) 2017, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ +#ifndef ARMMALIDP_H_ +#define ARMMALIDP_H_ + +/********************************************************************** + * + * This header file contains all the bits of the ARM Mali DP that are + * platform independent. + * + **********************************************************************/ +#define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBas= e)) + +// MALI DP Ids +#define MALIDP_500 0x500 +#define MALIDP_550 0x550 +#define MALIDP_650 0x650 + +// DP500 Peripheral Ids +#define DP500_ID_PART_0 0x00 +#define DP500_ID_DES_0 0xB +#define DP500_ID_PART_1 0x5 + +#define DP500_ID_REVISION 0x1 +#define DP500_ID_JEDEC 0x1 +#define DP500_ID_DES_1 0x3 + +#define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0) +#define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \ + | DP500_ID_PART_1) +#define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \ + | (DP500_ID_JEDEC << 3) \ + | (DP500_ID_DES_1)) + +// DP550 Peripheral Ids +#define DP550_ID_PART_0 0x50 +#define DP550_ID_DES_0 0xB +#define DP550_ID_PART_1 0x5 + +#define DP550_ID_REVISION 0x0 +#define DP550_ID_JEDEC 0x1 +#define DP550_ID_DES_1 0x3 + +#define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0) +#define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \ + | DP550_ID_PART_1) +#define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \ + | (DP550_ID_JEDEC << 3) \ + | (DP550_ID_DES_1)) + +// DP650 Peripheral Ids +#define DP650_ID_PART_0 0x50 +#define DP650_ID_DES_0 0xB +#define DP650_ID_PART_1 0x6 + +#define DP650_ID_REVISION 0x0 +#define DP650_ID_JEDEC 0x1 +#define DP650_ID_DES_1 0x3 + +#define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0) +#define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \ + | DP650_ID_PART_1) +#define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \ + | (DP650_ID_JEDEC << 3) \ + | (DP650_ID_DES_1)) + +// Display Engine (DE) control register offsets for DP550/DP650 +#define DP_DE_STATUS 0x00000 +#define DP_DE_IRQ_SET 0x00004 +#define DP_DE_IRQ_MASK 0x00008 +#define DP_DE_IRQ_CLEAR 0x0000C +#define DP_DE_CONTROL 0x00010 +#define DP_DE_PROG_LINE 0x00014 +#define DP_DE_AXI_CONTROL 0x00018 +#define DP_DE_AXI_QOS 0x0001C +#define DP_DE_DISPLAY_FUNCTION 0x00020 + +#define DP_DE_H_INTERVALS 0x00030 +#define DP_DE_V_INTERVALS 0x00034 +#define DP_DE_SYNC_CONTROL 0x00038 +#define DP_DE_HV_ACTIVESIZE 0x0003C +#define DP_DE_DISPLAY_SIDEBAND 0x00040 +#define DP_DE_BACKGROUND_COLOR 0x00044 +#define DP_DE_DISPLAY_SPLIT 0x00048 +#define DP_DE_OUTPUT_DEPTH 0x0004C + +// Display Engine (DE) control register offsets for DP500 +#define DP_DE_DP500_CORE_ID 0x00018 +#define DP_DE_DP500_CONTROL 0x0000C +#define DP_DE_DP500_PROG_LINE 0x00010 +#define DP_DE_DP500_H_INTERVALS 0x00028 +#define DP_DE_DP500_V_INTERVALS 0x0002C +#define DP_DE_DP500_SYNC_CONTROL 0x00030 +#define DP_DE_DP500_HV_ACTIVESIZE 0x00034 +#define DP_DE_DP500_BG_COLOR_RG 0x0003C +#define DP_DE_DP500_BG_COLOR_B 0x00040 + +/* Display Engine (DE) graphics layer (LG) register offsets + * NOTE: For DP500 it will be LG2. + */ +#define DE_LG_OFFSET 0x00300 +#define DP_DE_LG_FORMAT (DE_LG_OFFSET) +#define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04) +#define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08) +#define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C) +#define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10) +#define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14) +#define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18) +#define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C) +#define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20) +#define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C) +#define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30) +#define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48) + +// Display core (DC) control register offsets. +#define DP_DC_OFFSET 0x0C000 +#define DP_DC_STATUS (DP_DC_OFFSET + 0x00) +#define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04) +#define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08) +#define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C) +#define DP_DC_CONTROL (DP_DC_OFFSET + 0x10) +#define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14) +#define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18) + +// DP500 has a global configuration register. +#define DP_DP500_CONFIG_VALID (0xF00) + +// Display core ID register offsets. +#define DP_DC_ID_OFFSET 0x0FF00 +#define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0) +#define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4) +#define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0) +#define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4) +#define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8) +#define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0) +#define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4) +#define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8) +#define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC) + +#define DP_DP500_ID_OFFSET 0x0F00 +#define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0) +#define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4) +#define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0) +#define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4) +#define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8) +#define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0) +#define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4) +#define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8) +#define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC) + +// Display status configuration mode activation flag +#define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16) + +// Display core control configuration mode +#define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18) +#define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17) +#define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16) + +#define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16) +#define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17) + +// Display core configuration valid register +#define DP_DC_CONFIG_VALID_CVAL (0x1U) + +/* DC_CORE_ID + * Display core version register PRODUCT_ID + */ +#define DP_DC_CORE_ID_SHIFT 16 +#define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT + +// Timing settings +#define DP_DE_HBACKPORCH_SHIFT 16 +#define DP_DE_VBACKPORCH_SHIFT 16 +#define DP_DE_VSP_SHIFT 28 +#define DP_DE_VSYNCWIDTH_SHIFT 16 +#define DP_DE_HSP_SHIFT 13 +#define DP_DE_V_ACTIVE_SHIFT 16 + +// BACKGROUND_COLOR +#define DP_DE_BG_R_PIXEL_SHIFT 16 +#define DP_DE_BG_G_PIXEL_SHIFT 8 + +//Graphics layer LG_FORMAT Pixel Format +#define DP_PIXEL_FORMAT_ARGB_8888 0x8 +#define DP_PIXEL_FORMAT_ABGR_8888 0x9 +#define DP_PIXEL_FORMAT_RGBA_8888 0xA +#define DP_PIXEL_FORMAT_BGRA_8888 0xB +#define DP_PIXEL_FORMAT_XRGB_8888 0x10 +#define DP_PIXEL_FORMAT_XBGR_8888 0x11 +#define DP_PIXEL_FORMAT_RGBX_8888 0x12 +#define DP_PIXEL_FORMAT_BGRX_8888 0x13 +#define DP_PIXEL_FORMAT_RGB_888 0x18 +#define DP_PIXEL_FORMAT_BGR_888 0x19 + +// DP500 format code are different than DP550/DP650 +#define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2 +#define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3 +#define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4 +#define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5 + +// Graphics layer LG_PTR_LOW and LG_PTR_HIGH +#define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU +#define DP_DE_LG_PTR_HIGH_SHIFT 32 + +// Graphics layer LG_CONTROL register characteristics +#define DP_DE_LG_L_ALPHA_SHIFT 16 +#define DP_DE_LG_CHK_SHIFT 15 +#define DP_DE_LG_PMUL_SHIFT 14 +#define DP_DE_LG_COM_SHIFT 12 +#define DP_DE_LG_VFP_SHIFT 11 +#define DP_DE_LG_HFP_SHIFT 10 +#define DP_DE_LG_ROTATION_SHIFT 8 + +#define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U +#define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U +#define DP_DE_LG_LAYER_BLEND_BG 0x2U +#define DP_DE_LG_PIXEL_BLEND_BG 0x3U +#define DP_DE_LG_ENABLE 0x1U + +// Graphics layer LG_IN_SIZE register characteristics +#define DP_DE_LG_V_IN_SIZE_SHIFT 16 + +// Graphics layer LG_CMP_SIZE register characteristics +#define DP_DE_LG_V_CMP_SIZE_SHIFT 16 +#define DP_DE_LG_V_OFFSET_SHIFT 16 + +// Helper display timing macro functions. +#define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hf= p) +#define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vf= p) +#define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hs= w) +#define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Ho= r) + +// Helper layer graphics macros. +#define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | = Hor) +#define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) |= Hor) + +#endif /* ARMMALIDP_H_ */ diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLi= b.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.c new file mode 100644 index 0000000000000000000000000000000000000000..81924cc41f5898605038a1bc20a= f096fbb85d81c --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmMaliDpLib/ArmMaliDpLib.c @@ -0,0 +1,377 @@ +/** @file ArmMaliDpLib.c +* +* The file contains ARM Mali DP platform specific implementation. +* +* Copyright (c) 2017, ARM Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +/** Check an address is within 40 bits. + * + * The ARM Mali DP frame buffer address size can not be wider than 40 bits +**/ +#define DP_VALID_BASE_ADDR(Address) ((Address >> 40) =3D=3D 0) + +typedef struct { + UINT32 Mode; + UINT32 OscFreq; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; +} DISPLAY_MODE; + +/** The display modes implemented by this driver. + * + * On Models, the OSC frequencies (listed for each mode below) are not us= ed. + * However these frequencies are useful on hardware plaforms where related + * clock (or PLL) settings are based on these pixel clocks. + * + * Since the clock settings are defined externally, the driver must + * communicate pixel clock frequencies to relevant modules + * responsible for setting clocks. e.g. SCP. +**/ +STATIC CONST DISPLAY_MODE mDisplayModes[] =3D { + { + // Mode 0 : VGA : 640 x 480 x 24 bpp. + VGA, + VGA_OSC_FREQUENCY, + {VGA_H_RES_PIXELS, VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH}, + {VGA_V_RES_PIXELS, VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH} + }, + { + // Mode 1 : WVGA : 800 x 480 x 24 bpp. + WVGA, + WVGA_OSC_FREQUENCY, + {WVGA_H_RES_PIXELS, WVGA_H_SYNC, WVGA_H_BACK_PORCH, WVGA_H_FRONT_PORCH= }, + {WVGA_V_RES_PIXELS, WVGA_V_SYNC, WVGA_V_BACK_PORCH, WVGA_V_FRONT_PORCH} + }, + { + // Mode 2 : SVGA : 800 x 600 x 24 bpp. + SVGA, + SVGA_OSC_FREQUENCY, + {SVGA_H_RES_PIXELS, SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH= }, + {SVGA_V_RES_PIXELS, SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH} + }, + { + // Mode 3 : QHD : 960 x 540 x 24 bpp. + QHD, + QHD_OSC_FREQUENCY, + {QHD_H_RES_PIXELS, QHD_H_SYNC, QHD_H_BACK_PORCH, QHD_H_FRONT_PORCH}, + {QHD_V_RES_PIXELS, QHD_V_SYNC, QHD_V_BACK_PORCH, QHD_V_FRONT_PORCH} + }, + { + // Mode 4 : WSVGA : 1024 x 600 x 24 bpp. + WSVGA, + WSVGA_OSC_FREQUENCY, + {WSVGA_H_RES_PIXELS, WSVGA_H_SYNC, WSVGA_H_BACK_PORCH, WSVGA_H_FRONT_P= ORCH}, + {WSVGA_V_RES_PIXELS, WSVGA_V_SYNC, WSVGA_V_BACK_PORCH, WSVGA_V_FRONT_P= ORCH} + }, + { + // Mode 5 : XGA : 1024 x 768 x 24 bpp. + XGA, + XGA_OSC_FREQUENCY, + {XGA_H_RES_PIXELS, XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH}, + {XGA_V_RES_PIXELS, XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH} + }, + { + // Mode 6 : HD : 1280 x 720 x 24 bpp. + HD720, + HD720_OSC_FREQUENCY, + {HD720_H_RES_PIXELS, HD720_H_SYNC, HD720_H_BACK_PORCH, HD720_H_FRONT_P= ORCH}, + {HD720_V_RES_PIXELS, HD720_V_SYNC, HD720_V_BACK_PORCH, HD720_V_FRONT_P= ORCH} + }, + { + // Mode 7 : WXGA : 1280 x 800 x 24 bpp. + WXGA, + WXGA_OSC_FREQUENCY, + {WXGA_H_RES_PIXELS, WXGA_H_SYNC, WXGA_H_BACK_PORCH, WXGA_H_FRONT_PORCH= }, + {WXGA_V_RES_PIXELS, WXGA_V_SYNC, WXGA_V_BACK_PORCH, WXGA_V_FRONT_PORCH} + }, + { // Mode 8 : SXGA : 1280 x 1024 x 24 bpp. + SXGA, + SXGA_OSC_FREQUENCY, + {SXGA_H_RES_PIXELS, SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH= }, + {SXGA_V_RES_PIXELS, SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH} + }, + { // Mode 9 : WSXGA+ : 1680 x 1050 x 24 bpp. + WSXGA, + WSXGA_OSC_FREQUENCY, + {WSXGA_H_RES_PIXELS, WSXGA_H_SYNC, WSXGA_H_BACK_PORCH, WSXGA_H_FRONT_P= ORCH}, + {WSXGA_V_RES_PIXELS,WSXGA_V_SYNC, WSXGA_V_BACK_PORCH, WSXGA_V_FRONT_PO= RCH} + }, + { + // Mode 10 : HD : 1920 x 1080 x 24 bpp. + HD, + HD_OSC_FREQUENCY, + {HD_H_RES_PIXELS, HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH}, + {HD_V_RES_PIXELS, HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH} + } +}; + +/** If PcdArmMaliDpMaxMode is 0, platform supports full range of modes + * else platform supports modes from 0 to PcdArmMaliDpMaxMode - 1 +**/ +STATIC CONST UINT32 mMaxMode =3D ((FixedPcdGet32 (PcdArmMaliDpMaxMode) != =3D 0) + ? FixedPcdGet32 (PcdArmMaliDpMaxMode) + : sizeof (mDisplayModes) / sizeof (DISP= LAY_MODE)); + + +/** Platform related initialization function. + * + * @retval EFI_SUCCESS Platform initialization success. + * @retval EFI_UNSUPPORTED PcdGopPixelFormat must be + * PixelRedGreenBlueReserved8BitPerColor OR + * PixelBlueGreenRedReserved8BitPerColor + * any other format is not supported. +**/ +EFI_STATUS +LcdPlatformInitializeDisplay ( + IN CONST EFI_HANDLE Handle + ) +{ + EFI_GRAPHICS_PIXEL_FORMAT PixelFormat; + + (VOID)Handle; + + // PixelBitMask and PixelBltOnly pixel formats are not supported + PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + if (PixelFormat !=3D PixelRedGreenBlueReserved8BitPerColor + && PixelFormat !=3D PixelBlueGreenRedReserved8BitPerColor) { + + ASSERT (PixelFormat =3D=3D PixelRedGreenBlueReserved8BitPerColor + || PixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor); + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** Reserve VRAM memory in DRAM for the frame buffer + * + * (unless it is reserved already). + * + * The allocated address can be used to set the frame buffer as a base bu= ffer + * address for any layer of the ARM Mali DP. + * + * @param OUT VramBaseAddress A pointer to the frame buffer address. + * @param OUT VramSize A pointer to the size of the frame + * buffer in bytes + * + * @retval EFI_SUCCESS Frame buffer memory allocation success. + * @retval EFI_INVALID_PARAMETER VramBaseAddress or VramSize are NULL. + * @retval EFI_UNSUPPORTED Allocated address wider than 40 bits + * @retval !EFI_SUCCESS Other errors. +**/ +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS * CONST VramBaseAddress, + OUT UINTN * CONST VramSize + ) +{ + EFI_STATUS Status; + + // Check VramBaseAddress and VramSize are not NULL. + if (VramBaseAddress =3D=3D NULL || VramSize =3D=3D NULL) { + ASSERT (VramBaseAddress !=3D NULL); + ASSERT (VramSize !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + // Set the VRAM size. + *VramSize =3D (UINTN)FixedPcdGet32 (PcdArmLcdDdrFrameBufferSize); + + // Check if memory is already reserved for the frame buffer. +#if (FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase) !=3D 0) + +#if (!DP_VALID_BASE_ADDR (FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase))) +#error ARM Mali DP frame buffer base address cannot be wider than 40 bits. +#else + + *VramBaseAddress =3D + (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdArmLcdDdrFrameBufferBase); + + Status =3D EFI_SUCCESS; +#endif + +#else + // If not already reserved, attempt to allocate the VRAM from the DRAM. + Status =3D gBS->AllocatePages ( + AllocateAnyPages, + EfiBootServicesData, + EFI_SIZE_TO_PAGES (*VramSize), + VramBaseAddress + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ArmMaliDpLib: Failed to allocate frame buffer.\n= ")); + ASSERT_EFI_ERROR (Status); + return Status; + } + + // ARM Mali DP frame buffer base address can not be wider than 40 bits. + if (!DP_VALID_BASE_ADDR (*VramBaseAddress)) { + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); + ASSERT (DP_VALID_BASE_ADDR (*VramBaseAddress)); + return EFI_UNSUPPORTED; + } + + /* Mark the VRAM as write-combining. The VRAM is inside the DRAM, which = is cacheable. + * For ARM/AArch64 EFI_MEMORY_WC memory is actually uncached. + */ + Status =3D gDS->SetMemorySpaceAttributes ( + *VramBaseAddress, + *VramSize, + EFI_MEMORY_WC + ); + + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); + } + +#endif + return Status; +} + +/** Return total number of modes supported. + * + * Note: Valid mode numbers are 0 to MaxMode - 1 + * See Section 12.9 of the UEFI Specification 2.7 + * + * @retval UINT32 Mode Number. +**/ +UINT32 +LcdPlatformGetMaxMode (VOID) +{ + return mMaxMode; +} + +/** Set the requested display mode. + * + * @param IN ModeNumber Mode Number. + * + * @retval EFI_SUCCESS Set mode success. + * @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformSetMode ( + IN CONST UINT32 ModeNumber + ) +{ + + if (ModeNumber >=3D mMaxMode) { + ASSERT (ModeNumber < mMaxMode); + return EFI_INVALID_PARAMETER; + } + /* On models, platform specific clock/mux settings are not required + * Display controller specific settings for Mali DP are done in LcdSetMo= de. + */ + return EFI_SUCCESS; +} + +/** Return information for the requested mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT Info Pointer for returned mode information + * (on success). + * + * @retval EFI_SUCCESS Requested mode found. + * @retval EFI_INVALID_PARAMETER Info is NULL. + * @retval EFI_INVALID_PARAMETER Requested mode not found. +**/ +EFI_STATUS +LcdPlatformQueryMode ( + IN CONST UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION * CONST Info + ) +{ + if (ModeNumber >=3D mMaxMode || Info =3D=3D NULL) { + ASSERT (ModeNumber < mMaxMode); + ASSERT (Info !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + Info->Version =3D 0; + Info->HorizontalResolution =3D mDisplayModes[ModeNumber].Horizontal.Reso= lution; + Info->VerticalResolution =3D mDisplayModes[ModeNumber].Vertical.Resoluti= on; + Info->PixelsPerScanLine =3D mDisplayModes[ModeNumber].Horizontal.Resolut= ion; + + Info->PixelFormat =3D FixedPcdGet32 (PcdGopPixelFormat); + + return EFI_SUCCESS; +} + +/** Returns the display timing information for the requested mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT Horizontal Pointer to horizontal timing parameter= s. + * (Resolution, Sync, Back porch, Front p= orch) + * @param OUT Vertical Pointer to vertical timing parameters. + * (Resolution, Sync, Back porch, Front p= orch) + * + * @retval EFI_SUCCESS Requested mode found. + * @retval EFI_INVALID_PARAMETER Requested mode not found. + * @retval EFI_INVALID_PARAMETER One of the OUT parameters is NULL. +**/ +EFI_STATUS +LcdPlatformGetTimings ( + IN UINT32 ModeNumber, + OUT CONST SCAN_TIMINGS ** Horizontal, + OUT CONST SCAN_TIMINGS ** Vertical + ) +{ + if (ModeNumber >=3D mMaxMode || Horizontal =3D=3D NULL || Vertical =3D= =3D NULL) { + ASSERT (ModeNumber < mMaxMode); + // One of the pointers is NULL + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + *Horizontal =3D &mDisplayModes[ModeNumber].Horizontal; + *Vertical =3D &mDisplayModes[ModeNumber].Vertical; + + return EFI_SUCCESS; +} + +/** Return bytes per pixel information for a mode number. + * + * @param IN ModeNumber Mode Number. + * @param OUT Bpp Pointer to value Bytes Per Pixel. + * + * @retval EFI_SUCCESS The requested mode is found. + * @retval EFI_INVALID_PARAMETER Requested mode not found. + * @retval EFI_INVALID_PARAMETER Bpp is NULL. +**/ +EFI_STATUS +LcdPlatformGetBpp ( + IN CONST UINT32 ModeNumber, + OUT LCD_BPP * CONST Bpp + ) +{ + if (ModeNumber >=3D mMaxMode || Bpp =3D=3D NULL) { + // Check valid ModeNumber and Bpp. + ASSERT (ModeNumber < mMaxMode); + ASSERT (Bpp !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + *Bpp =3D LCD_BITS_PER_PIXEL_24; + + return EFI_SUCCESS; +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMM= em.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c index 5cd529750a3d2d3b0d381b58d875d378afaba2c2..87a7a26132e39b933ecd2a95e38= b2ab869cd4079 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -21,9 +21,10 @@ #include =20 #define FRAME_BUFFER_DESCRIPTOR ((FixedPcdGet64 (PcdArmLcdDdrFrameBufferBa= se) !=3D 0) ? 1 : 0) +#define DP_BASE_DESCRIPTOR ((FixedPcdGet64 (PcdArmMaliDpBase) !=3D 0)= ? 1 : 0) =20 // Number of Virtual Memory Map Descriptors -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (9 + FRAME_BUFFER_DESCRIPTOR) +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (9 + FRAME_BUFFER_DESCRIPTOR + = DP_BASE_DESCRIPTOR) =20 // DDR attributes #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK @@ -159,6 +160,13 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_UNC= ACHED_UNBUFFERED; #endif =20 +#if (FixedPcdGet64 (PcdArmMaliDpBase) !=3D 0) + // DP500/DP550/DP650 peripheral memory region + VirtualMemoryTable[++Index].PhysicalBase =3D FixedPcdGet64 (PcdArmMaliDp= Base); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdArmMaliDpBas= e); + VirtualMemoryTable[Index].Length =3D FixedPcdGet32 (PcdArmMaliDpMemoryRe= gionLength); + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_DEV= ICE; +#endif // Map sparse memory region if present if (HasSparseMemory) { VirtualMemoryTable[++Index].PhysicalBase =3D SparseMemoryBase; diff --git a/ArmPlatformPkg/Drivers/ArmMaliDp/ArmMaliDp.c b/ArmPlatformPkg/= Drivers/ArmMaliDp/ArmMaliDp.c new file mode 100644 index 0000000000000000000000000000000000000000..ff7236371d27915d9f1e34162dc= e0954dde63a77 --- /dev/null +++ b/ArmPlatformPkg/Drivers/ArmMaliDp/ArmMaliDp.c @@ -0,0 +1,412 @@ +/** @file ArmMaliDp.c + + ARM Mali DP 500/550/650 display controller driver + + Copyright (c) 2017, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include + +// CORE_ID of the MALI DP +STATIC UINT32 gDpDeviceId; + +/** Disable the graphics layer + * + * This is done by clearing the EN bit + * of the LG_CONTROL register. +**/ +STATIC +VOID +LayerGraphicsDisable (VOID) +{ + MmioAnd32 (DP_BASE + DP_DE_LG_CONTROL, ~DP_DE_LG_ENABLE); +} + +/** Enable the graphics layer + * + * This is done by setting the EN bit + * of the LG_CONTROL register. +**/ +STATIC +VOID +LayerGraphicsEnable (VOID) +{ + MmioOr32 (DP_BASE + DP_DE_LG_CONTROL, DP_DE_LG_ENABLE); +} + +/** Set the frame address of the graphics layer. + * + * @param FrameBaseAddress Address of the data buffer + * to be used as a frame buffer. +**/ +STATIC +VOID +LayerGraphicsSetFrame ( + IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress + ) +{ + // Disable the graphics layer. + LayerGraphicsDisable (); + + /* Set up memory address of the data buffer for graphics layer. + * write lower bits of the address. + */ + MmioWrite32 ( + DP_BASE + DP_DE_LG_PTR_LOW, + DP_DE_LG_PTR_LOW_MASK & FrameBaseAddress + ); + + // Write higher bits of the address. + MmioWrite32 ( + DP_BASE + DP_DE_LG_PTR_HIGH, + (UINT32)(FrameBaseAddress >> DP_DE_LG_PTR_HIGH_SHIFT) + ); + + // Enable the graphics layer. + LayerGraphicsEnable (); +} + +/** Configures various graphics layer characteristics. + * + * @param HRes Horizontal resolution of the graphics lay= er. + * @param VRes Vertical resolution of the graphics layer. +**/ +STATIC +VOID +LayerGraphicsConfig ( + IN CONST EFI_GRAPHICS_PIXEL_FORMAT UefiGfxPixelFormat, + IN CONST UINT32 HRes, + IN CONST UINT32 VRes + ) +{ + UINT32 PixelFormat; + + // Disable the graphics layer before configuring any settings. + LayerGraphicsDisable (); + + // Setup graphics layer size. + MmioWrite32 (DP_BASE + DP_DE_LG_IN_SIZE, FRAME_IN_SIZE (HRes, VRes)); + + // Setup graphics layer composition size. + MmioWrite32 (DP_BASE + DP_DE_LG_CMP_SIZE, FRAME_CMP_SIZE (HRes, VRes)); + + // Setup memory stride (total visible pixels on a line * 4 ). + MmioWrite32 (DP_BASE + DP_DE_LG_H_STRIDE, (HRes * sizeof (UINT32))); + + /* Set the format. + * + * In PixelBlueGreenRedReserved8BitPerColor format, byte 0 represents bl= ue, + * byte 1 represents green, and byte 2 represents red, and byte 3 is res= erved + * which is equivalent to XRGB format of the DP500/DP550/DP650. Whereas + * PixelRedGreenBlueReserved8BitPerColor is equivalent to XBGR of the + * DP500/DP550/DP650. + */ + if (UefiGfxPixelFormat =3D=3D PixelBlueGreenRedReserved8BitPerColor) { + PixelFormat =3D (gDpDeviceId =3D=3D MALIDP_500) ? DP_PIXEL_FORMAT_DP50= 0_XRGB_8888 + : DP_PIXEL_FORMAT_XRGB_8888; + } else { + PixelFormat =3D (gDpDeviceId =3D=3D MALIDP_500) ? DP_PIXEL_FORMAT_DP50= 0_XBGR_8888 + : DP_PIXEL_FORMAT_XBGR_8888; + } + + MmioWrite32 (DP_BASE + DP_DE_LG_FORMAT, PixelFormat); + + // Enable graphics layer. + LayerGraphicsEnable (); +} + +/** Configure timing information of the display. + * @param IN Horizontal Pointer to horizontal timing parameters. + * (Resolution, Sync, Back porch, Front po= rch) + * @param IN Vertical Pointer to vertical timing parameters. + * (Resolution, Sync, Back porch, Front po= rch) +**/ +STATIC +VOID +SetDisplayEngineTiming ( + IN CONST SCAN_TIMINGS * CONST Horizontal, + IN CONST SCAN_TIMINGS * CONST Vertical + ) +{ + UINTN RegHIntervals; + UINTN RegVIntervals; + UINTN RegSyncControl; + UINTN RegHVActiveSize; + + if (gDpDeviceId =3D=3D MALIDP_500) { + // MALI DP500 timing registers. + RegHIntervals =3D DP_BASE + DP_DE_DP500_H_INTERVALS; + RegVIntervals =3D DP_BASE + DP_DE_DP500_V_INTERVALS; + RegSyncControl =3D DP_BASE + DP_DE_DP500_SYNC_CONTROL; + RegHVActiveSize =3D DP_BASE + DP_DE_DP500_HV_ACTIVESIZE; + } else { + // MALI DP550/DP650 timing registers. + RegHIntervals =3D DP_BASE + DP_DE_H_INTERVALS; + RegVIntervals =3D DP_BASE + DP_DE_V_INTERVALS; + RegSyncControl =3D DP_BASE + DP_DE_SYNC_CONTROL; + RegHVActiveSize =3D DP_BASE + DP_DE_HV_ACTIVESIZE; + } + + // Horizontal back porch and front porch. + MmioWrite32 ( + RegHIntervals, + H_INTERVALS (Horizontal->FrontPorch, Horizontal->BackPorch) + ); + + // Vertical back porch and front porch. + MmioWrite32 ( + RegVIntervals, + V_INTERVALS (Vertical->FrontPorch, Vertical->BackPorch) + ); + + // Sync control, Horizontal and Vertical sync. + MmioWrite32 ( + RegSyncControl, + SYNC_WIDTH (Horizontal->Sync, Vertical->Sync) + ); + + // Set up Horizontal and Vertical area size. + MmioWrite32 ( + RegHVActiveSize, + HV_ACTIVE (Horizontal->Resolution, Vertical->Resolution) + ); +} + +/** Return CORE_ID of the ARM Mali DP. + * + * @retval 0 No Mali DP found. + * @retval 0x500 Mali DP core id for DP500. + * @retval 0x550 Mali DP core id for DP550. + * @retval 0x650 Mali DP core id for DP650. +**/ +STATIC +UINT32 +ArmMaliDpGetCoreId ( + ) +{ + UINT32 DpCoreId; + + /* First check for DP500 as register offset for DP550/DP650 CORE_ID + * is beyond 3K/4K register space of the DP500. + */ + DpCoreId =3D MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID); + DpCoreId >>=3D DP_DE_DP500_CORE_ID_SHIFT; + + if (DpCoreId =3D=3D MALIDP_500) { + return DpCoreId; + } + + // Check for DP550 or DP650. + DpCoreId =3D MmioRead32 (DP_BASE + DP_DC_CORE_ID); + DpCoreId >>=3D DP_DC_CORE_ID_SHIFT; + + if (DpCoreId =3D=3D MALIDP_550 + || DpCoreId =3D=3D MALIDP_650) { + return DpCoreId; + } + + return 0; +} + +/** Check for presence of MALI. + * + * This function returns success if the platform implements + * DP500/DP550/DP650 ARM Mali display processor. + * + * @retval EFI_SUCCESS Platform implements DP500/DP550/DP650. + * @retval EFI_NOT_FOUND DP500/DP550/DP650 display processor not + * found on the platform. +**/ +EFI_STATUS +LcdIdentify (VOID) +{ + UINT32 DpCoreId; + + DEBUG ((DEBUG_WARN, + "Probing ARM Mali DP500/DP550/DP650 at base address 0x%p\n", + DP_BASE + )); + +#if (DP_BASE =3D=3D 0) +#error "ARM Mali DP peripheral base address is invalid\n" +#endif + + DpCoreId =3D ArmMaliDpGetCoreId (); + + if (DpCoreId !=3D 0) { + DEBUG ((DEBUG_WARN, "Found ARM Mali DP %x\n", DpCoreId)); + return EFI_SUCCESS; + } + + DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n")); + + return EFI_NOT_FOUND; +} + +/** Initialize platform display. + * + * @param FrameBaseAddress Address of the frame buffer. + * + * @retval EFI_SUCCESS Display initialization success. + * @retval !(EFI_SUCCESS) Display initialization failure. +**/ +EFI_STATUS +LcdInitialize ( + IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress + ) +{ + DEBUG ((DEBUG_WARN, "Frame buffer base address =3D %p\n", FrameBaseAddre= ss)); + + gDpDeviceId =3D ArmMaliDpGetCoreId (); + if (gDpDeviceId =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "ARM Mali DP initialization fail," + "no ARM Mali DP present\n")); + return EFI_NOT_FOUND; + } + + // We are using graphics layer of the Mali DP as a main frame buffer. + LayerGraphicsSetFrame (FrameBaseAddress); + + return EFI_SUCCESS; +} + +/** Set ARM Mali DP in cofiguration mode. + * + * The ARM Mali DP must be in the configuration mode for + * configuration of the H_INTERVALS, V_INTERVALS, SYNC_CONTROL + * and HV_ACTIVESIZE. +**/ +STATIC +VOID +SetConfigurationMode (VOID) +{ + // Request configuration Mode. + if (gDpDeviceId =3D=3D MALIDP_500) { + MmioOr32 (DP_BASE + DP_DE_DP500_CONTROL, DP_DE_DP500_CONTROL_CONFIG_REQ= ); + } else { + MmioOr32 (DP_BASE + DP_DC_CONTROL, DP_DC_CONTROL_CM_ACTIVE); + } +} + +/** Set ARM Mali DP in normal mode. + * + * Normal mode is the main operating mode of the display processor + * in which display layer data is fetched from frame buffer and + * displayed. +**/ +STATIC +VOID +SetNormalMode (VOID) +{ + // Disable configuration Mode. + if (gDpDeviceId =3D=3D MALIDP_500) { + MmioAnd32 (DP_BASE + DP_DE_DP500_CONTROL, ~DP_DE_DP500_CONTROL_CONFIG_R= EQ); + } else { + MmioAnd32 (DP_BASE + DP_DC_CONTROL, ~DP_DC_CONTROL_CM_ACTIVE ); + } +} + +/** Set the global configuration valid flag. + * + * Any new configuration parameters written to the display engine are not + * activated until the global configuration valid flag is set in the + * CONFIG_VALID register. +**/ +STATIC +VOID +SetConfigValid (VOID) +{ + if (gDpDeviceId =3D=3D MALIDP_500) { + MmioOr32 (DP_BASE + DP_DP500_CONFIG_VALID, DP_DC_CONFIG_VALID); + } else { + MmioOr32 (DP_BASE + DP_DC_CONFIG_VALID, DP_DC_CONFIG_VALID ); + } +} + +/** Set requested mode of the display. + * + * @param ModeNumber Display mode number. + * @retval EFI_SUCCESS Display set mode success. + * @retval EFI_DEVICE_ERROR If mode not found/supported. + * @retval EFI_DEVICE_ERROR If mode does not support more + * than 24 bytes per pixel format. +**/ +EFI_STATUS +LcdSetMode ( + IN CONST UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + CONST SCAN_TIMINGS *Horizontal; + CONST SCAN_TIMINGS *Vertical; + + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; + + // Get the display mode timings and other relevant information. + Status =3D LcdPlatformGetTimings ( + ModeNumber, + &Horizontal, + &Vertical + ); + + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + ASSERT (Horizontal !=3D NULL); + ASSERT (Vertical !=3D NULL); + + // Get the pixel format information. + Status =3D LcdPlatformQueryMode (ModeNumber, &ModeInfo); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // Request configuration mode. + SetConfigurationMode (); + + // Configure the graphics layer. + LayerGraphicsConfig ( + ModeInfo.PixelFormat, + Horizontal->Resolution, + Vertical->Resolution + ); + + // Set the display engine timings. + SetDisplayEngineTiming (Horizontal, Vertical); + + // After configuration, set Mali DP in normal mode. + SetNormalMode (); + + /* Any parameters written to the display engine are not activated until + * CONFIG_VALID is set. + */ + SetConfigValid (); + + return EFI_SUCCESS; +} + +/** + * This function de-initializes the display. +**/ +VOID +LcdShutdown (VOID) +{ + // Disable graphics layer. + LayerGraphicsDisable (); +} --=20 Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel