From nobody Wed Dec 25 13:00:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507798097952529.5576034910029; Thu, 12 Oct 2017 01:48:17 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9DA0B21F38825; Thu, 12 Oct 2017 01:44:45 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9C05921FC7498 for ; Thu, 12 Oct 2017 01:44:44 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP; 12 Oct 2017 01:48:14 -0700 Received: from ray-dev.ccr.corp.intel.com ([10.239.9.7]) by FMSMGA003.fm.intel.com with ESMTP; 12 Oct 2017 01:48:13 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,365,1503385200"; d="scan'208";a="909212119" From: Ruiyu Ni To: edk2-devel@lists.01.org Date: Thu, 12 Oct 2017 16:48:07 +0800 Message-Id: <20171012084810.148196-2-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.12.2.windows.2 In-Reply-To: <20171012084810.148196-1-ruiyu.ni@intel.com> References: <20171012084810.148196-1-ruiyu.ni@intel.com> Subject: [edk2] [PATCH 1/4] UefiCpuPkg/MtrrLib: refine MtrrLibProgramFixedMtrr() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael D Kinney , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The patch replaces some if-checks with assertions because they are impossible to happen. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Michael D Kinney Cc: Eric Dong --- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 66 +++++++++++++++++---------------= ---- 1 file changed, 31 insertions(+), 35 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/Mtrr= Lib/MtrrLib.c index cf1af29936..5b21fe11f1 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -466,10 +466,10 @@ MtrrGetVariableMtrr ( @param[in] Type The memory type to set. @param[in, out] Base The base address of memory range. @param[in, out] Length The length of memory range. - @param[in, out] LastMsrNum On input, the last index of the fixed M= TRR MSR to program. + @param[in, out] LastMsrIndex On input, the last index of the fixed M= TRR MSR to program. On return, the current index of the fix= ed MTRR MSR to program. - @param[out] ReturnClearMask The bits to clear in the fixed MTRR MSR. - @param[out] ReturnOrMask The bits to set in the fixed MTRR MSR. + @param[out] ClearMask The bits to clear in the fixed MTRR MSR. + @param[out] OrMask The bits to set in the fixed MTRR MSR. =20 @retval RETURN_SUCCESS The cache type was updated successfully @retval RETURN_UNSUPPORTED The requested range or cache type was invalid @@ -481,27 +481,25 @@ MtrrLibProgramFixedMtrr ( IN MTRR_MEMORY_CACHE_TYPE Type, IN OUT UINT64 *Base, IN OUT UINT64 *Length, - IN OUT UINT32 *LastMsrNum, - OUT UINT64 *ReturnClearMask, - OUT UINT64 *ReturnOrMask + IN OUT UINT32 *LastMsrIndex, + OUT UINT64 *ClearMask, + OUT UINT64 *OrMask ) { - UINT32 MsrNum; + UINT32 MsrIndex; UINT32 LeftByteShift; UINT32 RightByteShift; - UINT64 OrMask; - UINT64 ClearMask; UINT64 SubLength; =20 // // Find the fixed MTRR index to be programmed // - for (MsrNum =3D *LastMsrNum + 1; MsrNum < MTRR_NUMBER_OF_FIXED_MTRR; Msr= Num++) { - if ((*Base >=3D mMtrrLibFixedMtrrTable[MsrNum].BaseAddress) && + for (MsrIndex =3D *LastMsrIndex + 1; MsrIndex < ARRAY_SIZE (mMtrrLibFixe= dMtrrTable); MsrIndex++) { + if ((*Base >=3D mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) && (*Base < ( - mMtrrLibFixedMtrrTable[MsrNum].BaseAddress + - (8 * mMtrrLibFixedMtrrTable[MsrNum].Length) + mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress + + (8 * mMtrrLibFixedMtrrTable[MsrIndex].Length) ) ) ) { @@ -509,65 +507,63 @@ MtrrLibProgramFixedMtrr ( } } =20 - if (MsrNum =3D=3D MTRR_NUMBER_OF_FIXED_MTRR) { - return RETURN_UNSUPPORTED; - } + ASSERT (MsrIndex !=3D ARRAY_SIZE (mMtrrLibFixedMtrrTable)); =20 // // Find the begin offset in fixed MTRR and calculate byte offset of left= shift // - LeftByteShift =3D ((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrNum].BaseAd= dress) - / mMtrrLibFixedMtrrTable[MsrNum].Length; - - if (LeftByteShift >=3D 8) { + if ((((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) % mM= trrLibFixedMtrrTable[MsrIndex].Length) !=3D 0) { + // + // Base address should be aligned to the begin of a certain Fixed MTRR= range. + // return RETURN_UNSUPPORTED; } + LeftByteShift =3D ((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].Base= Address) / mMtrrLibFixedMtrrTable[MsrIndex].Length; + ASSERT (LeftByteShift < 8); =20 // // Find the end offset in fixed MTRR and calculate byte offset of right = shift // - SubLength =3D mMtrrLibFixedMtrrTable[MsrNum].Length * (8 - LeftByteShift= ); + SubLength =3D mMtrrLibFixedMtrrTable[MsrIndex].Length * (8 - LeftByteShi= ft); if (*Length >=3D SubLength) { RightByteShift =3D 0; } else { - RightByteShift =3D 8 - LeftByteShift - - (UINT32)(*Length) / mMtrrLibFixedMtrrTable[MsrNum].Length; - if ((LeftByteShift >=3D 8) || - (((UINT32)(*Length) % mMtrrLibFixedMtrrTable[MsrNum].Length) !=3D = 0) - ) { + if (((UINT32)(*Length) % mMtrrLibFixedMtrrTable[MsrIndex].Length) !=3D= 0) { + // + // Length should be aligned to the end of a certain Fixed MTRR range. + // return RETURN_UNSUPPORTED; } + RightByteShift =3D 8 - LeftByteShift - (UINT32)(*Length) / mMtrrLibFix= edMtrrTable[MsrIndex].Length; // // Update SubLength by actual length // SubLength =3D *Length; } =20 - ClearMask =3D CLEAR_SEED; - OrMask =3D MultU64x32 (OR_SEED, (UINT32) Type); + *ClearMask =3D CLEAR_SEED; + *OrMask =3D MultU64x32 (OR_SEED, (UINT32) Type); =20 if (LeftByteShift !=3D 0) { // // Clear the low bits by LeftByteShift // - ClearMask &=3D LShiftU64 (ClearMask, LeftByteShift * 8); - OrMask &=3D LShiftU64 (OrMask, LeftByteShift * 8); + *ClearMask &=3D LShiftU64 (*ClearMask, LeftByteShift * 8); + *OrMask &=3D LShiftU64 (*OrMask, LeftByteShift * 8); } =20 if (RightByteShift !=3D 0) { // // Clear the high bits by RightByteShift // - ClearMask &=3D RShiftU64 (ClearMask, RightByteShift * 8); - OrMask &=3D RShiftU64 (OrMask, RightByteShift * 8); + *ClearMask &=3D RShiftU64 (*ClearMask, RightByteShift * 8); + *OrMask &=3D RShiftU64 (*OrMask, RightByteShift * 8); } =20 *Length -=3D SubLength; *Base +=3D SubLength; =20 - *LastMsrNum =3D MsrNum; - *ReturnClearMask =3D ClearMask; - *ReturnOrMask =3D OrMask; + *LastMsrIndex =3D MsrIndex; =20 return RETURN_SUCCESS; } --=20 2.12.2.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:00:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507798100613226.93744001754885; Thu, 12 Oct 2017 01:48:20 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D1C3C21F38829; Thu, 12 Oct 2017 01:44:45 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DFEFF21FC7497 for ; Thu, 12 Oct 2017 01:44:44 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP; 12 Oct 2017 01:48:15 -0700 Received: from ray-dev.ccr.corp.intel.com ([10.239.9.7]) by FMSMGA003.fm.intel.com with ESMTP; 12 Oct 2017 01:48:14 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,365,1503385200"; d="scan'208";a="909212124" From: Ruiyu Ni To: edk2-devel@lists.01.org Date: Thu, 12 Oct 2017 16:48:08 +0800 Message-Id: <20171012084810.148196-3-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.12.2.windows.2 In-Reply-To: <20171012084810.148196-1-ruiyu.ni@intel.com> References: <20171012084810.148196-1-ruiyu.ni@intel.com> Subject: [edk2] [PATCH 2/4] UefiCpuPkg/MtrrLib: Optimize MtrrLibLeastAlignment() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael D Kinney , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The patch changes MtrrLibLeastAlignment() to MtrrLibBiggestAlignment() and optimizes the implementation to be more efficient. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Michael D Kinney Cc: Eric Dong --- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/Mtrr= Lib/MtrrLib.c index 5b21fe11f1..0fecc0122c 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -656,7 +656,8 @@ MtrrGetMemoryAttributeInVariableMtrr ( } =20 /** - Return the least alignment of address. + Return the biggest alignment (lowest set bit) of address. + The function is equivalent to: 1 << LowBitSet64 (Address). =20 @param Address The address to return the alignment. @param Alignment0 The alignment to return when Address is 0. @@ -664,7 +665,7 @@ MtrrGetMemoryAttributeInVariableMtrr ( @return The least alignment of the Address. **/ UINT64 -MtrrLibLeastAlignment ( +MtrrLibBiggestAlignment ( UINT64 Address, UINT64 Alignment0 ) @@ -673,7 +674,7 @@ MtrrLibLeastAlignment ( return Alignment0; } =20 - return LShiftU64 (1, (UINTN) LowBitSet64 (Address)); + return Address & ((~Address) + 1); } =20 /** @@ -705,12 +706,12 @@ MtrrLibGetPositiveMtrrNumber ( // for (MtrrNumber =3D 0; Length !=3D 0; MtrrNumber++) { if (UseLeastAlignment) { - SubLength =3D MtrrLibLeastAlignment (BaseAddress, Alignment0); + SubLength =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); =20 if (SubLength > Length) { // // Set a flag when remaining length is too small - // so that MtrrLibLeastAlignment() is not called in following loo= ps. + // so that MtrrLibBiggestAlignment() is not called in following l= oops. // UseLeastAlignment =3D FALSE; } @@ -873,7 +874,7 @@ MtrrLibGetMtrrNumber ( // Left subtraction bit by bit, to find the optimal left subtraction s= olution. // for (SubtractiveMtrrNumber =3D 0, SubtractiveCount =3D 1; BaseAddress = !=3D 0; SubtractiveCount++) { - Alignment =3D MtrrLibLeastAlignment (BaseAddress, Alignment0); + Alignment =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); =20 // // Check whether the memory type of [BaseAddress - Alignment, BaseAd= dress) can override Type. @@ -928,7 +929,7 @@ MtrrLibGetMtrrNumber ( // MiddleMtrrNumber =3D 0; while (Length !=3D 0) { - BaseAlignment =3D MtrrLibLeastAlignment (BaseAddress, Alignment0); + BaseAlignment =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); if (BaseAlignment > Length) { break; } @@ -953,7 +954,7 @@ MtrrLibGetMtrrNumber ( LeastRightMtrrNumber =3D MtrrLibGetPositiveMtrrNumber (BaseAddress, Leng= th, Alignment0); =20 for (SubtractiveCount =3D 1; Length < BaseAlignment; SubtractiveCount++)= { - Alignment =3D MtrrLibLeastAlignment (BaseAddress + Length, Alignment0); + Alignment =3D MtrrLibBiggestAlignment (BaseAddress + Length, Alignment= 0); if (!MtrrLibSubstractable (Ranges, RangeCount, Type, BaseAddress + Len= gth, Alignment)) { break; } @@ -1644,7 +1645,7 @@ MtrrLibSetMemoryAttributeInVariableMtrr ( } =20 while (SubtractiveLeft-- !=3D 0) { - Alignment =3D MtrrLibLeastAlignment (BaseAddress, Alignment0); + Alignment =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); ASSERT (Alignment <=3D Length); =20 MtrrLibAddVariableMtrr (Ranges, RangeCount, VariableMtrr, VariableMtrr= Capacity, VariableMtrrCount, @@ -1654,7 +1655,7 @@ MtrrLibSetMemoryAttributeInVariableMtrr ( } =20 while (Length !=3D 0) { - Alignment =3D MtrrLibLeastAlignment (BaseAddress, Alignment0); + Alignment =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); if (Alignment > Length) { break; } @@ -1665,7 +1666,7 @@ MtrrLibSetMemoryAttributeInVariableMtrr ( } =20 while (SubtractiveRight-- !=3D 0) { - Alignment =3D MtrrLibLeastAlignment (BaseAddress + Length, Alignment0); + Alignment =3D MtrrLibBiggestAlignment (BaseAddress + Length, Alignment= 0); MtrrLibAddVariableMtrr (Ranges, RangeCount, VariableMtrr, VariableMtrr= Capacity, VariableMtrrCount, BaseAddress + Length, Alignment, CacheInvalid,= Alignment0); Length +=3D Alignment; @@ -1674,7 +1675,7 @@ MtrrLibSetMemoryAttributeInVariableMtrr ( UseLeastAlignment =3D TRUE; while (Length !=3D 0) { if (UseLeastAlignment) { - Alignment =3D MtrrLibLeastAlignment (BaseAddress, Alignment0); + Alignment =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); if (Alignment > Length) { UseLeastAlignment =3D FALSE; } --=20 2.12.2.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:00:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150779810390241.335728404218685; Thu, 12 Oct 2017 01:48:23 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2457E21F3882F; Thu, 12 Oct 2017 01:44:49 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4CE8E21F3882C for ; Thu, 12 Oct 2017 01:44:47 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP; 12 Oct 2017 01:48:17 -0700 Received: from ray-dev.ccr.corp.intel.com ([10.239.9.7]) by FMSMGA003.fm.intel.com with ESMTP; 12 Oct 2017 01:48:15 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,365,1503385200"; d="scan'208";a="909212136" From: Ruiyu Ni To: edk2-devel@lists.01.org Date: Thu, 12 Oct 2017 16:48:09 +0800 Message-Id: <20171012084810.148196-4-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.12.2.windows.2 In-Reply-To: <20171012084810.148196-1-ruiyu.ni@intel.com> References: <20171012084810.148196-1-ruiyu.ni@intel.com> Subject: [edk2] [PATCH 3/4] UefiCpuPkg/MtrrLib: Update algorithm to calculate optimal settings X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael D Kinney , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The new algorithm converts the problem calculating optimal MTRR settings (using least MTRR registers) to the problem finding the shortest path in a graph. The memory required in extreme but rare case can be up to 256KB, so using local stack buffer is impossible considering current DxeIpl only allocates 128KB stack. The patch changes existing MtrrSetMemoryAttributeInMtrrSettings() and MtrrSetMemoryAttribute() to use the 4-page stack buffer for calculation. The two APIs return BUFFER_TOO_SMALL when the buffer is too small for calculation. The patch adds a new API MtrrSetMemoryAttribute*s*InMtrrSettings() to set multiple-range attributes in one function call. Since every call to MtrrSetMemoryAttributeInMtrrSettings (without-s) or MtrrSetMemoryAttribute() requires to calculate the MTRRs for the whole physical memory, combining multiple calls in one API can significantly reduce the calculation time. In theory, if N times of call to without-s API costs N seconds, the new API only costs 1 second. The new API uses the buffer supplied from caller to calculate MTRRs and returns BUFFER_TOO_SMALL when the buffer is too small for calculation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Michael D Kinney Cc: Eric Dong --- UefiCpuPkg/Include/Library/MtrrLib.h | 45 +- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 2375 ++++++++++++++++++++----------= ---- 2 files changed, 1435 insertions(+), 985 deletions(-) diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h b/UefiCpuPkg/Include/Libr= ary/MtrrLib.h index 612052640a..d05d839915 100644 --- a/UefiCpuPkg/Include/Library/MtrrLib.h +++ b/UefiCpuPkg/Include/Library/MtrrLib.h @@ -103,6 +103,12 @@ typedef enum { #define MTRR_CACHE_WRITE_BACK 6 #define MTRR_CACHE_INVALID_TYPE 7 =20 +typedef struct { + UINT64 BaseAddress; + UINT64 Length; + MTRR_MEMORY_CACHE_TYPE Type; +} MTRR_MEMORY_RANGE; + /** Returns the variable MTRR count for the CPU. =20 @@ -151,7 +157,7 @@ GetFirmwareVariableMtrrCount ( @retval RETURN_OUT_OF_RESOURCES There are not enough system resources = to modify the attributes of the memory resource range. - + @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MT= RR calculation. **/ RETURN_STATUS EFIAPI @@ -346,7 +352,7 @@ MtrrGetDefaultMemoryType ( BaseAddress and Length cannot be modif= ied. @retval RETURN_OUT_OF_RESOURCES There are not enough system resources = to modify the attributes of the memory resource range. - + @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MT= RR calculation. **/ RETURN_STATUS EFIAPI @@ -357,4 +363,39 @@ MtrrSetMemoryAttributeInMtrrSettings ( IN MTRR_MEMORY_CACHE_TYPE Attribute ); =20 +/** + This function attempts to set the attributes into MTRR setting buffer fo= r multiple memory ranges. + + @param[in, out] MtrrSetting MTRR setting buffer to be set. + @param[in] Scratch A temporary scratch buffer that is used to= perform the calculation. + @param[in, out] ScratchSize Pointer to the size in bytes of the scratc= h buffer. + It may be updated to the actual required s= ize when the calculation + needs more scratch buffer. + @param[in] Ranges Pointer to an array of MTRR_MEMORY_RANGE. + When range overlap happens, the last one t= akes higher priority. + When the function returns, either all the = attributes are set successfully, + or none of them is set. + @param[in] Count of MTRR_MEMORY_RANGE. + + @retval RETURN_SUCCESS The attributes were set for all the me= mory ranges. + @retval RETURN_INVALID_PARAMETER Length in any range is zero. + @retval RETURN_UNSUPPORTED The processor does not support one or = more bytes of the + memory resource range specified by Bas= eAddress and Length in any range. + @retval RETURN_UNSUPPORTED The bit mask of attributes is not supp= ort for the memory resource + range specified by BaseAddress and Len= gth in any range. + @retval RETURN_OUT_OF_RESOURCES There are not enough system resources = to modify the attributes of + the memory resource ranges. + @retval RETURN_ACCESS_DENIED The attributes for the memory resource= range specified by + BaseAddress and Length cannot be modif= ied. + @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MT= RR calculation. +**/ +RETURN_STATUS +EFIAPI +MtrrSetMemoryAttributesInMtrrSettings ( + IN OUT MTRR_SETTINGS *MtrrSetting, + IN VOID *Scratch, + IN OUT UINTN *ScratchSize, + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount + ); #endif // _MTRR_LIB_H_ diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/Mtrr= Lib/MtrrLib.c index 0fecc0122c..a7adbafae3 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -16,8 +16,7 @@ =20 **/ =20 -#include - +#include #include #include =20 @@ -29,8 +28,13 @@ =20 #define OR_SEED 0x0101010101010101ull #define CLEAR_SEED 0xFFFFFFFFFFFFFFFFull - +#define MAX_WEIGHT MAX_UINT8 +#define SCRATCH_BUFFER_SIZE (4 * SIZE_4KB) #define MTRR_LIB_ASSERT_ALIGNED(B, L) ASSERT ((B & ~(L - 1)) =3D=3D B); + +#define M(x,y) ((x) * VectorCount + (y)) +#define O(x,y) ((y) * VectorCount + (x)) + // // Context to save and restore when MTRRs are programmed // @@ -40,10 +44,18 @@ typedef struct { } MTRR_CONTEXT; =20 typedef struct { - UINT64 BaseAddress; + UINT64 Address; + UINT64 Alignment; UINT64 Length; - MTRR_MEMORY_CACHE_TYPE Type; -} MEMORY_RANGE; + UINT8 Type : 7; + + // + // Temprary use for calculating the best MTRR settings. + // + BOOLEAN Visited : 1; + UINT8 Weight; + UINT16 Previous; +} MTRR_LIB_ADDRESS; =20 // // This table defines the offset, base and length of the fixed MTRRs @@ -120,6 +132,21 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemory= CacheTypeShortName[] =3D { "R*" // Invalid }; =20 + +/** + Worker function prints all MTRRs for debugging. + + If MtrrSetting is not NULL, print MTRR settings from input MTRR + settings buffer. + If MtrrSetting is NULL, print MTRR settings from MTRRs. + + @param MtrrSetting A buffer holding all MTRRs content. +**/ +VOID +MtrrDebugPrintAllMtrrsWorker ( + IN MTRR_SETTINGS *MtrrSetting + ); + /** Worker function returns the variable MTRR count for the CPU. =20 @@ -134,7 +161,7 @@ GetVariableMtrrCountWorker ( MSR_IA32_MTRRCAP_REGISTER MtrrCap; =20 MtrrCap.Uint64 =3D AsmReadMsr64 (MSR_IA32_MTRRCAP); - ASSERT (MtrrCap.Bits.VCNT <=3D MTRR_NUMBER_OF_VARIABLE_MTRR); + ASSERT (MtrrCap.Bits.VCNT <=3D ARRAY_SIZE (((MTRR_VARIABLE_SETTINGS *) 0= )->Mtrr)); return MtrrCap.Bits.VCNT; } =20 @@ -418,7 +445,7 @@ MtrrGetVariableMtrrWorker ( { UINT32 Index; =20 - ASSERT (VariableMtrrCount <=3D MTRR_NUMBER_OF_VARIABLE_MTRR); + ASSERT (VariableMtrrCount <=3D ARRAY_SIZE (VariableSettings->Mtrr)); =20 for (Index =3D 0; Index < VariableMtrrCount; Index++) { if (MtrrSetting =3D=3D NULL) { @@ -596,12 +623,13 @@ MtrrGetMemoryAttributeInVariableMtrrWorker ( UINTN Index; UINT32 UsedMtrr; =20 - ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * MTRR_NUMBER_OF_VARIABLE_= MTRR); + ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * ARRAY_SIZE (VariableSett= ings->Mtrr)); for (Index =3D 0, UsedMtrr =3D 0; Index < VariableMtrrCount; Index++) { if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index= ].Mask)->Bits.V !=3D 0) { VariableMtrr[Index].Msr =3D (UINT32)Index; VariableMtrr[Index].BaseAddress =3D (VariableSettings->Mtrr[Index].B= ase & MtrrValidAddressMask); - VariableMtrr[Index].Length =3D ((~(VariableSettings->Mtrr[Index= ].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1; + VariableMtrr[Index].Length =3D + ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & = MtrrValidBitsMask) + 1; VariableMtrr[Index].Type =3D (VariableSettings->Mtrr[Index].B= ase & 0x0ff); VariableMtrr[Index].Valid =3D TRUE; VariableMtrr[Index].Used =3D TRUE; @@ -611,6 +639,44 @@ MtrrGetMemoryAttributeInVariableMtrrWorker ( return UsedMtrr; } =20 +/** + Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array. + One MTRR_MEMORY_RANGE element is created for each MTRR setting. + The routine doesn't remove the overlap or combine the near-by region. + + @param[in] VariableSettings The variable MTRR values to shadow + @param[in] VariableMtrrCount The number of variable MTRRs + @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR + @param[in] MtrrValidAddressMask The valid address mask for MTRR + @param[out] VariableMtrr The array to shadow variable MTRRs co= ntent + + @return Number of MTRRs which has been used. + +**/ +UINT32 +MtrrLibGetRawVariableRanges ( + IN MTRR_VARIABLE_SETTINGS *VariableSettings, + IN UINTN VariableMtrrCount, + IN UINT64 MtrrValidBitsMask, + IN UINT64 MtrrValidAddressMask, + OUT MTRR_MEMORY_RANGE *VariableMtrr + ) +{ + UINTN Index; + UINT32 UsedMtrr; + + ZeroMem (VariableMtrr, sizeof (MTRR_MEMORY_RANGE) * ARRAY_SIZE (Variable= Settings->Mtrr)); + for (Index =3D 0, UsedMtrr =3D 0; Index < VariableMtrrCount; Index++) { + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index= ].Mask)->Bits.V !=3D 0) { + VariableMtrr[Index].BaseAddress =3D (VariableSettings->Mtrr[Index].B= ase & MtrrValidAddressMask); + VariableMtrr[Index].Length =3D + ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & = MtrrValidBitsMask) + 1; + VariableMtrr[Index].Type =3D (MTRR_MEMORY_CACHE_TYPE)(Variabl= eSettings->Mtrr[Index].Base & 0x0ff); + UsedMtrr++; + } + } + return UsedMtrr; +} =20 /** Gets the attribute of variable MTRRs. @@ -678,57 +744,6 @@ MtrrLibBiggestAlignment ( } =20 /** - Return the number of required variable MTRRs to positively cover the - specified range. - - @param BaseAddress Base address of the range. - @param Length Length of the range. - @param Alignment0 Alignment of 0. - - @return The number of the required variable MTRRs. -**/ -UINT32 -MtrrLibGetPositiveMtrrNumber ( - IN UINT64 BaseAddress, - IN UINT64 Length, - IN UINT64 Alignment0 -) -{ - UINT64 SubLength; - UINT32 MtrrNumber; - BOOLEAN UseLeastAlignment; - - UseLeastAlignment =3D TRUE; - SubLength =3D 0; - - // - // Calculate the alignment of the base address. - // - for (MtrrNumber =3D 0; Length !=3D 0; MtrrNumber++) { - if (UseLeastAlignment) { - SubLength =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); - - if (SubLength > Length) { - // - // Set a flag when remaining length is too small - // so that MtrrLibBiggestAlignment() is not called in following l= oops. - // - UseLeastAlignment =3D FALSE; - } - } - - if (!UseLeastAlignment) { - SubLength =3D GetPowerOfTwo64 (Length); - } - - BaseAddress +=3D SubLength; - Length -=3D SubLength; - } - - return MtrrNumber; -} - -/** Return whether the left MTRR type precedes the right MTRR type. =20 The MTRR type precedence rules are: @@ -752,229 +767,6 @@ MtrrLibTypeLeftPrecedeRight ( return (BOOLEAN) (Left =3D=3D CacheUncacheable || (Left =3D=3D CacheWrit= eThrough && Right =3D=3D CacheWriteBack)); } =20 - -/** - Return whether the type of the specified range can precede the specified= type. - - @param Ranges Memory range array holding memory type settings for all - the memory address. - @param RangeCount Count of memory ranges. - @param Type Type to check precedence. - @param SubBase Base address of the specified range. - @param SubLength Length of the specified range. - - @retval TRUE The type of the specified range can precede the Type. - @retval FALSE The type of the specified range cannot precede the Type. - So the subtraction is not applicable. -**/ -BOOLEAN -MtrrLibSubstractable ( - IN CONST MEMORY_RANGE *Ranges, - IN UINT32 RangeCount, - IN MTRR_MEMORY_CACHE_TYPE Type, - IN UINT64 SubBase, - IN UINT64 SubLength -) -{ - UINT32 Index; - UINT64 Length; - // WT > WB - // UC > * - for (Index =3D 0; Index < RangeCount; Index++) { - if (Ranges[Index].BaseAddress <=3D SubBase && SubBase < Ranges[Index].= BaseAddress + Ranges[Index].Length) { - - if (Ranges[Index].BaseAddress + Ranges[Index].Length >=3D SubBase + = SubLength) { - return MtrrLibTypeLeftPrecedeRight (Ranges[Index].Type, Type); - - } else { - if (!MtrrLibTypeLeftPrecedeRight (Ranges[Index].Type, Type)) { - return FALSE; - } - - Length =3D Ranges[Index].BaseAddress + Ranges[Index].Length - SubB= ase; - SubBase +=3D Length; - SubLength -=3D Length; - } - } - } - - ASSERT (FALSE); - return FALSE; -} - -/** - Return the number of required variable MTRRs to cover the specified rang= e. - - The routine considers subtraction in the both side of the range to find = out - the most optimal solution (which uses the least MTRRs). - - @param Ranges Array holding memory type settings of all memory - address. - @param RangeCount Count of memory ranges. - @param VariableMtrr Array holding allocated variable MTRRs. - @param VariableMtrrCount Count of allocated variable MTRRs. - @param BaseAddress Base address of the specified range. - @param Length Length of the specified range. - @param Type MTRR type of the specified range. - @param Alignment0 Alignment of 0. - @param SubLeft Return the count of left subtraction. - @param SubRight Return the count of right subtraction. - - @return Number of required variable MTRRs. -**/ -UINT32 -MtrrLibGetMtrrNumber ( - IN CONST MEMORY_RANGE *Ranges, - IN UINT32 RangeCount, - IN CONST VARIABLE_MTRR *VariableMtrr, - IN UINT32 VariableMtrrCount, - IN UINT64 BaseAddress, - IN UINT64 Length, - IN MTRR_MEMORY_CACHE_TYPE Type, - IN UINT64 Alignment0, - OUT UINT32 *SubLeft, // subtractive from BaseAddress to g= et more aligned address, to save MTRR - OUT UINT32 *SubRight // subtractive from BaseAddress + Le= ngth, to save MTRR - ) -{ - UINT64 Alignment; - UINT32 LeastLeftMtrrNumber; - UINT32 MiddleMtrrNumber; - UINT32 LeastRightMtrrNumber; - UINT32 CurrentMtrrNumber; - UINT32 SubtractiveCount; - UINT32 SubtractiveMtrrNumber; - UINT32 LeastSubtractiveMtrrNumber; - UINT64 SubtractiveBaseAddress; - UINT64 SubtractiveLength; - UINT64 BaseAlignment; - UINT32 Index; - UINT64 OriginalBaseAddress; - UINT64 OriginalLength; - - *SubLeft =3D 0; - *SubRight =3D 0; - LeastSubtractiveMtrrNumber =3D 0; - BaseAlignment =3D 0; - - // - // Get the optimal left subtraction solution. - // - if (BaseAddress !=3D 0) { - - OriginalBaseAddress =3D BaseAddress; - OriginalLength =3D Length; - SubtractiveBaseAddress =3D 0; - SubtractiveLength =3D 0; - // - // Get the MTRR number needed without left subtraction. - // - LeastLeftMtrrNumber =3D MtrrLibGetPositiveMtrrNumber (BaseAddress, Len= gth, Alignment0); - - // - // Left subtraction bit by bit, to find the optimal left subtraction s= olution. - // - for (SubtractiveMtrrNumber =3D 0, SubtractiveCount =3D 1; BaseAddress = !=3D 0; SubtractiveCount++) { - Alignment =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); - - // - // Check whether the memory type of [BaseAddress - Alignment, BaseAd= dress) can override Type. - // IA32 Manual defines the following override rules: - // WT > WB - // UC > * (any) - // - if (!MtrrLibSubstractable (Ranges, RangeCount, Type, BaseAddress - A= lignment, Alignment)) { - break; - } - - for (Index =3D 0; Index < VariableMtrrCount; Index++) { - if ((VariableMtrr[Index].BaseAddress =3D=3D BaseAddress - Alignmen= t) && - (VariableMtrr[Index].Length =3D=3D Alignment)) { - break; - } - } - if (Index =3D=3D VariableMtrrCount) { - // - // Increment SubtractiveMtrrNumber when [BaseAddress - Alignment, = BaseAddress) is not be planed as a MTRR - // - SubtractiveMtrrNumber++; - } - - BaseAddress -=3D Alignment; - Length +=3D Alignment; - - CurrentMtrrNumber =3D SubtractiveMtrrNumber + MtrrLibGetPositiveMtrr= Number (BaseAddress, Length, Alignment0); - if (CurrentMtrrNumber <=3D LeastLeftMtrrNumber) { - LeastLeftMtrrNumber =3D CurrentMtrrNumber; - LeastSubtractiveMtrrNumber =3D SubtractiveMtrrNumber; - *SubLeft =3D SubtractiveCount; - SubtractiveBaseAddress =3D BaseAddress; - SubtractiveLength =3D Length; - } - } - - // - // If left subtraction is better, subtract BaseAddress to left, and en= large Length - // - if (*SubLeft !=3D 0) { - BaseAddress =3D SubtractiveBaseAddress; - Length =3D SubtractiveLength; - } else { - BaseAddress =3D OriginalBaseAddress; - Length =3D OriginalLength; - } - } - - // - // Increment BaseAddress greedily until (BaseAddress + Alignment) exceed= s (BaseAddress + Length) - // - MiddleMtrrNumber =3D 0; - while (Length !=3D 0) { - BaseAlignment =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); - if (BaseAlignment > Length) { - break; - } - BaseAddress +=3D BaseAlignment; - Length -=3D BaseAlignment; - MiddleMtrrNumber++; - } - - - if (Length =3D=3D 0) { - return LeastSubtractiveMtrrNumber + MiddleMtrrNumber; - } - - - // - // Get the optimal right subtraction solution. - // - - // - // Get the MTRR number needed without right subtraction. - // - LeastRightMtrrNumber =3D MtrrLibGetPositiveMtrrNumber (BaseAddress, Leng= th, Alignment0); - - for (SubtractiveCount =3D 1; Length < BaseAlignment; SubtractiveCount++)= { - Alignment =3D MtrrLibBiggestAlignment (BaseAddress + Length, Alignment= 0); - if (!MtrrLibSubstractable (Ranges, RangeCount, Type, BaseAddress + Len= gth, Alignment)) { - break; - } - - Length +=3D Alignment; - - // - // SubtractiveCount =3D Number of MTRRs used for subtraction - // - CurrentMtrrNumber =3D SubtractiveCount + MtrrLibGetPositiveMtrrNumber = (BaseAddress, Length, Alignment0); - if (CurrentMtrrNumber <=3D LeastRightMtrrNumber) { - LeastRightMtrrNumber =3D CurrentMtrrNumber; - *SubRight =3D SubtractiveCount; - SubtractiveLength =3D Length; - } - } - - return LeastSubtractiveMtrrNumber + MiddleMtrrNumber + LeastRightMtrrNum= ber; -} - /** Initializes the valid bits mask and valid address mask for MTRRs. =20 @@ -1065,7 +857,7 @@ MtrrGetMemoryAttributeByAddressWorker ( UINTN Index; UINTN SubIndex; MTRR_MEMORY_CACHE_TYPE MtrrType; - VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTR= R]; + MTRR_MEMORY_RANGE VariableMtrr[ARRAY_SIZE (MtrrSetting->Va= riables.Mtrr)]; UINT64 MtrrValidBitsMask; UINT64 MtrrValidAddressMask; UINT32 VariableMtrrCount; @@ -1111,11 +903,11 @@ MtrrGetMemoryAttributeByAddressWorker ( } =20 VariableMtrrCount =3D GetVariableMtrrCountWorker (); - ASSERT (VariableMtrrCount <=3D MTRR_NUMBER_OF_VARIABLE_MTRR); + ASSERT (VariableMtrrCount <=3D ARRAY_SIZE (MtrrSetting->Variables.Mtrr)); MtrrGetVariableMtrrWorker (MtrrSetting, VariableMtrrCount, &VariableSett= ings); =20 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask); - MtrrGetMemoryAttributeInVariableMtrrWorker ( + MtrrLibGetRawVariableRanges ( &VariableSettings, VariableMtrrCount, MtrrValidBitsMask, @@ -1128,7 +920,7 @@ MtrrGetMemoryAttributeByAddressWorker ( // MtrrType =3D CacheInvalid; for (Index =3D 0; Index < VariableMtrrCount; Index++) { - if (VariableMtrr[Index].Valid) { + if (VariableMtrr[Index].Length !=3D 0) { if (Address >=3D VariableMtrr[Index].BaseAddress && Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].= Length) { if (MtrrType =3D=3D CacheInvalid) { @@ -1175,178 +967,6 @@ MtrrGetMemoryAttribute ( } =20 /** - Worker function prints all MTRRs for debugging. - - If MtrrSetting is not NULL, print MTRR settings from input MTRR - settings buffer. - If MtrrSetting is NULL, print MTRR settings from MTRRs. - - @param MtrrSetting A buffer holding all MTRRs content. -**/ -VOID -MtrrDebugPrintAllMtrrsWorker ( - IN MTRR_SETTINGS *MtrrSetting - ) -{ - DEBUG_CODE ( - MTRR_SETTINGS LocalMtrrs; - MTRR_SETTINGS *Mtrrs; - UINTN Index; - UINTN Index1; - UINTN VariableMtrrCount; - UINT64 Base; - UINT64 Limit; - UINT64 MtrrBase; - UINT64 MtrrLimit; - UINT64 RangeBase; - UINT64 RangeLimit; - UINT64 NoRangeBase; - UINT64 NoRangeLimit; - UINT32 RegEax; - UINTN MemoryType; - UINTN PreviousMemoryType; - BOOLEAN Found; - - if (!IsMtrrSupported ()) { - return; - } - - DEBUG((DEBUG_CACHE, "MTRR Settings\n")); - DEBUG((DEBUG_CACHE, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n")); - - if (MtrrSetting !=3D NULL) { - Mtrrs =3D MtrrSetting; - } else { - MtrrGetAllMtrrs (&LocalMtrrs); - Mtrrs =3D &LocalMtrrs; - } - - DEBUG((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType)= ); - for (Index =3D 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) { - DEBUG((DEBUG_CACHE, "Fixed MTRR[%02d] : %016lx\n", Index, Mtrrs->F= ixed.Mtrr[Index])); - } - - VariableMtrrCount =3D GetVariableMtrrCount (); - for (Index =3D 0; Index < VariableMtrrCount; Index++) { - DEBUG((DEBUG_CACHE, "Variable MTRR[%02d]: Base=3D%016lx Mask=3D%016l= x\n", - Index, - Mtrrs->Variables.Mtrr[Index].Base, - Mtrrs->Variables.Mtrr[Index].Mask - )); - } - DEBUG((DEBUG_CACHE, "\n")); - DEBUG((DEBUG_CACHE, "MTRR Ranges\n")); - DEBUG((DEBUG_CACHE, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n")); - - Base =3D 0; - PreviousMemoryType =3D MTRR_CACHE_INVALID_TYPE; - for (Index =3D 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) { - Base =3D mMtrrLibFixedMtrrTable[Index].BaseAddress; - for (Index1 =3D 0; Index1 < 8; Index1++) { - MemoryType =3D (UINTN)(RShiftU64 (Mtrrs->Fixed.Mtrr[Index], Index1 *= 8) & 0xff); - if (MemoryType > CacheWriteBack) { - MemoryType =3D MTRR_CACHE_INVALID_TYPE; - } - if (MemoryType !=3D PreviousMemoryType) { - if (PreviousMemoryType !=3D MTRR_CACHE_INVALID_TYPE) { - DEBUG((DEBUG_CACHE, "%016lx\n", Base - 1)); - } - PreviousMemoryType =3D MemoryType; - DEBUG((DEBUG_CACHE, "%a:%016lx-", mMtrrMemoryCacheTypeShortName[= MemoryType], Base)); - } - Base +=3D mMtrrLibFixedMtrrTable[Index].Length; - } - } - DEBUG((DEBUG_CACHE, "%016lx\n", Base - 1)); - - VariableMtrrCount =3D GetVariableMtrrCount (); - - Limit =3D BIT36 - 1; - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); - if (RegEax >=3D 0x80000008) { - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); - Limit =3D LShiftU64 (1, RegEax & 0xff) - 1; - } - Base =3D BASE_1MB; - PreviousMemoryType =3D MTRR_CACHE_INVALID_TYPE; - do { - MemoryType =3D MtrrGetMemoryAttributeByAddressWorker (Mtrrs, Base); - if (MemoryType > CacheWriteBack) { - MemoryType =3D MTRR_CACHE_INVALID_TYPE; - } - - if (MemoryType !=3D PreviousMemoryType) { - if (PreviousMemoryType !=3D MTRR_CACHE_INVALID_TYPE) { - DEBUG((DEBUG_CACHE, "%016lx\n", Base - 1)); - } - PreviousMemoryType =3D MemoryType; - DEBUG((DEBUG_CACHE, "%a:%016lx-", mMtrrMemoryCacheTypeShortName[Me= moryType], Base)); - } - - RangeBase =3D BASE_1MB; - NoRangeBase =3D BASE_1MB; - RangeLimit =3D Limit; - NoRangeLimit =3D Limit; - - for (Index =3D 0, Found =3D FALSE; Index < VariableMtrrCount; Index+= +) { - if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) =3D=3D 0) { - // - // If mask is not valid, then do not display range - // - continue; - } - MtrrBase =3D (Mtrrs->Variables.Mtrr[Index].Base & (~(SIZE_4KB - 1= ))); - MtrrLimit =3D MtrrBase + ((~(Mtrrs->Variables.Mtrr[Index].Mask & (= ~(SIZE_4KB - 1)))) & Limit); - - if (Base >=3D MtrrBase && Base < MtrrLimit) { - Found =3D TRUE; - } - - if (Base >=3D MtrrBase && MtrrBase > RangeBase) { - RangeBase =3D MtrrBase; - } - if (Base > MtrrLimit && MtrrLimit > RangeBase) { - RangeBase =3D MtrrLimit + 1; - } - if (Base < MtrrBase && MtrrBase < RangeLimit) { - RangeLimit =3D MtrrBase - 1; - } - if (Base < MtrrLimit && MtrrLimit <=3D RangeLimit) { - RangeLimit =3D MtrrLimit; - } - - if (Base > MtrrLimit && NoRangeBase < MtrrLimit) { - NoRangeBase =3D MtrrLimit + 1; - } - if (Base < MtrrBase && NoRangeLimit > MtrrBase) { - NoRangeLimit =3D MtrrBase - 1; - } - } - - if (Found) { - Base =3D RangeLimit + 1; - } else { - Base =3D NoRangeLimit + 1; - } - } while (Base < Limit); - DEBUG((DEBUG_CACHE, "%016lx\n\n", Base - 1)); - ); -} - - -/** - This function prints all MTRRs for debugging. -**/ -VOID -EFIAPI -MtrrDebugPrintAllMtrrs ( - VOID - ) -{ - MtrrDebugPrintAllMtrrsWorker (NULL); -} - -/** Update the Ranges array to change the specified range identified by BaseAddress and Length to Type. =20 @@ -1359,26 +979,28 @@ MtrrDebugPrintAllMtrrs ( =20 @retval RETURN_SUCCESS The type of the specified memory range is changed successfully. + @retval RETURN_ALREADY_STARTED The type of the specified memory range e= quals + to the desired type. @retval RETURN_OUT_OF_RESOURCES The new type set causes the count of mem= ory range exceeds capacity. **/ RETURN_STATUS MtrrLibSetMemoryType ( - IN MEMORY_RANGE *Ranges, - IN UINT32 Capacity, - IN OUT UINT32 *Count, + IN MTRR_MEMORY_RANGE *Ranges, + IN UINTN Capacity, + IN OUT UINTN *Count, IN UINT64 BaseAddress, IN UINT64 Length, IN MTRR_MEMORY_CACHE_TYPE Type ) { - UINT32 Index; + UINTN Index; UINT64 Limit; UINT64 LengthLeft; UINT64 LengthRight; - UINT32 StartIndex; - UINT32 EndIndex; - UINT32 DeltaCount; + UINTN StartIndex; + UINTN EndIndex; + UINTN DeltaCount; =20 LengthRight =3D 0; LengthLeft =3D 0; @@ -1404,7 +1026,7 @@ MtrrLibSetMemoryType ( =20 ASSERT (StartIndex !=3D *Count && EndIndex !=3D *Count); if (StartIndex =3D=3D EndIndex && Ranges[StartIndex].Type =3D=3D Type) { - return RETURN_SUCCESS; + return RETURN_ALREADY_STARTED; } =20 // @@ -1467,242 +1089,646 @@ MtrrLibSetMemoryType ( } =20 /** - Allocate one or more variable MTRR to cover the range identified by - BaseAddress and Length. + Return the number of memory types in range [BaseAddress, BaseAddress + L= ength). =20 - @param Ranges Memory range array holding the memory type - settings for all memory address. - @param RangeCount Count of memory ranges. - @param VariableMtrr Variable MTRR array. - @param VariableMtrrCapacity Capacity of variable MTRR array. - @param VariableMtrrCount Count of variable MTRR. - @param BaseAddress Base address of the memory range. - @param Length Length of the memory range. - @param Type MTRR type of the memory range. - @param Alignment0 Alignment of 0. + @param Ranges Array holding memory type settings for all memory reg= ions. + @param RangeCount The count of memory ranges the array holds. + @param BaseAddress Base address. + @param Length Length. + @param Types Return bit mask to indicate all memory types in the s= pecified range. =20 - @retval RETURN_SUCCESS Variable MTRRs are allocated successfull= y. - @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity. + @retval Number of memory types. **/ -RETURN_STATUS -MtrrLibSetMemoryAttributeInVariableMtrr ( - IN CONST MEMORY_RANGE *Ranges, - IN UINT32 RangeCount, - IN OUT VARIABLE_MTRR *VariableMtrr, - IN UINT32 VariableMtrrCapacity, - IN OUT UINT32 *VariableMtrrCount, - IN UINT64 BaseAddress, - IN UINT64 Length, - IN MTRR_MEMORY_CACHE_TYPE Type, - IN UINT64 Alignment0 - ); +UINT8 +MtrrLibGetNumberOfTypes ( + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount, + IN UINT64 BaseAddress, + IN UINT64 Length, + IN OUT UINT8 *Types OPTIONAL + ) +{ + UINTN Index; + UINT8 TypeCount; + UINT8 LocalTypes; + + TypeCount =3D 0; + LocalTypes =3D 0; + for (Index =3D 0; Index < RangeCount; Index++) { + if ((Ranges[Index].BaseAddress <=3D BaseAddress) && + (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length) + ) { + if ((LocalTypes & (1 << Ranges[Index].Type)) =3D=3D 0) { + LocalTypes |=3D (UINT8)(1 << Ranges[Index].Type); + TypeCount++; + } + + if (BaseAddress + Length > Ranges[Index].BaseAddress + Ranges[Index]= .Length) { + Length -=3D Ranges[Index].BaseAddress + Ranges[Index].Length - Bas= eAddress; + BaseAddress =3D Ranges[Index].BaseAddress + Ranges[Index].Length; + } else { + break; + } + } + } + + if (Types !=3D NULL) { + *Types =3D LocalTypes; + } + return TypeCount; +} =20 /** - Allocate one or more variable MTRR to cover the range identified by - BaseAddress and Length. + Calculate the least MTRR number from vector Start to Stop and update + the Previous of all vectors from Start to Stop is updated to reflect + how the memory range is covered by MTRR. + + @param VectorCount The count of vectors in the graph. + @param Vector Array holding all vectors. + @param Weight 2-dimention array holding weights between vectors. + @param Start Start vector. + @param Stop Stop vector. + @param IncludeOptional TRUE to count the optional weight. +**/ +VOID +MtrrLibCalculateLeastMtrrs ( + IN UINT16 VectorCount, + IN MTRR_LIB_ADDRESS *Vector, + IN OUT CONST UINT8 *Weight, + IN UINT16 Start, + IN UINT16 Stop, + IN BOOLEAN IncludeOptional + ) +{ + UINT16 Index; + UINT8 MinWeight; + UINT16 MinI; + UINT8 Mandatory; + UINT8 Optional; + + for (Index =3D Start; Index <=3D Stop; Index++) { + Vector[Index].Visited =3D FALSE; + Vector[Index].Previous =3D VectorCount; + Mandatory =3D Weight[M(Start,Index)]; + Vector[Index].Weight =3D Mandatory; + if (Mandatory !=3D MAX_WEIGHT) { + Optional =3D IncludeOptional ? Weight[O(Start, Index)] : 0; + Vector[Index].Weight +=3D Optional; + ASSERT (Vector[Index].Weight >=3D Optional); + } + } =20 - The routine recursively calls MtrrLibSetMemoryAttributeInVariableMtrr() - to allocate variable MTRRs when the range contains several sub-ranges - with different attributes. + MinI =3D Start; + MinWeight =3D 0; + while (!Vector[Stop].Visited) { + // + // Update the weight from the shortest vector to other unvisited vecto= rs + // + for (Index =3D Start + 1; Index <=3D Stop; Index++) { + if (!Vector[Index].Visited) { + Mandatory =3D Weight[M(MinI, Index)]; + if (Mandatory !=3D MAX_WEIGHT) { + Optional =3D IncludeOptional ? Weight[O(MinI, Index)] : 0; + if (MinWeight + Mandatory + Optional <=3D Vector[Index].Weight) { + Vector[Index].Weight =3D MinWeight + Mandatory + Optional; + Vector[Index].Previous =3D MinI; // Previous is Start based. + } + } + } + } =20 - @param Ranges Memory range array holding the memory type - settings for all memory address. - @param RangeCount Count of memory ranges. - @param VariableMtrr Variable MTRR array. - @param VariableMtrrCapacity Capacity of variable MTRR array. - @param VariableMtrrCount Count of variable MTRR. - @param BaseAddress Base address of the memory range. - @param Length Length of the memory range. - @param Type MTRR type of the range. - If it's CacheInvalid, the memory range may - contains several sub-ranges with different - attributes. - @param Alignment0 Alignment of 0. + // + // Find the shortest vector from Start + // + MinI =3D VectorCount; + MinWeight =3D MAX_WEIGHT; + for (Index =3D Start + 1; Index <=3D Stop; Index++) { + if (!Vector[Index].Visited && MinWeight > Vector[Index].Weight) { + MinI =3D Index; + MinWeight =3D Vector[Index].Weight; + } + } =20 - @retval RETURN_SUCCESS Variable MTRRs are allocated successfull= y. - @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity. + // + // Mark the shortest vector from Start as visited + // + Vector[MinI].Visited =3D TRUE; + } +} + +/** + Append the MTRR setting to MTRR setting array. + + @param Mtrrs Array holding all MTRR settings. + @param MtrrCapacity Capacity of the MTRR array. + @param MtrrCount The count of MTRR settings in array. + @param BaseAddress Base address. + @param Length Length. + @param Type Memory type. + + @retval RETURN_SUCCESS MTRR setting is appended to array. + @retval RETURN_OUT_OF_RESOURCES Array is full. **/ RETURN_STATUS -MtrrLibAddVariableMtrr ( - IN CONST MEMORY_RANGE *Ranges, - IN UINT32 RangeCount, - IN OUT VARIABLE_MTRR *VariableMtrr, - IN UINT32 VariableMtrrCapacity, - IN OUT UINT32 *VariableMtrrCount, - IN PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN MTRR_MEMORY_CACHE_TYPE Type, - IN UINT64 Alignment0 +MtrrLibAppendVariableMtrr ( + IN OUT MTRR_MEMORY_RANGE *Mtrrs, + IN UINT32 MtrrCapacity, + IN OUT UINT32 *MtrrCount, + IN UINT64 BaseAddress, + IN UINT64 Length, + IN MTRR_MEMORY_CACHE_TYPE Type + ) +{ + if (*MtrrCount =3D=3D MtrrCapacity) { + return RETURN_OUT_OF_RESOURCES; + } + + Mtrrs[*MtrrCount].BaseAddress =3D BaseAddress; + Mtrrs[*MtrrCount].Length =3D Length; + Mtrrs[*MtrrCount].Type =3D Type; + (*MtrrCount)++; + return RETURN_SUCCESS; +} + +/** + Return the memory type that has the least precedence. + + @param TypeBits Bit mask of memory type. + + @retval Memory type that has the least precedence. +**/ +MTRR_MEMORY_CACHE_TYPE +MtrrLibLowestType ( + IN UINT8 TypeBits ) { - RETURN_STATUS Status; - UINT32 Index; - UINT64 SubLength; + INT8 Type; =20 - MTRR_LIB_ASSERT_ALIGNED (BaseAddress, Length); - if (Type =3D=3D CacheInvalid) { - ASSERT (Ranges !=3D NULL); - for (Index =3D 0; Index < RangeCount; Index++) { - if (Ranges[Index].BaseAddress <=3D BaseAddress && BaseAddress < Rang= es[Index].BaseAddress + Ranges[Index].Length) { + ASSERT (TypeBits !=3D 0); + for (Type =3D 7; (INT8)TypeBits > 0; Type--, TypeBits <<=3D 1); + return (MTRR_MEMORY_CACHE_TYPE)Type; +} =20 - // - // Because the Length may not be aligned to BaseAddress, below cod= e calls - // MtrrLibSetMemoryAttributeInVariableMtrr() instead of itself. - // MtrrLibSetMemoryAttributeInVariableMtrr() splits the range to s= everal - // aligned ranges. - // - if (Ranges[Index].BaseAddress + Ranges[Index].Length >=3D BaseAddr= ess + Length) { - return MtrrLibSetMemoryAttributeInVariableMtrr ( - Ranges, RangeCount, VariableMtrr, VariableMtrrCapacity, Variab= leMtrrCount, - BaseAddress, Length, Ranges[Index].Type, Alignment0 - ); - } else { - SubLength =3D Ranges[Index].BaseAddress + Ranges[Index].Length -= BaseAddress; - Status =3D MtrrLibSetMemoryAttributeInVariableMtrr ( - Ranges, RangeCount, VariableMtrr, VariableMtrrCapacity, Variab= leMtrrCount, - BaseAddress, SubLength, Ranges[Index].Type, Alignment0 - ); - if (RETURN_ERROR (Status)) { - return Status; - } - BaseAddress +=3D SubLength; - Length -=3D SubLength; - } - } +/** + Return TRUE when the Operand is exactly power of 2. + + @retval TRUE Operand is exactly power of 2. + @retval FALSE Operand is not power of 2. +**/ +BOOLEAN +MtrrLibIsPowerOfTwo ( + IN UINT64 Operand +) +{ + ASSERT (Operand !=3D 0); + return (BOOLEAN) ((Operand & (Operand - 1)) =3D=3D 0); +} + +/** + Calculate the subtractive path from vector Start to Stop. + + @param DefaultType Default memory type. + @param A0 Alignment to use when base address is 0. + @param Ranges Array holding memory type settings for all memory re= gions. + @param RangeCount The count of memory ranges the array holds. + @param VectorCount The count of vectors in the graph. + @param Vector Array holding all vectors. + @param Weight 2-dimention array holding weights between vectors. + @param Start Start vector. + @param Stop Stop vector. + @param Types Type bit mask of memory range from Start to Stop. + @param TypeCount Number of different memory types from Start to Stop. + @param Mtrrs Array holding all MTRR settings. + @param MtrrCapacity Capacity of the MTRR array. + @param MtrrCount The count of MTRR settings in array. + + @retval RETURN_SUCCESS The subtractive path is calculated succe= ssfully. + @retval RETURN_OUT_OF_RESOURCES The MTRR setting array is full. + +**/ +RETURN_STATUS +MtrrLibCalculateSubtractivePath ( + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN UINT64 A0, + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount, + IN UINT16 VectorCount, + IN MTRR_LIB_ADDRESS *Vector, + IN OUT UINT8 *Weight, + IN UINT16 Start, + IN UINT16 Stop, + IN UINT8 Types, + IN UINT8 TypeCount, + IN OUT MTRR_MEMORY_RANGE *Mtrrs, OPTIONAL + IN UINT32 MtrrCapacity, OPTIONAL + IN OUT UINT32 *MtrrCount OPTIONAL + ) +{ + RETURN_STATUS Status; + UINT64 Base; + UINT64 Length; + UINT8 PrecedentTypes; + UINTN Index; + UINT64 HBase; + UINT64 HLength; + UINT64 SubLength; + UINT16 SubStart; + UINT16 SubStop; + UINT16 Cur; + UINT16 Pre; + MTRR_MEMORY_CACHE_TYPE LowestType; + MTRR_MEMORY_CACHE_TYPE LowestPrecedentType; + + Base =3D Vector[Start].Address; + Length =3D Vector[Stop].Address - Base; + + LowestType =3D MtrrLibLowestType (Types); + + // + // Clear the lowest type (highest bit) to get the precedent types + // + PrecedentTypes =3D ~(1 << LowestType) & Types; + LowestPrecedentType =3D MtrrLibLowestType (PrecedentTypes); + + if (Mtrrs =3D=3D NULL) { + Weight[M(Start, Stop)] =3D ((LowestType =3D=3D DefaultType) ? 0 : 1); + Weight[O(Start, Stop)] =3D ((LowestType =3D=3D DefaultType) ? 1 : 0); + } + + // Add all high level ranges + HBase =3D MAX_UINT64; + HLength =3D 0; + for (Index =3D 0; Index < RangeCount; Index++) { + if (Length =3D=3D 0) { + break; + } + if ((Base < Ranges[Index].BaseAddress) || (Ranges[Index].BaseAddress += Ranges[Index].Length <=3D Base)) { + continue; } =20 // - // Because memory ranges cover all the memory addresses, it's impossib= le to be here. + // Base is in the Range[Index] // - ASSERT (FALSE); - return RETURN_DEVICE_ERROR; - } else { - for (Index =3D 0; Index < *VariableMtrrCount; Index++) { - if (VariableMtrr[Index].BaseAddress =3D=3D BaseAddress && VariableMt= rr[Index].Length =3D=3D Length) { - ASSERT (VariableMtrr[Index].Type =3D=3D Type); - break; + if (Base + Length > Ranges[Index].BaseAddress + Ranges[Index].Length) { + SubLength =3D Ranges[Index].BaseAddress + Ranges[Index].Length - Bas= e; + } else { + SubLength =3D Length; + } + if (((1 << Ranges[Index].Type) & PrecedentTypes) !=3D 0) { + // + // Meet a range whose types take precedence. + // Update the [HBase, HBase + HLength) to include the range, + // [HBase, HBase + HLength) may contain sub ranges with 2 different = types, and both take precedence. + // + if (HBase =3D=3D MAX_UINT64) { + HBase =3D Base; } + HLength +=3D SubLength; } - if (Index =3D=3D *VariableMtrrCount) { - if (*VariableMtrrCount =3D=3D VariableMtrrCapacity) { - return RETURN_OUT_OF_RESOURCES; + + Base +=3D SubLength; + Length -=3D SubLength; + + if (HLength =3D=3D 0) { + continue; + } + + if ((Ranges[Index].Type =3D=3D LowestType) || (Length =3D=3D 0)) { // = meet low type or end + + // + // Add the MTRRs for each high priority type range + // the range[HBase, HBase + HLength) contains only two types. + // We might use positive or subtractive, depending on which way uses= less MTRR + // + for (SubStart =3D Start; SubStart <=3D Stop; SubStart++) { + if (Vector[SubStart].Address =3D=3D HBase) { + break; + } } - VariableMtrr[Index].BaseAddress =3D BaseAddress; - VariableMtrr[Index].Length =3D Length; - VariableMtrr[Index].Type =3D Type; - VariableMtrr[Index].Valid =3D TRUE; - VariableMtrr[Index].Used =3D TRUE; - (*VariableMtrrCount)++; + + for (SubStop =3D SubStart; SubStop <=3D Stop; SubStop++) { + if (Vector[SubStop].Address =3D=3D HBase + HLength) { + break; + } + } + ASSERT (Vector[SubStart].Address =3D=3D HBase); + ASSERT (Vector[SubStop].Address =3D=3D HBase + HLength); + + if ((TypeCount =3D=3D 2) || (SubStart =3D=3D SubStop - 1)) { + // + // add subtractive MTRRs for [HBase, HBase + HLength) + // [HBase, HBase + HLength) contains only one type. + // while - loop is to split the range to MTRR - compliant aligned = range. + // + if (Mtrrs =3D=3D NULL) { + Weight[M (Start, Stop)] +=3D (UINT8)(SubStop - SubStart); + } else { + while (SubStart !=3D SubStop) { + Status =3D MtrrLibAppendVariableMtrr ( + Mtrrs, MtrrCapacity, MtrrCount, + Vector[SubStart].Address, Vector[SubStart].Length, (MTRR_MEM= ORY_CACHE_TYPE) Vector[SubStart].Type + ); + if (RETURN_ERROR (Status)) { + return Status; + } + SubStart++; + } + } + } else { + ASSERT (TypeCount =3D=3D 3); + MtrrLibCalculateLeastMtrrs (VectorCount, Vector, Weight, SubStart,= SubStop, TRUE); + + if (Mtrrs =3D=3D NULL) { + Weight[M (Start, Stop)] +=3D Vector[SubStop].Weight; + } else { + // When we need to collect the optimal path from SubStart to Sub= Stop + while (SubStop !=3D SubStart) { + Cur =3D SubStop; + Pre =3D Vector[Cur].Previous; + SubStop =3D Pre; + + if (Weight[M (Pre, Cur)] !=3D 0) { + Status =3D MtrrLibAppendVariableMtrr ( + Mtrrs, MtrrCapacity, MtrrCount, + Vector[Pre].Address, Vector[Cur].Address - Vector[Pre].Add= ress, LowestPrecedentType + ); + if (RETURN_ERROR (Status)) { + return Status; + } + } + if (Pre !=3D Cur - 1) { + Status =3D MtrrLibCalculateSubtractivePath ( + DefaultType, A0, + Ranges, RangeCount, + VectorCount, Vector, Weight, + Pre, Cur, PrecedentTypes, 2, + Mtrrs, MtrrCapacity, MtrrCount + ); + if (RETURN_ERROR (Status)) { + return Status; + } + } + } + } + + } + // + // Reset HBase, HLength + // + HBase =3D MAX_UINT64; + HLength =3D 0; } - return RETURN_SUCCESS; } + return RETURN_SUCCESS; } =20 /** - Allocate one or more variable MTRR to cover the range identified by - BaseAddress and Length. - - @param Ranges Memory range array holding the memory type - settings for all memory address. - @param RangeCount Count of memory ranges. - @param VariableMtrr Variable MTRR array. - @param VariableMtrrCapacity Capacity of variable MTRR array. - @param VariableMtrrCount Count of variable MTRR. - @param BaseAddress Base address of the memory range. - @param Length Length of the memory range. - @param Type MTRR type of the memory range. - @param Alignment0 Alignment of 0. + Calculate MTRR settings to cover the specified memory ranges. + + @param DefaultType Default memory type. + @param A0 Alignment to use when base address is 0. + @param Ranges Memory range array holding the memory type + settings for all memory address. + @param RangeCount Count of memory ranges. + @param Scratch A temporary scratch buffer that is used to perform t= he calculation. + This is an optional parameter that may be NULL. + @param ScratchSize Pointer to the size in bytes of the scratch buffer. + It may be updated to the actual required size when t= he calculation + needs more scratch buffer. + @param Mtrrs Array holding all MTRR settings. + @param MtrrCapacity Capacity of the MTRR array. + @param MtrrCount The count of MTRR settings in array. =20 @retval RETURN_SUCCESS Variable MTRRs are allocated successfull= y. @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity. + @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR= calculation. **/ RETURN_STATUS -MtrrLibSetMemoryAttributeInVariableMtrr ( - IN CONST MEMORY_RANGE *Ranges, - IN UINT32 RangeCount, - IN OUT VARIABLE_MTRR *VariableMtrr, - IN UINT32 VariableMtrrCapacity, - IN OUT UINT32 *VariableMtrrCount, - IN UINT64 BaseAddress, - IN UINT64 Length, - IN MTRR_MEMORY_CACHE_TYPE Type, - IN UINT64 Alignment0 -) +MtrrLibCalculateMtrrs ( + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN UINT64 A0, + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount, + IN VOID *Scratch, + IN OUT UINTN *ScratchSize, + IN OUT MTRR_MEMORY_RANGE *Mtrrs, + IN UINT32 MtrrCapacity, + IN OUT UINT32 *MtrrCount + ) { + UINT64 Base0; + UINT64 Base1; + UINTN Index; + UINT64 Base; + UINT64 Length; UINT64 Alignment; - UINT32 MtrrNumber; - UINT32 SubtractiveLeft; - UINT32 SubtractiveRight; - BOOLEAN UseLeastAlignment; - - Alignment =3D 0; + UINT64 SubLength; + MTRR_LIB_ADDRESS *Vector; + UINT8 *Weight; + UINT32 VectorIndex; + UINT32 VectorCount; + UINTN RequiredScratchSize; + UINT8 TypeCount; + UINT16 Start; + UINT16 Stop; + UINT8 Type; + RETURN_STATUS Status; =20 - MtrrNumber =3D MtrrLibGetMtrrNumber (Ranges, RangeCount, VariableMtrr, *= VariableMtrrCount, - BaseAddress, Length, Type, Alignment0= , &SubtractiveLeft, &SubtractiveRight); + Base0 =3D Ranges[0].BaseAddress; + Base1 =3D Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Le= ngth; + MTRR_LIB_ASSERT_ALIGNED (Base0, Base1 - Base0); =20 - if (MtrrNumber + *VariableMtrrCount > VariableMtrrCapacity) { - return RETURN_OUT_OF_RESOURCES; + // + // Count the number of vectors. + // + Vector =3D (MTRR_LIB_ADDRESS*)Scratch; + for (VectorIndex =3D 0, Index =3D 0; Index < RangeCount; Index++) { + Base =3D Ranges[Index].BaseAddress; + Length =3D Ranges[Index].Length; + while (Length !=3D 0) { + Alignment =3D MtrrLibBiggestAlignment (Base, A0); + SubLength =3D Alignment; + if (SubLength > Length) { + SubLength =3D GetPowerOfTwo64 (Length); + } + if (VectorIndex < *ScratchSize / sizeof (*Vector)) { + Vector[VectorIndex].Address =3D Base; + Vector[VectorIndex].Alignment =3D Alignment; + Vector[VectorIndex].Type =3D Ranges[Index].Type; + Vector[VectorIndex].Length =3D SubLength; + } + Base +=3D SubLength; + Length -=3D SubLength; + VectorIndex++; + } } + // + // Vector[VectorIndex] =3D Base1, so whole vector count is (VectorIndex = + 1). + // + VectorCount =3D VectorIndex + 1; + DEBUG (( + DEBUG_CACHE, "VectorCount (%016lx - %016lx) =3D %d\n",=20 + Ranges[0].BaseAddress, Ranges[RangeCount - 1].BaseAddress + Ranges[Ran= geCount - 1].Length, VectorCount + )); + ASSERT (VectorCount < MAX_UINT16); =20 - while (SubtractiveLeft-- !=3D 0) { - Alignment =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); - ASSERT (Alignment <=3D Length); - - MtrrLibAddVariableMtrr (Ranges, RangeCount, VariableMtrr, VariableMtrr= Capacity, VariableMtrrCount, - BaseAddress - Alignment, Alignment, CacheInval= id, Alignment0); - BaseAddress -=3D Alignment; - Length +=3D Alignment; + RequiredScratchSize =3D VectorCount * sizeof (*Vector) + VectorCount * V= ectorCount * sizeof (*Weight); + if (*ScratchSize < RequiredScratchSize) { + *ScratchSize =3D RequiredScratchSize; + return RETURN_BUFFER_TOO_SMALL; } + Vector[VectorCount - 1].Address =3D Base1; =20 - while (Length !=3D 0) { - Alignment =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); - if (Alignment > Length) { - break; + Weight =3D (UINT8 *) &Vector[VectorCount]; + // + // Set mandatory weight between any vector to max + // Set optional weight and between any vector and self->self to 0 + // E.g.: + // 00 FF FF FF + // 00 00 FF FF + // 00 00 00 FF + // 00 00 00 00 + // + for (VectorIndex =3D 0; VectorIndex < VectorCount; VectorIndex++) { + SetMem (&Weight[M(VectorIndex, 0)], VectorIndex + 1, 0); + if (VectorIndex !=3D VectorCount - 1) { + Weight[M (VectorIndex, VectorIndex + 1)] =3D (DefaultType =3D=3D Vec= tor[VectorIndex].Type) ? 0 : 1; + SetMem (&Weight[M (VectorIndex, VectorIndex + 2)], VectorCount - Vec= torIndex - 2, MAX_WEIGHT); } - MtrrLibAddVariableMtrr (NULL, 0, VariableMtrr, VariableMtrrCapacity, V= ariableMtrrCount, - BaseAddress, Alignment, Type, Alignment0); - BaseAddress +=3D Alignment; - Length -=3D Alignment; } =20 - while (SubtractiveRight-- !=3D 0) { - Alignment =3D MtrrLibBiggestAlignment (BaseAddress + Length, Alignment= 0); - MtrrLibAddVariableMtrr (Ranges, RangeCount, VariableMtrr, VariableMtrr= Capacity, VariableMtrrCount, - BaseAddress + Length, Alignment, CacheInvalid,= Alignment0); - Length +=3D Alignment; + for (TypeCount =3D 2; TypeCount <=3D 3; TypeCount++) { + for (Start =3D 0; Start < VectorCount; Start++) { + for (Stop =3D Start + 2; Stop < VectorCount; Stop++) { + ASSERT (Vector[Stop].Address > Vector[Start].Address); + Length =3D Vector[Stop].Address - Vector[Start].Address; + if (Length > Vector[Start].Alignment) { + // + // Pickup a new Start when [Start, Stop) cannot be described by = one MTRR. + // + break; + } + if ((Weight[M(Start, Stop)] =3D=3D MAX_WEIGHT) && MtrrLibIsPowerOf= Two (Length)) { + if (MtrrLibGetNumberOfTypes ( + Ranges, RangeCount, Vector[Start].Address, Vector[Stop].Ad= dress - Vector[Start].Address, &Type + ) =3D=3D TypeCount) { + // + // Update the Weight[Start, Stop] using subtractive path. + // + MtrrLibCalculateSubtractivePath ( + DefaultType, A0, + Ranges, RangeCount, + (UINT16)VectorCount, Vector, Weight, + Start, Stop, Type, TypeCount, + NULL, 0, NULL + ); + } else if (TypeCount =3D=3D 2) { + // + // Pick up a new Start when we expect 2-type range, but 3-type= range is met. + // Because no matter how Stop is increased, we always meet 3-t= ype range. + // + break; + } + } + } + } } =20 - UseLeastAlignment =3D TRUE; - while (Length !=3D 0) { - if (UseLeastAlignment) { - Alignment =3D MtrrLibBiggestAlignment (BaseAddress, Alignment0); - if (Alignment > Length) { - UseLeastAlignment =3D FALSE; + Status =3D RETURN_SUCCESS; + MtrrLibCalculateLeastMtrrs ((UINT16) VectorCount, Vector, Weight, 0, (UI= NT16) VectorCount - 1, FALSE); + Stop =3D (UINT16) VectorCount - 1; + while (Stop !=3D 0) { + Start =3D Vector[Stop].Previous; + TypeCount =3D MAX_UINT8; + Type =3D 0; + if (Weight[M(Start, Stop)] !=3D 0) { + TypeCount =3D MtrrLibGetNumberOfTypes (Ranges, RangeCount, Vector[St= art].Address, Vector[Stop].Address - Vector[Start].Address, &Type); + Status =3D MtrrLibAppendVariableMtrr ( + Mtrrs, MtrrCapacity, MtrrCount, + Vector[Start].Address, Vector[Stop].Address - Vector[Start].Addres= s,=20 + MtrrLibLowestType (Type) + ); + if (RETURN_ERROR (Status)) { + break; } } =20 - if (!UseLeastAlignment) { - Alignment =3D GetPowerOfTwo64 (Length); + if (Start !=3D Stop - 1) { + // + // substractive path + // + if (TypeCount =3D=3D MAX_UINT8) { + TypeCount =3D MtrrLibGetNumberOfTypes ( + Ranges, RangeCount, Vector[Start].Address, Vector[St= op].Address - Vector[Start].Address, &Type + ); + } + Status =3D MtrrLibCalculateSubtractivePath ( + DefaultType, A0, + Ranges, RangeCount, + (UINT16) VectorCount, Vector, Weight, Start, Stop, + Type, TypeCount, + Mtrrs, MtrrCapacity, MtrrCount + ); + if (RETURN_ERROR (Status)) { + break; + } } + Stop =3D Start; + } + return Status; +} + =20 - MtrrLibAddVariableMtrr (NULL, 0, VariableMtrr, VariableMtrrCapacity, V= ariableMtrrCount, - BaseAddress, Alignment, Type, Alignment0); - BaseAddress +=3D Alignment; - Length -=3D Alignment; +/** + Apply the variable MTRR settings to memory range array. + + @param Fixed The fixed MTRR settings. + @param Ranges Return the memory range array holding memory ty= pe + settings for all memory address. + @param RangeCapacity The capacity of memory range array. + @param RangeCount Return the count of memory range. + + @retval RETURN_SUCCESS The memory range array is returned succe= ssfully. + @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capac= ity. +**/ +RETURN_STATUS +MtrrLibApplyFixedMtrrs ( + IN MTRR_FIXED_SETTINGS *Fixed, + IN OUT MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCapacity, + IN OUT UINTN *RangeCount + ) +{ + RETURN_STATUS Status; + UINTN MsrIndex; + UINTN Index; + MTRR_MEMORY_CACHE_TYPE MemoryType; + UINT64 Base; + + Base =3D 0; + for (MsrIndex =3D 0; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Msr= Index++) { + ASSERT (Base =3D=3D mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress); + for (Index =3D 0; Index < sizeof (UINT64); Index++) { + MemoryType =3D (MTRR_MEMORY_CACHE_TYPE)((UINT8 *)(&Fixed->Mtrr[MsrIn= dex]))[Index]; + Status =3D MtrrLibSetMemoryType ( + Ranges, RangeCapacity, RangeCount, Base, mMtrrLibFixedMtr= rTable[MsrIndex].Length, MemoryType + ); + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + return Status; + } + Base +=3D mMtrrLibFixedMtrrTable[MsrIndex].Length; + } } + ASSERT (Base =3D=3D BASE_1MB); return RETURN_SUCCESS; } =20 /** - Return an array of memory ranges holding memory type settings for all me= mory - address. + Apply the variable MTRR settings to memory range array. =20 - @param DefaultType The default memory type. - @param TotalLength The total length of the memory. @param VariableMtrr The variable MTRR array. @param VariableMtrrCount The count of variable MTRRs. - @param Ranges Return the memory range array holding memory ty= pe - settings for all memory address. + @param Ranges Return the memory range array with new MTRR set= tings applied. @param RangeCapacity The capacity of memory range array. @param RangeCount Return the count of memory range. =20 @@ -1710,15 +1736,13 @@ MtrrLibSetMemoryAttributeInVariableMtrr ( @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capac= ity. **/ RETURN_STATUS -MtrrLibGetMemoryTypes ( - IN MTRR_MEMORY_CACHE_TYPE DefaultType, - IN UINT64 TotalLength, - IN CONST VARIABLE_MTRR *VariableMtrr, - IN UINT32 VariableMtrrCount, - OUT MEMORY_RANGE *Ranges, - IN UINT32 RangeCapacity, - OUT UINT32 *RangeCount -) +MtrrLibApplyVariableMtrrs ( + IN CONST MTRR_MEMORY_RANGE *VariableMtrr, + IN UINT32 VariableMtrrCount, + IN OUT MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCapacity, + IN OUT UINTN *RangeCount + ) { RETURN_STATUS Status; UINTN Index; @@ -1730,23 +1754,15 @@ MtrrLibGetMemoryTypes ( // =20 // - // 0. Set whole range as DefaultType - // - *RangeCount =3D 1; - Ranges[0].BaseAddress =3D 0; - Ranges[0].Length =3D TotalLength; - Ranges[0].Type =3D DefaultType; - - // // 1. Set WB // for (Index =3D 0; Index < VariableMtrrCount; Index++) { - if (VariableMtrr[Index].Valid && VariableMtrr[Index].Type =3D=3D Cache= WriteBack) { + if ((VariableMtrr[Index].Length !=3D 0) && (VariableMtrr[Index].Type = =3D=3D CacheWriteBack)) { Status =3D MtrrLibSetMemoryType ( Ranges, RangeCapacity, RangeCount, - VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, (MTRR= _MEMORY_CACHE_TYPE) VariableMtrr[Index].Type + VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, Varia= bleMtrr[Index].Type ); - if (RETURN_ERROR (Status)) { + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { return Status; } } @@ -1756,12 +1772,13 @@ MtrrLibGetMemoryTypes ( // 2. Set other types than WB or UC // for (Index =3D 0; Index < VariableMtrrCount; Index++) { - if (VariableMtrr[Index].Valid && VariableMtrr[Index].Type !=3D CacheWr= iteBack && VariableMtrr[Index].Type !=3D CacheUncacheable) { + if ((VariableMtrr[Index].Length !=3D 0) &&=20 + (VariableMtrr[Index].Type !=3D CacheWriteBack) && (VariableMtrr[In= dex].Type !=3D CacheUncacheable)) { Status =3D MtrrLibSetMemoryType ( - Ranges, RangeCapacity, RangeCount, - VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, (MTRR= _MEMORY_CACHE_TYPE) VariableMtrr[Index].Type - ); - if (RETURN_ERROR (Status)) { + Ranges, RangeCapacity, RangeCount, + VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Leng= th, VariableMtrr[Index].Type + ); + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { return Status; } } @@ -1771,12 +1788,12 @@ MtrrLibGetMemoryTypes ( // 3. Set UC // for (Index =3D 0; Index < VariableMtrrCount; Index++) { - if (VariableMtrr[Index].Valid && VariableMtrr[Index].Type =3D=3D Cache= Uncacheable) { + if (VariableMtrr[Index].Length !=3D 0 && VariableMtrr[Index].Type =3D= =3D CacheUncacheable) { Status =3D MtrrLibSetMemoryType ( - Ranges, RangeCapacity, RangeCount, - VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, (MTRR= _MEMORY_CACHE_TYPE) VariableMtrr[Index].Type - ); - if (RETURN_ERROR (Status)) { + Ranges, RangeCapacity, RangeCount, + VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Leng= th, VariableMtrr[Index].Type + ); + if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { return Status; } } @@ -1785,437 +1802,724 @@ MtrrLibGetMemoryTypes ( } =20 /** - Worker function attempts to set the attributes for a memory range. + Return the memory type bit mask that's compatible to first type in the R= anges. =20 - If MtrrSetting is not NULL, set the attributes into the input MTRR - settings buffer. - If MtrrSetting is NULL, set the attributes into MTRRs registers. + @param Ranges Memory range array holding the memory type + settings for all memory address. + @param RangeCount Count of memory ranges. =20 - @param[in, out] MtrrSetting A buffer holding all MTRRs content. - @param[in] BaseAddress The physical address that is the start - address of a memory range. - @param[in] Length The size in bytes of the memory range. - @param[in] Type The MTRR type to set for the memory r= ange. + @return Compatible memory type bit mask. +**/ +UINT8 +MtrrLibGetCompatibleTypes ( + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount + ) +{ + ASSERT (RangeCount !=3D 0); + + switch (Ranges[0].Type) { + case CacheWriteBack: + case CacheWriteThrough: + return (1 << CacheWriteBack) | (1 << CacheWriteThrough) | (1 << CacheU= ncacheable); + break; + + case CacheWriteCombining: + case CacheWriteProtected: + return (1 << Ranges[0].Type) | (1 << CacheUncacheable); + break; + + case CacheUncacheable: + if (RangeCount =3D=3D 1) { + return (1 << CacheUncacheable); + } + return MtrrLibGetCompatibleTypes (&Ranges[1], RangeCount - 1); + break; =20 - @retval RETURN_SUCCESS The attributes were set for the memory - range. - @retval RETURN_INVALID_PARAMETER Length is zero. - @retval RETURN_UNSUPPORTED The processor does not support one or - more bytes of the memory resource range - specified by BaseAddress and Length. - @retval RETURN_UNSUPPORTED The MTRR type is not support for the - memory resource range specified - by BaseAddress and Length. - @retval RETURN_OUT_OF_RESOURCES There are not enough system resources = to - modify the attributes of the memory - resource range. + case CacheInvalid: + default: + ASSERT (FALSE); + break; + } + return 0; +} =20 +/** + Overwrite the destination MTRR settings with the source MTRR settings. + This routine is to make sure the modification to destination MTRR settin= gs + is as small as possible. + + @param DstMtrrs Destination MTRR settings. + @param DstMtrrCount Count of destination MTRR settings. + @param SrcMtrrs Source MTRR settings. + @param SrcMtrrCount Count of source MTRR settings. + @param Modified Flag array to indicate which destination MTRR settin= g is modified. **/ -RETURN_STATUS -MtrrSetMemoryAttributeWorker ( - IN OUT MTRR_SETTINGS *MtrrSetting, - IN PHYSICAL_ADDRESS BaseAddress, - IN UINT64 Length, - IN MTRR_MEMORY_CACHE_TYPE Type +VOID +MtrrLibMergeVariableMtrr ( + MTRR_MEMORY_RANGE *DstMtrrs, + UINT32 DstMtrrCount, + MTRR_MEMORY_RANGE *SrcMtrrs, + UINT32 SrcMtrrCount, + BOOLEAN *Modified ) { - RETURN_STATUS Status; - UINT32 Index; - UINT32 WorkingIndex; - // - // N variable MTRRs can maximumly separate (2N + 1) Ranges, plus 1 range= for [0, 1M). - // - MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR * 2 + 2]; - UINT32 RangeCount; - UINT64 MtrrValidBitsMask; - UINT64 MtrrValidAddressMask; - UINT64 Alignment0; - MTRR_CONTEXT MtrrContext; - BOOLEAN MtrrContextValid; + UINT32 DstIndex; + UINT32 SrcIndex; =20 - MTRR_MEMORY_CACHE_TYPE DefaultType; + ASSERT (SrcMtrrCount <=3D DstMtrrCount); =20 - UINT32 MsrIndex; - UINT64 ClearMask; - UINT64 OrMask; - UINT64 NewValue; - BOOLEAN FixedSettingsValid[MTRR_NUMBER_OF_FIXED_MTRR]; - BOOLEAN FixedSettingsModified[MTRR_NUMBER_OF_FIXED_MTR= R]; - MTRR_FIXED_SETTINGS WorkingFixedSettings; + for (DstIndex =3D 0; DstIndex < DstMtrrCount; DstIndex++) { + Modified[DstIndex] =3D FALSE; =20 - UINT32 FirmwareVariableMtrrCount; - MTRR_VARIABLE_SETTINGS *VariableSettings; - MTRR_VARIABLE_SETTINGS OriginalVariableSettings; - UINT32 OriginalVariableMtrrCount; - VARIABLE_MTRR OriginalVariableMtrr[MTRR_NUMBER_OF_VARIABLE_M= TRR]; - UINT32 WorkingVariableMtrrCount; - VARIABLE_MTRR WorkingVariableMtrr[MTRR_NUMBER_OF_VARIABLE_MT= RR]; - BOOLEAN VariableSettingModified[MTRR_NUMBER_OF_VARIABL= E_MTRR]; - UINTN FreeVariableMtrrCount; + if (DstMtrrs[DstIndex].Length =3D=3D 0) { + continue; + } + for (SrcIndex =3D 0; SrcIndex < SrcMtrrCount; SrcIndex++) { + if (DstMtrrs[DstIndex].BaseAddress =3D=3D SrcMtrrs[SrcIndex].BaseAdd= ress && + DstMtrrs[DstIndex].Length =3D=3D SrcMtrrs[SrcIndex].Length && + DstMtrrs[DstIndex].Type =3D=3D SrcMtrrs[SrcIndex].Type) { + break; + } + } =20 - if (Length =3D=3D 0) { - return RETURN_INVALID_PARAMETER; + if (SrcIndex =3D=3D SrcMtrrCount) { + // + // Remove the one from DstMtrrs which is not in SrcMtrrs + // + DstMtrrs[DstIndex].Length =3D 0; + Modified[DstIndex] =3D TRUE; + } else { + // + // Remove the one from SrcMtrrs which is also in DstMtrrs + // + SrcMtrrs[SrcIndex].Length =3D 0; + } } =20 - MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask); - if (((BaseAddress & ~MtrrValidAddressMask) !=3D 0) || (Length & ~MtrrVal= idAddressMask) !=3D 0) { - return RETURN_UNSUPPORTED; - } - OriginalVariableMtrrCount =3D 0; - VariableSettings =3D NULL; + // + // Now valid MTRR only exists in either DstMtrrs or SrcMtrrs. + // Merge MTRRs from SrcMtrrs to DstMtrrs + // + DstIndex =3D 0; + for (SrcIndex =3D 0; SrcIndex < SrcMtrrCount; SrcIndex++) { + if (SrcMtrrs[SrcIndex].Length !=3D 0) { =20 - ZeroMem (&WorkingFixedSettings, sizeof (WorkingFixedSettings)); - for (Index =3D 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) { - FixedSettingsValid[Index] =3D FALSE; - FixedSettingsModified[Index] =3D FALSE; + // + // Find the empty slot in DstMtrrs + // + while (DstIndex < DstMtrrCount) { + if (DstMtrrs[DstIndex].Length =3D=3D 0) { + break; + } + DstIndex++; + } + ASSERT (DstIndex < DstMtrrCount); + CopyMem (&DstMtrrs[DstIndex], &SrcMtrrs[SrcIndex], sizeof (SrcMtrrs[= 0])); + Modified[DstIndex] =3D TRUE; + } } +} + +/** + Calculate the variable MTRR settings for all memory ranges. =20 + @param DefaultType Default memory type. + @param A0 Alignment to use when base address is 0. + @param Ranges Memory range array holding the memory type + settings for all memory address. + @param RangeCount Count of memory ranges. + @param Scratch Scratch buffer to be used in MTRR calculatio= n. + @param ScratchSize Pointer to the size of scratch buffer. + @param VariableMtrr Array holding all MTRR settings. + @param VariableMtrrCapacity Capacity of the MTRR array. + @param VariableMtrrCount The count of MTRR settings in array. + + @retval RETURN_SUCCESS Variable MTRRs are allocated successfull= y. + @retval RETURN_OUT_OF_RESOURCES Count of variable MTRRs exceeds capacity. + @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MTRR= calculation. + The required scratch buffer size is retu= rned through ScratchSize. +**/ +RETURN_STATUS +MtrrLibSetMemoryRanges ( + IN MTRR_MEMORY_CACHE_TYPE DefaultType, + IN UINT64 A0, + IN MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount, + IN VOID *Scratch, + IN OUT UINTN *ScratchSize, + OUT MTRR_MEMORY_RANGE *VariableMtrr, + IN UINT32 VariableMtrrCapacity, + OUT UINT32 *VariableMtrrCount + ) +{ + RETURN_STATUS Status; + UINT32 Index; + UINT64 Base0; + UINT64 Base1; + UINT64 Alignment; + UINT8 CompatibleTypes; + UINT64 Length; + UINT32 End; + UINTN ActualScratchSize; + UINTN BiggestScratchSize; + + *VariableMtrrCount =3D 0; + =20 // - // Check if Fixed MTRR + // Since the whole ranges need multiple calls of MtrrLibCalculateMtrrs(). + // Each call needs different scratch buffer size. + // When the provided scratch buffer size is not sufficient in any call, + // set the GetActualScratchSize to TRUE, and following calls will only + // calculate the actual scratch size for the caller. // - if (BaseAddress < BASE_1MB) { - MsrIndex =3D (UINT32)-1; - while ((BaseAddress < BASE_1MB) && (Length !=3D 0)) { - Status =3D MtrrLibProgramFixedMtrr (Type, &BaseAddress, &Length, &Ms= rIndex, &ClearMask, &OrMask); - if (RETURN_ERROR (Status)) { - return Status; + BiggestScratchSize =3D 0; + + for (Index =3D 0; Index < RangeCount;) { + Base0 =3D Ranges[Index].BaseAddress; + + // + // Full step is optimal + // + while (Index < RangeCount) { + ASSERT (Ranges[Index].BaseAddress =3D=3D Base0); + Alignment =3D MtrrLibBiggestAlignment (Base0, A0); + while (Base0 + Alignment <=3D Ranges[Index].BaseAddress + Ranges[Ind= ex].Length) { + if ((BiggestScratchSize <=3D *ScratchSize) && (Ranges[Index].Type = !=3D DefaultType)) { + Status =3D MtrrLibAppendVariableMtrr ( + VariableMtrr, VariableMtrrCapacity, VariableMtrrCount, + Base0, Alignment, Ranges[Index].Type + ); + if (RETURN_ERROR (Status)) { + return Status; + } + } + Base0 +=3D Alignment; + Alignment =3D MtrrLibBiggestAlignment (Base0, A0); } - if (MtrrSetting !=3D NULL) { - MtrrSetting->Fixed.Mtrr[MsrIndex] =3D (MtrrSetting->Fixed.Mtrr[Msr= Index] & ~ClearMask) | OrMask; - ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *) &MtrrSetting->MtrrDefType)->B= its.FE =3D 1; + + // + // Remove the above range from Ranges[Index] + // + Ranges[Index].Length -=3D Base0 - Ranges[Index].BaseAddress; + Ranges[Index].BaseAddress =3D Base0; + if (Ranges[Index].Length !=3D 0) { + break; } else { - if (!FixedSettingsValid[MsrIndex]) { - WorkingFixedSettings.Mtrr[MsrIndex] =3D AsmReadMsr64 (mMtrrLibFi= xedMtrrTable[MsrIndex].Msr); - FixedSettingsValid[MsrIndex] =3D TRUE; - } - NewValue =3D (WorkingFixedSettings.Mtrr[MsrIndex] & ~ClearMask) | = OrMask; - if (WorkingFixedSettings.Mtrr[MsrIndex] !=3D NewValue) { - WorkingFixedSettings.Mtrr[MsrIndex] =3D NewValue; - FixedSettingsModified[MsrIndex] =3D TRUE; - } + Index++; } } =20 - if (Length =3D=3D 0) { + if (Index =3D=3D RangeCount) { + break; + } + + // + // Find continous ranges [Base0, Base1) which could be combined by MTR= R. + // Per SDM, the compatible types between[B0, B1) are: + // UC, * + // WB, WT + // UC, WB, WT + // + CompatibleTypes =3D MtrrLibGetCompatibleTypes (&Ranges[Index], RangeCo= unt - Index); + + End =3D Index; // End points to last one that matches the CompatibleTy= pes. + while (End + 1 < RangeCount) { + if (((1 << Ranges[End + 1].Type) & CompatibleTypes) =3D=3D 0) { + break; + } + End++; + } + Alignment =3D MtrrLibBiggestAlignment (Base0, A0); + Length =3D GetPowerOfTwo64 (Ranges[End].BaseAddress + Ranges[End].L= ength - Base0); + Base1 =3D Base0 + MIN (Alignment, Length); + + // + // Base1 may not in Ranges[End]. Update End to the range Base1 belongs= to. + // + End =3D Index; + while (End + 1 < RangeCount) { + if (Base1 <=3D Ranges[End + 1].BaseAddress) { + break; + } + End++; + } + + Length =3D Ranges[End].Length; + Ranges[End].Length =3D Base1 - Ranges[End].BaseAddress; + ActualScratchSize =3D *ScratchSize; + Status =3D MtrrLibCalculateMtrrs ( + DefaultType, A0, + &Ranges[Index], End + 1 - Index, + Scratch, &ActualScratchSize, + VariableMtrr, VariableMtrrCapacity, VariableMtrrCount + ); + if (Status =3D=3D RETURN_BUFFER_TOO_SMALL) { + BiggestScratchSize =3D MAX (BiggestScratchSize, ActualScratchSize); // - // A Length of 0 can only make sense for fixed MTTR ranges. - // Since we just handled the fixed MTRRs, we can skip the - // variable MTRR section. + // Ignore this error, because we need to calculate the biggest + // scratch buffer size. // - goto Done; + Status =3D RETURN_SUCCESS; + } + if (RETURN_ERROR (Status)) { + return Status; + } + + if (Length !=3D Ranges[End].Length) { + Ranges[End].BaseAddress =3D Base1; + Ranges[End].Length =3D Length - Ranges[End].Length; + Index =3D End; + } else { + Index =3D End + 1; } } =20 - // - // Read the default MTRR type - // - DefaultType =3D MtrrGetDefaultMemoryTypeWorker (MtrrSetting); + if (*ScratchSize < BiggestScratchSize) { + *ScratchSize =3D BiggestScratchSize; + return RETURN_BUFFER_TOO_SMALL; + } + return RETURN_SUCCESS; +} =20 - // - // Read all variable MTRRs and convert to Ranges. - // - OriginalVariableMtrrCount =3D GetVariableMtrrCountWorker (); - if (MtrrSetting =3D=3D NULL) { - ZeroMem (&OriginalVariableSettings, sizeof (OriginalVariableSettings)); - MtrrGetVariableMtrrWorker (NULL, OriginalVariableMtrrCount, &OriginalV= ariableSettings); - VariableSettings =3D &OriginalVariableSettings; - } else { - VariableSettings =3D &MtrrSetting->Variables; +/** + Set the below-1MB memory attribute to fixed MTRR buffer. + Modified flag array indicates which fixed MTRR is modified. + + @param [in, out] FixedSettings Fixed MTRR buffer. + @param [out] Modified Flag array indicating which MTRR is modif= ied. + @param [in] BaseAddress Base address. + @param [in] Length Length. + @param [in] Type Memory type. + + @retval RETURN_SUCCESS The memory attribute is set successfully. + @retval RETURN_UNSUPPORTED The requested range or cache type was invalid + for the fixed MTRRs. +**/ +RETURN_STATUS +MtrrLibSetBelow1MBMemoryAttribute ( + IN OUT MTRR_FIXED_SETTINGS *FixedSettings, + OUT BOOLEAN *Modified, + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN MTRR_MEMORY_CACHE_TYPE Type + ) +{ + RETURN_STATUS Status; + UINT32 MsrIndex; + UINT64 ClearMask; + UINT64 OrMask; + UINT64 ClearMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)= ]; + UINT64 OrMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)]; + + ASSERT (BaseAddress < BASE_1MB); + + MsrIndex =3D (UINT32)-1; + while ((BaseAddress < BASE_1MB) && (Length !=3D 0)) { + Status =3D MtrrLibProgramFixedMtrr (Type, &BaseAddress, &Length, &MsrI= ndex, &ClearMask, &OrMask); + if (RETURN_ERROR (Status)) { + return Status; + } + ClearMasks[MsrIndex] =3D ClearMask; + OrMasks[MsrIndex] =3D OrMask; + Modified[MsrIndex] =3D TRUE; } - MtrrGetMemoryAttributeInVariableMtrrWorker (VariableSettings, OriginalVa= riableMtrrCount, MtrrValidBitsMask, MtrrValidAddressMask, OriginalVariableM= trr); =20 - Status =3D MtrrLibGetMemoryTypes ( - DefaultType, MtrrValidBitsMask + 1, OriginalVariableMtrr, OriginalVari= ableMtrrCount, - Ranges, 2 * OriginalVariableMtrrCount + 1, &RangeCount - ); - ASSERT (Status =3D=3D RETURN_SUCCESS); + for (MsrIndex =3D 0; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Msr= Index++) { + if (Modified[MsrIndex]) { + FixedSettings->Mtrr[MsrIndex] =3D (FixedSettings->Mtrr[MsrIndex] & ~= ClearMasks[MsrIndex]) | OrMasks[MsrIndex]; + } + } + return RETURN_SUCCESS; +} + +/** + This function attempts to set the attributes into MTRR setting buffer fo= r multiple memory ranges. =20 - FirmwareVariableMtrrCount =3D GetFirmwareVariableMtrrCountWorker (); - ASSERT (RangeCount <=3D 2 * FirmwareVariableMtrrCount + 1); + @param[in, out] MtrrSetting MTRR setting buffer to be set. + @param[in] Scratch A temporary scratch buffer that is used to= perform the calculation. + @param[in, out] ScratchSize Pointer to the size in bytes of the scratc= h buffer. + It may be updated to the actual required s= ize when the calculation + needs more scratch buffer. + @param[in] Ranges Pointer to an array of MTRR_MEMORY_RANGE. + When range overlap happens, the last one t= akes higher priority. + When the function returns, either all the = attributes are set successfully, + or none of them is set. + @param[in] Count of MTRR_MEMORY_RANGE. + + @retval RETURN_SUCCESS The attributes were set for all the me= mory ranges. + @retval RETURN_INVALID_PARAMETER Length in any range is zero. + @retval RETURN_UNSUPPORTED The processor does not support one or = more bytes of the + memory resource range specified by Bas= eAddress and Length in any range. + @retval RETURN_UNSUPPORTED The bit mask of attributes is not supp= ort for the memory resource + range specified by BaseAddress and Len= gth in any range. + @retval RETURN_OUT_OF_RESOURCES There are not enough system resources = to modify the attributes of + the memory resource ranges. + @retval RETURN_ACCESS_DENIED The attributes for the memory resource= range specified by + BaseAddress and Length cannot be modif= ied. + @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MT= RR calculation. +**/ +RETURN_STATUS +EFIAPI +MtrrSetMemoryAttributesInMtrrSettings ( + IN OUT MTRR_SETTINGS *MtrrSetting, + IN VOID *Scratch, + IN OUT UINTN *ScratchSize, + IN CONST MTRR_MEMORY_RANGE *Ranges, + IN UINTN RangeCount + ) +{ + RETURN_STATUS Status; + UINT32 Index; + UINT64 BaseAddress; + UINT64 Length; + BOOLEAN Above1MbExist; + + UINT64 MtrrValidBitsMask; + UINT64 MtrrValidAddressMask; + MTRR_MEMORY_CACHE_TYPE DefaultType; + MTRR_VARIABLE_SETTINGS VariableSettings; + MTRR_MEMORY_RANGE WorkingRanges[2 * ARRAY_SIZE (MtrrSetting->Var= iables.Mtrr) + 2]; + UINTN WorkingRangeCount; + BOOLEAN Modified; + MTRR_VARIABLE_SETTING VariableSetting; + UINT32 OriginalVariableMtrrCount; + UINT32 FirmwareVariableMtrrCount; + UINT32 WorkingVariableMtrrCount; + MTRR_MEMORY_RANGE OriginalVariableMtrr[ARRAY_SIZE (MtrrSetting->= Variables.Mtrr)]; + MTRR_MEMORY_RANGE WorkingVariableMtrr[ARRAY_SIZE (MtrrSetting->V= ariables.Mtrr)]; + BOOLEAN VariableSettingModified[ARRAY_SIZE (MtrrSettin= g->Variables.Mtrr)]; + + BOOLEAN FixedSettingsModified[ARRAY_SIZE (mMtrrLibFixe= dMtrrTable)]; + MTRR_FIXED_SETTINGS WorkingFixedSettings; + + MTRR_CONTEXT MtrrContext; + BOOLEAN MtrrContextValid; + + MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask); =20 // - // Force [0, 1M) to UC, so that it doesn't impact left subtraction algor= ithm. + // TRUE indicating the accordingly Variable setting needs modificaiton i= n OriginalVariableMtrr. // - Status =3D MtrrLibSetMemoryType (Ranges, 2 * FirmwareVariableMtrrCount += 2, &RangeCount, 0, SIZE_1MB, CacheUncacheable); - ASSERT (Status =3D=3D RETURN_SUCCESS); + SetMem (VariableSettingModified, ARRAY_SIZE (VariableSettingModified), F= ALSE); // - // Apply Type to [BaseAddress, BaseAddress + Length) + // TRUE indicating the accordingly Fixed setting needs modification in W= orkingFixedSettings. // - Status =3D MtrrLibSetMemoryType (Ranges, 2 * FirmwareVariableMtrrCount += 2, &RangeCount, BaseAddress, Length, Type); - if (RETURN_ERROR (Status)) { - return Status; - } + SetMem (FixedSettingsModified, ARRAY_SIZE (FixedSettingsModified), FALSE= ); + + // + // TRUE indicating the caller requests to set variable MTRRs. + // + Above1MbExist =3D FALSE; + OriginalVariableMtrrCount =3D 0; =20 - Alignment0 =3D LShiftU64 (1, (UINTN) HighBitSet64 (MtrrValidBitsMask)); - WorkingVariableMtrrCount =3D 0; - ZeroMem (&WorkingVariableMtrr, sizeof (WorkingVariableMtrr)); + // + // 1. Validate the parameters. + // for (Index =3D 0; Index < RangeCount; Index++) { - if (Ranges[Index].Type !=3D DefaultType) { - // - // Maximum allowed MTRR count is (FirmwareVariableMtrrCount + 1) - // Because potentially the range [0, 1MB) is not merged, but can be = ignored because fixed MTRR covers that - // - Status =3D MtrrLibSetMemoryAttributeInVariableMtrr ( - Ranges, RangeCount, - WorkingVariableMtrr, FirmwareVariableMtrrCount + 1, &WorkingVariab= leMtrrCount, - Ranges[Index].BaseAddress, Ranges[Index].Length, - Ranges[Index].Type, Alignment0 - ); - if (RETURN_ERROR (Status)) { - return Status; - } + if (Ranges[Index].Length =3D=3D 0) { + return RETURN_INVALID_PARAMETER; + } + if (((Ranges[Index].BaseAddress & ~MtrrValidAddressMask) !=3D 0) || + ((Ranges[Index].Length & ~MtrrValidAddressMask) !=3D 0) + ) { + return RETURN_UNSUPPORTED; + } + if ((Ranges[Index].Type !=3D CacheUncacheable) && + (Ranges[Index].Type !=3D CacheWriteCombining) && + (Ranges[Index].Type !=3D CacheWriteThrough) && + (Ranges[Index].Type !=3D CacheWriteProtected) && + (Ranges[Index].Type !=3D CacheWriteBack)) { + return RETURN_INVALID_PARAMETER; + } + if (Ranges[Index].BaseAddress + Ranges[Index].Length > BASE_1MB) { + Above1MbExist =3D TRUE; } } =20 // - // Remove the [0, 1MB) MTRR if it still exists (not merged with other ra= nge) + // 2. Apply the above-1MB memory attribute settings. // - if (WorkingVariableMtrr[0].BaseAddress =3D=3D 0 && WorkingVariableMtrr[0= ].Length =3D=3D SIZE_1MB) { - ASSERT (WorkingVariableMtrr[0].Type =3D=3D CacheUncacheable); - WorkingVariableMtrrCount--; - CopyMem (&WorkingVariableMtrr[0], &WorkingVariableMtrr[1], WorkingVari= ableMtrrCount * sizeof (VARIABLE_MTRR)); - } + if (Above1MbExist) { + // + // 2.1. Read all variable MTRRs and convert to Ranges. + // + OriginalVariableMtrrCount =3D GetVariableMtrrCountWorker (); + MtrrGetVariableMtrrWorker (MtrrSetting, OriginalVariableMtrrCount, &Va= riableSettings); + MtrrLibGetRawVariableRanges ( + &VariableSettings, OriginalVariableMtrrCount, + MtrrValidBitsMask, MtrrValidAddressMask, OriginalVariableMtrr + ); =20 - if (WorkingVariableMtrrCount > FirmwareVariableMtrrCount) { - return RETURN_OUT_OF_RESOURCES; - } + DefaultType =3D MtrrGetDefaultMemoryTypeWorker (MtrrSetting); + WorkingRangeCount =3D 1; + WorkingRanges[0].BaseAddress =3D 0; + WorkingRanges[0].Length =3D MtrrValidBitsMask + 1; + WorkingRanges[0].Type =3D DefaultType; =20 - for (Index =3D 0; Index < OriginalVariableMtrrCount; Index++) { - VariableSettingModified[Index] =3D FALSE; + Status =3D MtrrLibApplyVariableMtrrs ( + OriginalVariableMtrr, OriginalVariableMtrrCount, + WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCou= nt); + ASSERT_RETURN_ERROR (Status); =20 - if (!OriginalVariableMtrr[Index].Valid) { - continue; - } - for (WorkingIndex =3D 0; WorkingIndex < WorkingVariableMtrrCount; Work= ingIndex++) { - if (OriginalVariableMtrr[Index].BaseAddress =3D=3D WorkingVariableMt= rr[WorkingIndex].BaseAddress && - OriginalVariableMtrr[Index].Length =3D=3D WorkingVariableMtrr[Wo= rkingIndex].Length && - OriginalVariableMtrr[Index].Type =3D=3D WorkingVariableMtrr[Work= ingIndex].Type) { - break; - } - } + ASSERT (OriginalVariableMtrrCount >=3D PcdGet32 (PcdCpuNumberOfReserve= dVariableMtrrs)); + FirmwareVariableMtrrCount =3D OriginalVariableMtrrCount - PcdGet32 (Pc= dCpuNumberOfReservedVariableMtrrs); + ASSERT (WorkingRangeCount <=3D 2 * FirmwareVariableMtrrCount + 1); =20 - if (WorkingIndex =3D=3D WorkingVariableMtrrCount) { - // - // Remove the one from OriginalVariableMtrr which is not in WorkingV= ariableMtrr - // - OriginalVariableMtrr[Index].Valid =3D FALSE; - VariableSettingModified[Index] =3D TRUE; - } else { - // - // Remove the one from WorkingVariableMtrr which is also in Original= VariableMtrr - // - WorkingVariableMtrr[WorkingIndex].Valid =3D FALSE; - } // - // The above two operations cause that valid MTRR only exists in eithe= r OriginalVariableMtrr or WorkingVariableMtrr. + // 2.2. Force [0, 1M) to UC, so that it doesn't impact subtraction alg= orithm. // - } + Status =3D MtrrLibSetMemoryType ( + WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCou= nt, + 0, SIZE_1MB, CacheUncacheable + ); + ASSERT (Status !=3D RETURN_OUT_OF_RESOURCES); =20 - // - // Merge remaining MTRRs from WorkingVariableMtrr to OriginalVariableMtrr - // - for (FreeVariableMtrrCount =3D 0, WorkingIndex =3D 0, Index =3D 0; Index= < OriginalVariableMtrrCount; Index++) { - if (!OriginalVariableMtrr[Index].Valid) { - for (; WorkingIndex < WorkingVariableMtrrCount; WorkingIndex++) { - if (WorkingVariableMtrr[WorkingIndex].Valid) { - break; + // + // 2.3. Apply the new memory attribute settings to Ranges. + // + Modified =3D FALSE; + for (Index =3D 0; Index < RangeCount; Index++) { + BaseAddress =3D Ranges[Index].BaseAddress; + Length =3D Ranges[Index].Length; + if (BaseAddress < BASE_1MB) { + if (Length <=3D BASE_1MB - BaseAddress) { + continue; } + Length -=3D BASE_1MB - BaseAddress; + BaseAddress =3D BASE_1MB; } - if (WorkingIndex =3D=3D WorkingVariableMtrrCount) { - FreeVariableMtrrCount++; + Status =3D MtrrLibSetMemoryType ( + WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeC= ount, + BaseAddress, Length, Ranges[Index].Type + ); + if (Status =3D=3D RETURN_ALREADY_STARTED) { + Status =3D RETURN_SUCCESS; + } else if (Status =3D=3D RETURN_OUT_OF_RESOURCES) { + return Status; } else { - CopyMem (&OriginalVariableMtrr[Index], &WorkingVariableMtrr[Workin= gIndex], sizeof (VARIABLE_MTRR)); - VariableSettingModified[Index] =3D TRUE; - WorkingIndex++; + ASSERT_RETURN_ERROR (Status); + Modified =3D TRUE; } } - } - ASSERT (OriginalVariableMtrrCount - FreeVariableMtrrCount <=3D FirmwareV= ariableMtrrCount); =20 - // - // Move MTRRs after the FirmwareVariableMtrrCount position to beginning - // - if (FirmwareVariableMtrrCount < OriginalVariableMtrrCount) { - WorkingIndex =3D FirmwareVariableMtrrCount; - for (Index =3D 0; Index < FirmwareVariableMtrrCount; Index++) { - if (!OriginalVariableMtrr[Index].Valid) { - // - // Found an empty MTRR in WorkingIndex position - // - for (; WorkingIndex < OriginalVariableMtrrCount; WorkingIndex++) { - if (OriginalVariableMtrr[WorkingIndex].Valid) { - break; - } - } + if (Modified) { + // + // 2.4. Calculate the Variable MTRR settings based on the Ranges. + // Buffer Too Small may be returned if the scratch buffer size = is insufficient. + // + Status =3D MtrrLibSetMemoryRanges ( + DefaultType, LShiftU64 (1, (UINTN)HighBitSet64 (MtrrValid= BitsMask)), WorkingRanges, WorkingRangeCount, + Scratch, ScratchSize, + WorkingVariableMtrr, FirmwareVariableMtrrCount + 1, &Work= ingVariableMtrrCount + ); + if (RETURN_ERROR (Status)) { + return Status; + } =20 - if (WorkingIndex !=3D OriginalVariableMtrrCount) { - CopyMem (&OriginalVariableMtrr[Index], &OriginalVariableMtrr[Wor= kingIndex], sizeof (VARIABLE_MTRR)); - VariableSettingModified[Index] =3D TRUE; - VariableSettingModified[WorkingIndex] =3D TRUE; - OriginalVariableMtrr[WorkingIndex].Valid =3D FALSE; + // + // 2.5. Remove the [0, 1MB) MTRR if it still exists (not merged with= other range) + // + for (Index =3D 0; Index < WorkingVariableMtrrCount; Index++) { + if (WorkingVariableMtrr[Index].BaseAddress =3D=3D 0 && WorkingVari= ableMtrr[Index].Length =3D=3D SIZE_1MB) { + ASSERT (WorkingVariableMtrr[Index].Type =3D=3D CacheUncacheable); + WorkingVariableMtrrCount--; + CopyMem ( + &WorkingVariableMtrr[Index], &WorkingVariableMtrr[Index + 1], + (WorkingVariableMtrrCount - Index) * sizeof (WorkingVariableMt= rr[0]) + ); + break; } } + + if (WorkingVariableMtrrCount > FirmwareVariableMtrrCount) { + return RETURN_OUT_OF_RESOURCES; + } + + // + // 2.6. Merge the WorkingVariableMtrr to OriginalVariableMtrr + // Make sure least modification is made to OriginalVariableMtrr. + // + MtrrLibMergeVariableMtrr ( + OriginalVariableMtrr, OriginalVariableMtrrCount, + WorkingVariableMtrr, WorkingVariableMtrrCount, + VariableSettingModified + ); } } =20 // - // Convert OriginalVariableMtrr to VariableSettings - // NOTE: MTRR from FirmwareVariableMtrr to OriginalVariableMtrr need to = update as well. + // 3. Apply the below-1MB memory attribute settings. // - for (Index =3D 0; Index < OriginalVariableMtrrCount; Index++) { - if (VariableSettingModified[Index]) { - if (OriginalVariableMtrr[Index].Valid) { - VariableSettings->Mtrr[Index].Base =3D (OriginalVariableMtrr[Index= ].BaseAddress & MtrrValidAddressMask) | (UINT8) OriginalVariableMtrr[Index]= .Type; - VariableSettings->Mtrr[Index].Mask =3D ((~(OriginalVariableMtrr[In= dex].Length - 1)) & MtrrValidAddressMask) | BIT11; - } else { - VariableSettings->Mtrr[Index].Base =3D 0; - VariableSettings->Mtrr[Index].Mask =3D 0; - } + for (Index =3D 0; Index < RangeCount; Index++) { + if (Ranges[Index].BaseAddress >=3D BASE_1MB) { + continue; } - } =20 -Done: - if (MtrrSetting !=3D NULL) { - ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *) &MtrrSetting->MtrrDefType)->Bits.= E =3D 1; - return RETURN_SUCCESS; + Status =3D MtrrLibSetBelow1MBMemoryAttribute ( + &WorkingFixedSettings, FixedSettingsModified, + Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Ind= ex].Type + ); + if (RETURN_ERROR (Status)) { + return Status; + } } =20 MtrrContextValid =3D FALSE; // - // Write fixed MTRRs that have been modified + // 4. Write fixed MTRRs that have been modified // - for (Index =3D 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) { + for (Index =3D 0; Index < ARRAY_SIZE (FixedSettingsModified); Index++) { if (FixedSettingsModified[Index]) { - if (!MtrrContextValid) { - MtrrLibPreMtrrChange (&MtrrContext); - MtrrContextValid =3D TRUE; - } - AsmWriteMsr64 ( - mMtrrLibFixedMtrrTable[Index].Msr, - WorkingFixedSettings.Mtrr[Index] + if (MtrrSetting !=3D NULL) { + MtrrSetting->Fixed.Mtrr[Index] =3D WorkingFixedSettings.Mtrr[Index= ]; + } else { + if (!MtrrContextValid) { + MtrrLibPreMtrrChange (&MtrrContext); + MtrrContextValid =3D TRUE; + } + AsmWriteMsr64 ( + mMtrrLibFixedMtrrTable[Index].Msr, + WorkingFixedSettings.Mtrr[Index] ); + } } } =20 // - // Write variable MTRRs - // When only fixed MTRRs were changed, below loop doesn't run - // because OriginalVariableMtrrCount equals to 0. + // 5. Write variable MTRRs that have been modified // for (Index =3D 0; Index < OriginalVariableMtrrCount; Index++) { if (VariableSettingModified[Index]) { - if (!MtrrContextValid) { - MtrrLibPreMtrrChange (&MtrrContext); - MtrrContextValid =3D TRUE; + if (OriginalVariableMtrr[Index].Length !=3D 0) { + VariableSetting.Base =3D (OriginalVariableMtrr[Index].BaseAddress = & MtrrValidAddressMask) + | (UINT8)OriginalVariableMtrr[Index].Type; + VariableSetting.Mask =3D ((~(OriginalVariableMtrr[Index].Length - = 1)) & MtrrValidAddressMask) | BIT11; + } else { + VariableSetting.Base =3D 0; + VariableSetting.Mask =3D 0; + } + if (MtrrSetting !=3D NULL) { + CopyMem (&MtrrSetting->Variables.Mtrr[Index], &VariableSetting, si= zeof (VariableSetting)); + } else { + if (!MtrrContextValid) { + MtrrLibPreMtrrChange (&MtrrContext); + MtrrContextValid =3D TRUE; + } + AsmWriteMsr64 ( + MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), + VariableSetting.Base + ); + AsmWriteMsr64 ( + MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), + VariableSetting.Mask + ); } - AsmWriteMsr64 ( - MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), - VariableSettings->Mtrr[Index].Base - ); - AsmWriteMsr64 ( - MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), - VariableSettings->Mtrr[Index].Mask - ); } } - if (MtrrContextValid) { - MtrrLibPostMtrrChange (&MtrrContext); + + if (MtrrSetting !=3D NULL) { + ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.E= =3D 1; + ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.F= E =3D 1; + } else { + if (MtrrContextValid) { + MtrrLibPostMtrrChange (&MtrrContext); + } } =20 return RETURN_SUCCESS; } =20 /** - This function attempts to set the attributes for a memory range. + This function attempts to set the attributes into MTRR setting buffer fo= r a memory range. =20 - @param[in] BaseAddress The physical address that is the start - address of a memory range. - @param[in] Length The size in bytes of the memory range. - @param[in] Attributes The bit mask of attributes to set for the - memory range. + @param[in, out] MtrrSetting MTRR setting buffer to be set. + @param[in] BaseAddress The physical address that is the start add= ress + of a memory range. + @param[in] Length The size in bytes of the memory range. + @param[in] Attribute The bit mask of attributes to set for the + memory range. =20 - @retval RETURN_SUCCESS The attributes were set for the memory - range. + @retval RETURN_SUCCESS The attributes were set for the memory= range. @retval RETURN_INVALID_PARAMETER Length is zero. - @retval RETURN_UNSUPPORTED The processor does not support one or - more bytes of the memory resource range - specified by BaseAddress and Length. - @retval RETURN_UNSUPPORTED The bit mask of attributes is not supp= ort - for the memory resource range specified - by BaseAddress and Length. - @retval RETURN_ACCESS_DENIED The attributes for the memory resource - range specified by BaseAddress and Len= gth - cannot be modified. - @retval RETURN_OUT_OF_RESOURCES There are not enough system resources = to - modify the attributes of the memory - resource range. - + @retval RETURN_UNSUPPORTED The processor does not support one or = more bytes of the + memory resource range specified by Bas= eAddress and Length. + @retval RETURN_UNSUPPORTED The bit mask of attributes is not supp= ort for the memory resource + range specified by BaseAddress and Len= gth. + @retval RETURN_ACCESS_DENIED The attributes for the memory resource= range specified by + BaseAddress and Length cannot be modif= ied. + @retval RETURN_OUT_OF_RESOURCES There are not enough system resources = to modify the attributes of + the memory resource range. + @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MT= RR calculation. **/ RETURN_STATUS EFIAPI -MtrrSetMemoryAttribute ( +MtrrSetMemoryAttributeInMtrrSettings ( + IN OUT MTRR_SETTINGS *MtrrSetting, IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN MTRR_MEMORY_CACHE_TYPE Attribute ) { RETURN_STATUS Status; + UINT8 Scratch[SCRATCH_BUFFER_SIZE]; + UINTN ScratchSize; + MTRR_MEMORY_RANGE Range; =20 if (!IsMtrrSupported ()) { return RETURN_UNSUPPORTED; } =20 - Status =3D MtrrSetMemoryAttributeWorker (NULL, BaseAddress, Length, Attr= ibute); - DEBUG ((DEBUG_CACHE, "MtrrSetMemoryAttribute() %a: [%016lx, %016lx) - %r= \n", + Range.BaseAddress =3D BaseAddress; + Range.Length =3D Length; + Range.Type =3D Attribute; + ScratchSize =3D sizeof (Scratch); + Status =3D MtrrSetMemoryAttributesInMtrrSettings (MtrrSetting, Scratch, = &ScratchSize, &Range, 1); + DEBUG ((DEBUG_CACHE, "MtrrSetMemoryAttribute(MtrrSettings =3D %p) %s: [%= 016lx, %016lx) - %x\n", + MtrrSetting, mMtrrMemoryCacheTypeShortName[Attribute], BaseAddress, BaseAddre= ss + Length, Status)); =20 if (!RETURN_ERROR (Status)) { - MtrrDebugPrintAllMtrrsWorker (NULL); + MtrrDebugPrintAllMtrrsWorker (MtrrSetting); } return Status; } =20 /** - This function attempts to set the attributes into MTRR setting buffer fo= r a memory range. + This function attempts to set the attributes for a memory range. =20 - @param[in, out] MtrrSetting MTRR setting buffer to be set. - @param[in] BaseAddress The physical address that is the start add= ress - of a memory range. - @param[in] Length The size in bytes of the memory range. - @param[in] Attribute The bit mask of attributes to set for the - memory range. + @param[in] BaseAddress The physical address that is the start + address of a memory range. + @param[in] Length The size in bytes of the memory range. + @param[in] Attributes The bit mask of attributes to set for the + memory range. =20 - @retval RETURN_SUCCESS The attributes were set for the memory= range. + @retval RETURN_SUCCESS The attributes were set for the memory + range. @retval RETURN_INVALID_PARAMETER Length is zero. - @retval RETURN_UNSUPPORTED The processor does not support one or = more bytes of the - memory resource range specified by Bas= eAddress and Length. - @retval RETURN_UNSUPPORTED The bit mask of attributes is not supp= ort for the memory resource - range specified by BaseAddress and Len= gth. - @retval RETURN_ACCESS_DENIED The attributes for the memory resource= range specified by - BaseAddress and Length cannot be modif= ied. - @retval RETURN_OUT_OF_RESOURCES There are not enough system resources = to modify the attributes of - the memory resource range. - + @retval RETURN_UNSUPPORTED The processor does not support one or + more bytes of the memory resource range + specified by BaseAddress and Length. + @retval RETURN_UNSUPPORTED The bit mask of attributes is not supp= ort + for the memory resource range specified + by BaseAddress and Length. + @retval RETURN_ACCESS_DENIED The attributes for the memory resource + range specified by BaseAddress and Len= gth + cannot be modified. + @retval RETURN_OUT_OF_RESOURCES There are not enough system resources = to + modify the attributes of the memory + resource range. + @retval RETURN_BUFFER_TOO_SMALL The scratch buffer is too small for MT= RR calculation. **/ RETURN_STATUS EFIAPI -MtrrSetMemoryAttributeInMtrrSettings ( - IN OUT MTRR_SETTINGS *MtrrSetting, +MtrrSetMemoryAttribute ( IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN MTRR_MEMORY_CACHE_TYPE Attribute ) { - RETURN_STATUS Status; - Status =3D MtrrSetMemoryAttributeWorker (MtrrSetting, BaseAddress, Lengt= h, Attribute); - DEBUG((DEBUG_CACHE, "MtrrSetMemoryAttributeMtrrSettings(%p) %a: [%016lx,= %016lx) - %r\n", - MtrrSetting, mMtrrMemoryCacheTypeShortName[Attribute], BaseAddres= s, BaseAddress + Length, Status)); - - if (!RETURN_ERROR (Status)) { - MtrrDebugPrintAllMtrrsWorker (MtrrSetting); - } - - return Status; + return MtrrSetMemoryAttributeInMtrrSettings (NULL, BaseAddress, Length, = Attribute); } =20 /** @@ -2233,7 +2537,7 @@ MtrrSetVariableMtrrWorker ( UINT32 VariableMtrrCount; =20 VariableMtrrCount =3D GetVariableMtrrCountWorker (); - ASSERT (VariableMtrrCount <=3D MTRR_NUMBER_OF_VARIABLE_MTRR); + ASSERT (VariableMtrrCount <=3D ARRAY_SIZE (VariableSettings->Mtrr)); =20 for (Index =3D 0; Index < VariableMtrrCount; Index++) { AsmWriteMsr64 ( @@ -2447,3 +2751,108 @@ IsMtrrSupported ( return TRUE; } =20 + +/** + Worker function prints all MTRRs for debugging. + + If MtrrSetting is not NULL, print MTRR settings from input MTRR + settings buffer. + If MtrrSetting is NULL, print MTRR settings from MTRRs. + + @param MtrrSetting A buffer holding all MTRRs content. +**/ +VOID +MtrrDebugPrintAllMtrrsWorker ( + IN MTRR_SETTINGS *MtrrSetting + ) +{ + DEBUG_CODE ( + MTRR_SETTINGS LocalMtrrs; + MTRR_SETTINGS *Mtrrs; + UINTN Index; + UINTN RangeCount; + UINT64 MtrrValidBitsMask; + UINT64 MtrrValidAddressMask; + MTRR_MEMORY_RANGE Ranges[ + ARRAY_SIZE (mMtrrLibFixedMtrrTable) * sizeof (UINT64) + 2 * ARRAY_SI= ZE (Mtrrs->Variables.Mtrr) + 1 + ]; + MTRR_MEMORY_RANGE RawVariableRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)= ]; + + if (!IsMtrrSupported ()) { + return; + } + + if (MtrrSetting !=3D NULL) { + Mtrrs =3D MtrrSetting; + } else { + MtrrGetAllMtrrs (&LocalMtrrs); + Mtrrs =3D &LocalMtrrs; + } + + // + // Dump RAW MTRR contents + // + DEBUG((DEBUG_CACHE, "MTRR Settings\n")); + DEBUG((DEBUG_CACHE, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n")); + DEBUG((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType)= ); + for (Index =3D 0; Index < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Index++= ) { + DEBUG((DEBUG_CACHE, "Fixed MTRR[%02d] : %016lx\n", Index, Mtrrs->F= ixed.Mtrr[Index])); + } + + for (Index =3D 0; Index < ARRAY_SIZE (Mtrrs->Variables.Mtrr); Index++)= { + if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) =3D=3D 0) { + // + // If mask is not valid, then do not display range + // + continue; + } + DEBUG ((DEBUG_CACHE, "Variable MTRR[%02d]: Base=3D%016lx Mask=3D%016= lx\n", + Index, + Mtrrs->Variables.Mtrr[Index].Base, + Mtrrs->Variables.Mtrr[Index].Mask + )); + } + DEBUG((DEBUG_CACHE, "\n")); + + // + // Dump MTRR setting in ranges + // + DEBUG((DEBUG_CACHE, "MTRR Ranges\n")); + DEBUG((DEBUG_CACHE, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n")); + MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask); + Ranges[0].BaseAddress =3D 0; + Ranges[0].Length =3D MtrrValidBitsMask + 1; + Ranges[0].Type =3D MtrrGetDefaultMemoryTypeWorker (Mtrrs); + RangeCount =3D 1; + + MtrrLibGetRawVariableRanges ( + &Mtrrs->Variables, ARRAY_SIZE (Mtrrs->Variables.Mtrr), + MtrrValidBitsMask, MtrrValidAddressMask, RawVariableRanges + ); + MtrrLibApplyVariableMtrrs ( + RawVariableRanges, ARRAY_SIZE (RawVariableRanges), + Ranges, ARRAY_SIZE (Ranges), &RangeCount + ); + + MtrrLibApplyFixedMtrrs (&Mtrrs->Fixed, Ranges, ARRAY_SIZE (Ranges), &R= angeCount); + + for (Index =3D 0; Index < RangeCount; Index++) { + DEBUG ((DEBUG_CACHE, "%a:%016lx-%016lx\n", + mMtrrMemoryCacheTypeShortName[Ranges[Index].Type], + Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Inde= x].Length - 1 + )); + } + ); +} + +/** + This function prints all MTRRs for debugging. +**/ +VOID +EFIAPI +MtrrDebugPrintAllMtrrs ( + VOID + ) +{ + MtrrDebugPrintAllMtrrsWorker (NULL); +} --=20 2.12.2.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed Dec 25 13:00:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507798107612671.4804510584618; Thu, 12 Oct 2017 01:48:27 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5E96421F38832; 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d="scan'208";a="909212144" From: Ruiyu Ni To: edk2-devel@lists.01.org Date: Thu, 12 Oct 2017 16:48:10 +0800 Message-Id: <20171012084810.148196-5-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.12.2.windows.2 In-Reply-To: <20171012084810.148196-1-ruiyu.ni@intel.com> References: <20171012084810.148196-1-ruiyu.ni@intel.com> Subject: [edk2] [PATCH 4/4] UefiCpuPkg/MtrrLib: Skip Base MSR access when the pair is invalid X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael D Kinney MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The patch optimized the MTRR access code to skip the Base MSR access when the Mask MSR indicates the pair is invalid. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Michael D Kinney --- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/Mtrr= Lib/MtrrLib.c index a7adbafae3..2fd1d0153e 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -449,10 +449,13 @@ MtrrGetVariableMtrrWorker ( =20 for (Index =3D 0; Index < VariableMtrrCount; Index++) { if (MtrrSetting =3D=3D NULL) { - VariableSettings->Mtrr[Index].Base =3D - AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1)); - VariableSettings->Mtrr[Index].Mask =3D - AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1)); + VariableSettings->Mtrr[Index].Mask =3D AsmReadMsr64 (MSR_IA32_MTRR_P= HYSMASK0 + (Index << 1)); + // + // Skip to read the Base MSR when the Mask.V is not set. + // + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Inde= x].Mask)->Bits.V !=3D 0) { + VariableSettings->Mtrr[Index].Base =3D AsmReadMsr64 (MSR_IA32_MTRR= _PHYSBASE0 + (Index << 1)); + } } else { VariableSettings->Mtrr[Index].Base =3D MtrrSetting->Variables.Mtrr[I= ndex].Base; VariableSettings->Mtrr[Index].Mask =3D MtrrSetting->Variables.Mtrr[I= ndex].Mask; @@ -2540,14 +2543,14 @@ MtrrSetVariableMtrrWorker ( ASSERT (VariableMtrrCount <=3D ARRAY_SIZE (VariableSettings->Mtrr)); =20 for (Index =3D 0; Index < VariableMtrrCount; Index++) { - AsmWriteMsr64 ( - MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), - VariableSettings->Mtrr[Index].Base - ); - AsmWriteMsr64 ( - MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), - VariableSettings->Mtrr[Index].Mask - ); + // + // Mask MSR is always updated since caller might need to invalidate th= e MSR pair. + // Base MSR is skipped when Mask.V is not set. + // + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSetting= s->Mtrr[Index].Mask); + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index]= .Mask)->Bits.V !=3D 0) { + AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSetti= ngs->Mtrr[Index].Base); + } } } =20 @@ -2800,7 +2803,7 @@ MtrrDebugPrintAllMtrrsWorker ( } =20 for (Index =3D 0; Index < ARRAY_SIZE (Mtrrs->Variables.Mtrr); Index++)= { - if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) =3D=3D 0) { + if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index= ].Mask)->Bits.V =3D=3D 0) { // // If mask is not valid, then do not display range // --=20 2.12.2.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel