Add a description of the SoCs GPIO controller as well as a description
of DIP switch block #3, which is wired to GPIOs 0 - 7, both on the
evaluation board as well as the Developer Box.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 50 ++++++++++++++++++++
Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 12 +++++
Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 50 ++++++++++++++++++++
3 files changed, 112 insertions(+)
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts
index 9e0acd593311..791e690adccd 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts
@@ -19,3 +19,53 @@
model = "Socionext Developer Box";
compatible = "socionext,developer-box", "socionext,synquacer";
};
+
+&gpio {
+ dsw3_1 {
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_2 {
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_3 {
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_4 {
+ gpios = <3 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_5 {
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_6 {
+ gpios = <5 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_7 {
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_8 {
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+};
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index 3aef10294662..0746b7853ebf 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -21,6 +21,9 @@
#define IRQ_TYPE_LEVEL_HIGH 4
#define IRQ_TYPE_LEVEL_LOW 8
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
/ {
#address-cells = <2>;
#size-cells = <2>;
@@ -511,4 +514,13 @@
msi-map = <0x0 &its 0x10000 0x7f00>;
dma-coherent;
};
+
+ gpio: gpio@51000000 {
+ compatible = "socionext,sc2a11-gpio", "fujitsu,mb86s70-gpio";
+ reg = <0x0 0x51000000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&clk_apb>;
+ base = <0>;
+ };
};
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts
index cda72fdf2f99..062c1e5eeeb1 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts
@@ -19,3 +19,53 @@
model = "SynQuacer Evaluation Board";
compatible = "socionext,synquacer-eval-board", "socionext,synquacer";
};
+
+&gpio {
+ dsw3_1 {
+ gpios = <0 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_2 {
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_3 {
+ gpios = <2 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_4 {
+ gpios = <3 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_5 {
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_6 {
+ gpios = <5 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_7 {
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+
+ dsw3_8 {
+ gpios = <7 GPIO_ACTIVE_HIGH>;
+ gpio-hog;
+ input;
+ };
+};
--
2.11.0
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