From nobody Wed Dec 25 14:57:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509447214587289.33507789081887; Tue, 31 Oct 2017 03:53:34 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E45C52035D0EE; Tue, 31 Oct 2017 03:49:14 -0700 (PDT) Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BB2052035D0E1 for ; Tue, 31 Oct 2017 03:49:12 -0700 (PDT) Received: by mail-wm0-x244.google.com with SMTP id b189so21459440wmd.4 for ; Tue, 31 Oct 2017 03:53:04 -0700 (PDT) Received: from localhost.localdomain ([105.129.222.2]) by smtp.gmail.com with ESMTPSA id o14sm460985wra.54.2017.10.31.03.52.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Oct 2017 03:53:01 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BNu1dbxH8Bq88x12++Qaw1ygKYt8Bh6fVW2AKnE6PZg=; b=gtTWITpCHmHWp2zYmcS8YFw/0hUnNBsUJKhezjD7w+H3XOvqsIbCuLBFfbj4yxV/VI OQD03vj9Wwc0v7hzyojbjUpmBP+XA1ZHXpdpwbMBbjsZmLqKoyyCOfCRFcA+dpG6kQRu /2EcyIiWN4ZU1HoI2PTmwvmkrHAXiyWObjJlo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BNu1dbxH8Bq88x12++Qaw1ygKYt8Bh6fVW2AKnE6PZg=; b=N5mS54jaUeCfizgA7FdpGvmHPS0ElttMDOeLOookf/daw2jB+jGRDzns8EZaLFJhuu RP5Aqw6J/CuGPsI/BqUNhvcLlQnnXRvXAQ33UkS/kNPHyG3uAETr1sNAZ8Nhjl6ouhUT A1azUaXrZO2IH9lJa9XedGtmfMviR/qJLMQ0XPGrgCkPPSo71m2VGnyFJtnh/+s4Gc5m 2JkNcH1WIbKS7qLE853jK8EKVGr2aMlwxbcz42zP8l1o01IM58KNxYb/3ZVBMpGvIyh4 7n0nri0iG2/r1a0DTcJbM/MVbPD8GAEOs/CkYjpy9PLt8Em9GTp1R4GG5lAA3wH+zTvP zNBw== X-Gm-Message-State: AMCzsaV6p4wkH0vBAhrJ/AQzazD/fu+tSKVe6pc7XwGI7GR0CvMMOGl2 p4YF9siUiZKbmRKs2KRzJwo5LcaA72M= X-Google-Smtp-Source: ABhQp+S+WglPlAaKLMR0WteOPfhv1n8YJ3Gui/aDAQs+sIeykO2Xfbg6ytUHC9UTrSN/zYyAW88pnA== X-Received: by 10.28.225.214 with SMTP id y205mr1618301wmg.12.1509447182545; Tue, 31 Oct 2017 03:53:02 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Tue, 31 Oct 2017 10:52:04 +0000 Message-Id: <20171031105218.30208-14-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171031105218.30208-1-ard.biesheuvel@linaro.org> References: <20171031105218.30208-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 13/27] Silicon/SynQuacer: add device tree support for eval board X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a device tree description of the SynQuacer SoC, and expose it for the SynQuacerEvalBoard platforms. This includes the menu option in the UEFI boot menu to switch between ACPI and DT. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 9 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 12 + Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 514 ++++++= ++++++++++++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 21 + Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf | 33 ++ 5 files changed, 589 insertions(+) diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b= /Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index 02db912562bd..ac90c718d003 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -544,3 +544,12 @@ [Components.common] MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRes= ourceTableDxe.inf + + # + # DT support + # + Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf + EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf { + + DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLib= Default/DxeDtPlatformDtbLoaderLibDefault.inf + } diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf b= /Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf index 2935f19139b6..961482b12e62 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf @@ -1,3 +1,4 @@ + # # Copyright (c) 2013-2014, ARM Limited. All rights reserved. # Copyright (c) 2017, Linaro Limited. All rights reserved. @@ -206,6 +207,12 @@ [FV.FvMain] INF RuleOverride =3D ACPITABLE Silicon/Socionext/SynQuacer/AcpiTables/Ac= piTables.inf INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphic= sResourceTableDxe.inf =20 + # + # DT support + # + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + INF RuleOverride =3D DTB Silicon/Socionext/SynQuacer/DeviceTree/SynQuace= rEvalBoard.inf + [FV.FVMAIN_PEI] FvAlignment =3D 16 ERASE_POLARITY =3D 1 @@ -368,3 +375,8 @@ [Rule.Common.USER_DEFINED.ACPITABLE] RAW ACPI |.acpi RAW ASL |.aml } + +[Rule.Common.USER_DEFINED.DTB] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW BIN |.dtb + } diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silico= n/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi new file mode 100644 index 000000000000..3aef10294662 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -0,0 +1,514 @@ +/** @file + * Copyright (c) 2017, Linaro Limited. All rights reserved. + * + * This program and the accompanying materials are licensed and made + * available under the terms and conditions of the BSD License which + * accompanies this distribution. The full text of the license may be + * found at http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + */ + +#define GIC_SPI 0 +#define GIC_PPI 1 + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RIS= ING) +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + dma-ranges =3D <0x0 0x0 0x0 0x0 0x100 0x0>; + + aliases { + serial0 =3D &soc_uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + CPU0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x0>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x1>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU2: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x100>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU3: cpu@101 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x101>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU4: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x200>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU5: cpu@201 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x201>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU6: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x300>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU7: cpu@301 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x301>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU8: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x400>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU9: cpu@401 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x401>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU10: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x500>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU11: cpu@501 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x501>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU12: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x600>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU13: cpu@601 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x601>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU14: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x700>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU15: cpu@701 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x701>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU16: cpu@800 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x800>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU17: cpu@801 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x801>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU18: cpu@900 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x900>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU19: cpu@901 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0x901>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU20: cpu@a00 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0xa00>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU21: cpu@a01 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0xa01>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU22: cpu@b00 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0xb00>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + CPU23: cpu@b01 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53","arm,armv8"; + reg =3D <0xb01>; + enable-method =3D "psci"; + //cpu-idle-states =3D <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&CPU0>; + }; + core1 { + cpu =3D <&CPU1>; + }; + }; + cluster1 { + core0 { + cpu =3D <&CPU2>; + }; + core1 { + cpu =3D <&CPU3>; + }; + }; + cluster2 { + core0 { + cpu =3D <&CPU4>; + }; + core1 { + cpu =3D <&CPU5>; + }; + }; + cluster3 { + core0 { + cpu =3D <&CPU6>; + }; + core1 { + cpu =3D <&CPU7>; + }; + }; + cluster4 { + core0 { + cpu =3D <&CPU8>; + }; + core1 { + cpu =3D <&CPU9>; + }; + }; + cluster5 { + core0 { + cpu =3D <&CPU10>; + }; + core1 { + cpu =3D <&CPU11>; + }; + }; + cluster6 { + core0 { + cpu =3D <&CPU12>; + }; + core1 { + cpu =3D <&CPU13>; + }; + }; + cluster7 { + core0 { + cpu =3D <&CPU14>; + }; + core1 { + cpu =3D <&CPU15>; + }; + }; + cluster8 { + core0 { + cpu =3D <&CPU16>; + }; + core1 { + cpu =3D <&CPU17>; + }; + }; + cluster9 { + core0 { + cpu =3D <&CPU18>; + }; + core1 { + cpu =3D <&CPU19>; + }; + }; + cluster10 { + core0 { + cpu =3D <&CPU20>; + }; + core1 { + cpu =3D <&CPU21>; + }; + }; + cluster11 { + core0 { + cpu =3D <&CPU22>; + }; + core1 { + cpu =3D <&CPU23>; + }; + }; + }; + }; + + idle-states { + entry-method =3D "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x0010000>; + entry-latency-us =3D <300>; + exit-latency-us =3D <1200>; + min-residency-us =3D <2000>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x1010000>; + entry-latency-us =3D <400>; + exit-latency-us =3D <1200>; + min-residency-us =3D <2500>; + local-timer-stop; + }; + }; + + gic: interrupt-controller@30000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x30000000 0x0 0x10000>, // GICD + <0x0 0x30400000 0x0 0x300000>, // GICR + <0x0 0x2c000000 0x0 0x2000>, // GICC + <0x0 0x2c010000 0x0 0x1000>, // GICH + <0x0 0x2c020000 0x0 0x2000>; // GICV + #interrupt-cells =3D <3>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + interrupt-controller; + interrupts =3D ; + + its: gic-its@30020000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30020000 0x0 0x20000>; + #msi-cells =3D <1>; + msi-controller; + socionext,synquacer-pre-its =3D <0x58000000 0x200000>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , // secure + , // non-secure + , // virtual + ; // HYP + }; + + mmio-timer@2a810000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x2a810000 0x0 0x10000>; + clock-frequency =3D <100000000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + frame@2a830000 { + frame-number =3D <0>; + interrupts =3D ; + reg =3D <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + mailbox: mhu@45000000 { + compatible =3D "arm,mhu", "arm,primecell"; + reg =3D <0x0 0x45000000 0x0 0x1000>; + interrupts =3D , + ; /* Non-Sec */ + interrupt-names =3D "mhu_lpri_rx", "mhu_hpri_rx"; + #mbox-cells =3D <1>; + clocks =3D <&clk_apb>; + clock-names =3D "apb_pclk"; + }; + + sram: sram@45200000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x45200000 0x0 0x200>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x0 0x45200000 0x200>; + + cpu_scp_hpri: scp-shmem@0 { + reg =3D <0x0 0x200>; + }; + }; + + scpi { + compatible =3D "arm,scpi"; + mboxes =3D <&mailbox 1>; + shmem =3D <&cpu_scp_hpri>; + }; + + clk_uart: refclk62500khz { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <62500000>; + clock-output-names =3D "uartclk"; + }; + + clk_apb: refclk100mhz { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + clock-output-names =3D "apb_pclk"; + }; + + soc_uart0: uart@2a400000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x2a400000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_uart &clk_apb>; + clock-names =3D "uartclk", "apb_pclk"; + }; + + clk_netsec: refclk125mhz { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + #clock-cells =3D <0>; + }; + + eth0: netsec@522D0000 { + compatible =3D "socionext,synquacer-netsec"; + reg =3D <0 0x522d0000 0x0 0x10000>, + <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; + interrupts =3D ; + clocks =3D <&clk_netsec>; + phy-mode =3D "rgmii"; + max-speed =3D <1000>; + max-frame-size =3D <9000>; + phy-handle =3D <ðphy0>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D ; + }; + }; + + smmu: iommu@582c0000 { + compatible =3D "arm,mmu-500", "arm,smmu-v2"; + reg =3D <0x0 0x582c0000 0x0 0x10000>; + #global-interrupts =3D <1>; + interrupts =3D , + , + ; + #iommu-cells =3D <1>; + status =3D "disabled"; + }; + + pcie0: pcie@60000000 { + compatible =3D "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam= "; + device_type =3D "pci"; + reg =3D <0x0 0x60000000 0x0 0x7f00000>; + bus-range =3D <0x0 0x7e>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x000100= 00>, + <0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000= >, + <0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000= >; + + #interrupt-cells =3D <0x1>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x0>; + interrupt-map =3D <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TY= PE_LEVEL_HIGH>; + + msi-map =3D <0x000 &its 0x0 0x7f00>; + dma-coherent; + }; + + pcie1: pcie@70000000 { + compatible =3D "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam= "; + device_type =3D "pci"; + reg =3D <0x0 0x70000000 0x0 0x7f00000>; + bus-range =3D <0x0 0x7e>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x1000000 0x00 0x00010000 0x00 0x77f00000 0x0 0x000100= 00>, + <0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000= >, + <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000= >; + + #interrupt-cells =3D <0x1>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x0>; + interrupt-map =3D <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TY= PE_LEVEL_HIGH>; + + msi-map =3D <0x0 &its 0x10000 0x7f00>; + dma-coherent; + }; +}; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts = b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts new file mode 100644 index 000000000000..cda72fdf2f99 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts @@ -0,0 +1,21 @@ +/** @file + * Copyright (c) 2017, Linaro Limited. All rights reserved. + * + * This program and the accompanying materials are licensed and made + * available under the terms and conditions of the BSD License which + * accompanies this distribution. The full text of the license may be + * found at http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + */ + +/dts-v1/; + +#include "SynQuacer.dtsi" + +/ { + model =3D "SynQuacer Evaluation Board"; + compatible =3D "socionext,synquacer-eval-board", "socionext,synquacer"; +}; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf = b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf new file mode 100644 index 000000000000..af9a283e67a2 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.inf @@ -0,0 +1,33 @@ +## @file +# +# Device tree description of the SynQuacer platform +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D SynQuacerDeviceTree + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + SynQuacerEvalBoard.dts + +[Packages] + MdePkg/MdePkg.dec + Silicon/Socionext/SynQuacer/SynQuacer.dec + +[FixedPcd] + gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase + gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel