From nobody Wed Jul 9 22:55:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1510323722302683.9198071343097; Fri, 10 Nov 2017 06:22:02 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0AE992035522C; Fri, 10 Nov 2017 06:17:58 -0800 (PST) Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5A9D621B00DC8 for ; Fri, 10 Nov 2017 06:17:56 -0800 (PST) Received: by mail-wr0-x243.google.com with SMTP id k61so8744318wrc.4 for ; Fri, 10 Nov 2017 06:21:59 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id e131sm1036477wmg.15.2017.11.10.06.21.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:21:56 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P/tdm3SiCEkh4UACJCMKTJ86wKzG+V8L7SY7FRldEDc=; b=XtEayIQwzRCNKC+J5ZXdjIzwPr1fkb60fsG+mmfFksH9qA4cdC2brVLTV5rgFOWUoH eG2S89dCjAkt74gUTFxMdy6eJv6ZsJcBOizKNJKbjlYqzQiFFuMIxsVcv90E2ZnKyogR ofFm85qMITRttce3jpm2mdJVGtYZGqYzqWJzo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P/tdm3SiCEkh4UACJCMKTJ86wKzG+V8L7SY7FRldEDc=; b=D7UT6zk8omaMsHdgg3adn3ezoges0W3vVVHbcSPEBxNMuJIjONsnL9S2sVUQWIYrp4 yswYApugO8lpv9BZCFotm6MYDRZRsWyE0qyxCMaxwuKcwz9VhEVgSMGvRlAqVQFlo0uv KxSf//MEA1E5f3p9IVxkkOZX3VjsH8ADkFz0xhcWXh3FV/eeydPiILiEFDtbnpztP+qs PYs/b6mahc0iyrHtLBH40ncc0o5eR7IbsO1VaQfDx7Lnfi5IhThkbFumuSSnGsam/jQf /lzyax8ibPauMcQHje5FOVxKFChDpqtolalkGH4wi1Vvg/PFW2RFs4JfQtil5qD8NZCt RrWQ== X-Gm-Message-State: AJaThX5V9e4gmq1jBoa3HxA9fePEFryibC3vTuMK5QI7vUKLnGxmS2uL uKSxSBHObqIWQFDkp9znLx2h61LzkSc= X-Google-Smtp-Source: AGs4zMbB/JJ/d/BfJzJzH+TaM9Z9MUym6He4qbnnpzLD3AXdSzsx0qyMj6IMwFutYWqh7kqecSkHew== X-Received: by 10.223.156.138 with SMTP id d10mr474791wre.214.1510323717398; Fri, 10 Nov 2017 06:21:57 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, daniel.thompson@linaro.org Date: Fri, 10 Nov 2017 14:20:56 +0000 Message-Id: <20171110142127.12018-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171110142127.12018-1-ard.biesheuvel@linaro.org> References: <20171110142127.12018-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 03/34] Silicon/Socionext: add PlatformPeilib implementation for SynQuacer X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Create a specialized PlatformPeiLib implementation that invokes the platform specific firmware interface (currently, just a data structure left in SRAM) to set the ARM standard PcdSystemMemoryBase|Size PCDs, and expose the information via a newly added DramInfo PPI. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- v4: remove code to copy the compressed FV to DRAM, this is no longer necess= ary now that we have figured out how to map the NOR flash cacheable Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h = | 30 +++++ Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h = | 64 ++++++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatf= ormPeiLib.c | 123 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatf= ormPeiLib.inf | 50 ++++++++ Silicon/Socionext/SynQuacer/SynQuacer.dec = | 9 ++ 5 files changed, 276 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h b/Sili= con/Socionext/SynQuacer/Include/Platform/DramInfo.h new file mode 100644 index 000000000000..f7691bdade4a --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/DramInfo.h @@ -0,0 +1,30 @@ +/** @file + Data structure for passing DRAM information from lower level firmware + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_PLATFORM_DRAM_INFO_H_ +#define _SYNQUACER_PLATFORM_DRAM_INFO_H_ + +typedef struct { + UINT64 Base; + UINT64 Size; +} DRAM_INFO_ENTRY; + +typedef struct { + UINT32 NumRegions; + UINT32 Reserved; + DRAM_INFO_ENTRY Entry[3]; +} DRAM_INFO; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h b/Silicon/S= ocionext/SynQuacer/Include/Ppi/DramInfo.h new file mode 100644 index 000000000000..6453e121317d --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Ppi/DramInfo.h @@ -0,0 +1,64 @@ +/** @file + DRAM info PPI to retrieve DRAM information from lower level firmware + + Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYNQUACER_DRAMINFO_PPI_ +#define _SYNQUACER_DRAMINFO_PPI_ + +#define SYNQUACER_DRAMINFO_PPI_GUID \ + { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46, 0xbf, 0x89, 0x1c, 0x86, 0x46= , 0xcc } } + +/** + Retrieve the number of discontiguous DRAM regions + + @param[out] RegionCount The number of available DRAM regions + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER RegionCount =3D=3D NULL + +**/ +typedef +EFI_STATUS +(EFIAPI * DRAMINFO_GET_REGION_COUNT) ( + OUT UINTN *RegionCount + ); + +/** + Retrieve the base and size of a DRAM region + + @param[in] RegionIndex The 0-based index of the region to retrieve + @param[out] Base The base of the requested region + @param[out] Size The size of the requested region + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER Base =3D=3D NULL or Size =3D=3D NULL + @retval EFI_NOT_FOUND No region exists with index >=3D RegionInd= ex + +**/ +typedef +EFI_STATUS +(EFIAPI * DRAMINFO_GET_REGION) ( + IN UINTN RegionIndex, + OUT UINT64 *Base, + OUT UINT64 *Size + ); + +typedef struct { + DRAMINFO_GET_REGION_COUNT GetRegionCount; + DRAMINFO_GET_REGION GetRegion; +} SYNQUACER_DRAM_INFO_PPI; + +extern EFI_GUID gSynQuacerDramInfoPpiGuid; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/Sy= nQuacerPlatformPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlat= formPeiLib/SynQuacerPlatformPeiLib.c new file mode 100644 index 000000000000..358dd5a91f08 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacer= PlatformPeiLib.c @@ -0,0 +1,123 @@ +/** @file +* +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +STATIC +CONST DRAM_INFO *mDramInfo =3D (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBa= se); + +/** + Retrieve the number of discontiguous DRAM regions + + @param[out] RegionCount The number of available DRAM regions + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER RegionCount =3D=3D NULL + +**/ +STATIC +EFI_STATUS +EFIAPI +GetDramRegionCount ( + OUT UINTN *RegionCount + ) +{ + if (RegionCount =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *RegionCount =3D mDramInfo->NumRegions; + + return EFI_SUCCESS; +} + +/** + Retrieve the base and size of a DRAM region + + @param[in] RegionIndex The 0-based index of the region to retrieve + @param[out] Base The base of the requested region + @param[out] Size The size of the requested region + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_INVALID_PARAMETER Base =3D=3D NULL or Size =3D=3D NULL + @retval EFI_NOT_FOUND No region exists with index >=3D RegionInd= ex + +**/ +STATIC +EFI_STATUS +EFIAPI +GetDramRegion ( + IN UINTN RegionIndex, + OUT UINT64 *Base, + OUT UINT64 *Size + ) +{ + if (Base =3D=3D NULL || Size =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (RegionIndex >=3D mDramInfo->NumRegions) { + return EFI_NOT_FOUND; + } + + *Base =3D mDramInfo->Entry[RegionIndex].Base; + *Size =3D mDramInfo->Entry[RegionIndex].Size; + + return EFI_SUCCESS; +} + +STATIC SYNQUACER_DRAM_INFO_PPI mDramInfoPpi =3D { + GetDramRegionCount, + GetDramRegion +}; + +STATIC CONST EFI_PEI_PPI_DESCRIPTOR mDramInfoPpiDescriptor =3D { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gSynQuacerDramInfoPpiGuid, + &mDramInfoPpi +}; + +EFI_STATUS +EFIAPI +PlatformPeim ( + VOID + ) +{ + EFI_STATUS Status; + + ASSERT (mDramInfo->NumRegions > 0); + + // + // Record the first region into PcdSystemMemoryBase and PcdSystemMemoryS= ize. + // This is the region we will use for UEFI itself. + // + Status =3D PcdSet64S (PcdSystemMemoryBase, mDramInfo->Entry[0].Base); + ASSERT_EFI_ERROR (Status); + + Status =3D PcdSet64S (PcdSystemMemorySize, mDramInfo->Entry[0].Size); + ASSERT_EFI_ERROR (Status); + + BuildFvHob (FixedPcdGet64 (PcdFvBaseAddress), FixedPcdGet32 (PcdFvSize)); + + return PeiServicesInstallPpi (&mDramInfoPpiDescriptor); +} diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/Sy= nQuacerPlatformPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPl= atformPeiLib/SynQuacerPlatformPeiLib.inf new file mode 100644 index 000000000000..70eb715d44e3 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacer= PlatformPeiLib.inf @@ -0,0 +1,50 @@ +#/** @file +# +# Copyright (c) 2017, Linaro, Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SynQuacerPlatformPeiLib + FILE_GUID =3D 86537337-b62b-4dcd-846f-033a6a8355e0 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformPeiLib + +[Sources] + SynQuacerPlatformPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Socionext/SynQuacer/SynQuacer.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + HobLib + MemoryAllocationLib + PcdLib + PeiServicesLib + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdFvSize + gSynQuacerTokenSpaceGuid.PcdDramInfoBase + +[Ppis] + gSynQuacerDramInfoPpiGuid ## PRODUCES + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/= SynQuacer/SynQuacer.dec index c3adf85d3562..1249ce688600 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -18,3 +18,12 @@ [Defines] =20 [Includes] Include + +[Guids] + gSynQuacerTokenSpaceGuid =3D { 0x4d04555b, 0xdfdc, 0x418a, { 0x8a, 0xab,= 0x07, 0xce, 0xef, 0x46, 0x82, 0xbb } } + +[Ppis] + gSynQuacerDramInfoPpiGuid =3D { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46= , 0xbf, 0x89, 0x1c, 0x86, 0x46, 0xcc } } + +[PcdsFixedAtBuild] + gSynQuacerTokenSpaceGuid.PcdDramInfoBase|0|UINT64|0x00000001 --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel