.../BensonGlacier/BoardInitPostMem/BoardGpios.h | 20 ++++++------ .../AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl | 2 ++ .../PlatformSsdt/Sensors/GenericSpi3.asl | 38 ++++++++++++++++++++++ 3 files changed, 50 insertions(+), 10 deletions(-) create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Sensors/GenericSpi3.asl
-Enable generic SPI device for BensonGlacier config to be
used with SenseHat board.
-Enable GPIO config to enable SenseHat board programming
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Teemu Rytkonen <teemu.s.rytkonen@intel.com>
---
.../BensonGlacier/BoardInitPostMem/BoardGpios.h | 20 ++++++------
.../AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl | 2 ++
.../PlatformSsdt/Sensors/GenericSpi3.asl | 38 ++++++++++++++++++++++
3 files changed, 50 insertions(+), 10 deletions(-)
create mode 100644 Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Sensors/GenericSpi3.asl
diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
index d72cd80c9..db48c4e85 100644
--- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
+++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/BoardGpios.h
@@ -80,13 +80,13 @@ BXT_GPIO_PAD_INIT mBenson_GpioInitData_N[] =
BXT_GPIO_PAD_CONF(L"GPIO_14", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0070, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_15", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0078, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_16", M0 , GPI , NA , NA , Edge , Wake_Disabled, P_20K_H, Inverted,IOAPIC, HizRx0I ,DisPuPd, GPIO_PADBAR+0x0080, NORTH),//Feature:SIM Card Detect Net in Sch: SIM_CON_CD1, falling edge trigger
- BXT_GPIO_PAD_CONF(L"GPIO_17", M0 , GPI , GPIO_D, NA , Edge , Wake_Disabled, P_NONE , NA ,IOAPIC, NA ,DisPuPd, GPIO_PADBAR+0x0088, NORTH), // SOC_LSE_HOST_IRQ_N
+ BXT_GPIO_PAD_CONF(L"GPIO_17", M0 , GPI , GPIO_D, NA , Edge , Wake_Disabled, P_NONE , NA ,IOAPIC, NA ,DisPuPd, GPIO_PADBAR+0x0088, NORTH), // SOC_LSE_HOST_IRQ_N
BXT_GPIO_PAD_CONF(L"GPIO_18", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x0090, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_19", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x0098, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_20", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00A0, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_21", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00A8, NORTH),//Feature: LB
BXT_GPIO_PAD_CONF(L"GPIO_22", M0 , GPIO ,GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00B0, NORTH),//Feature: LB
- BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO ,GPIO_D, LO , NA , Wake_Disabled, P_20K_H, NA , NA, NA , EnPu, GPIO_PADBAR+0x00B8, NORTH), // SOC_SUE_RST_N
+ BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO ,GPIO_D, LO , NA , Wake_Disabled, P_20K_H, NA , NA, NA , EnPu, GPIO_PADBAR+0x00B8, NORTH), // SOC_SUE_RST_N
BXT_GPIO_PAD_CONF(L"GPIO_24", M0 , GPO ,GPIO_D , NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA, GPIO_PADBAR+0x00C0, NORTH),//SATA_DEVSLP0
BXT_GPIO_PAD_CONF(L"GPIO_25", M0 , GPO ,GPIO_D , NA , Level , Wake_Disabled, P_20K_H, Inverted, SCI, NA , NA, GPIO_PADBAR+0x00C8, NORTH),//Feature:ODD MD/DA SCI Net in Sch: SATA_ODD_DA_IN
BXT_GPIO_PAD_CONF(L"GPIO_26", M0 , GPIO ,GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA, GPIO_PADBAR+0x00D0, NORTH),//SATA_LEDN
@@ -216,16 +216,16 @@ BXT_GPIO_PAD_INIT mBenson_GpioInitData_NW [] =
BXT_GPIO_PAD_CONF(L"GPIO_106 GP_SSP_0_FS1", M0 , GPI , GPIO_D , NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd, GPIO_PADBAR+0x01F8, NORTHWEST),
BXT_GPIO_PAD_CONF(L"GPIO_109 GP_SSP_0_RXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd, GPIO_PADBAR+0x0200, NORTHWEST),
BXT_GPIO_PAD_CONF(L"GPIO_110 GP_SSP_0_TXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd, GPIO_PADBAR+0x0208, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 , GPI ,GPIO_D, NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on RVP
- BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0218, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0220, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 , GPI ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on RVP
+ BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M0 , GPI ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0218, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M0 , GPO ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0220, NORTHWEST),
BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M2 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0228, NORTHWEST),//Feature: LPSS UART Hdr
BXT_GPIO_PAD_CONF(L"GPIO_117 GP_SSP_1_TXD", M0 , GPIO , GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0230, NORTHWEST),//Feature: LPSS UART Hdr
- BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0238, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0240, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0248, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0250, NORTHWEST),
- BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M0 , GPIO , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0258, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0238, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0240, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0248, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0250, NORTHWEST),
+ BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0258, NORTHWEST),
BXT_GPIO_PAD_CONF(L"GPIO_123 GP_SSP_2_TXD", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0260, NORTHWEST),
BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0020, NORTHWEST),//Feature: DBI_SDA
BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M1 , NA , NA , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA, GPIO_PADBAR+0x0028, NORTHWEST),//Feature: DBI_SCL
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl
index 1f9da7678..bbab6b63a 100644
--- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl
+++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl
@@ -30,6 +30,7 @@ DefinitionBlock (
External(\_SB.PCI0.URT2, DeviceObj)
External(\_SB.PCI0.SDIO, DeviceObj)
External(\_SB.PCI0.SPI1, DeviceObj)
+ External(\_SB.PCI0.SPI3, DeviceObj)
External(\_SB.GPO0.CWLE, IntObj)
External(\_SB.GPO0.AVBL, IntObj)
External(\_SB.PCI0.SDIO.PSTS, IntObj)
@@ -66,5 +67,6 @@ DefinitionBlock (
include ("Fingerprint/Fingerprint_FPC.asl")
include ("SueCreek/SueCreek.asl")
+ include ("Sensors/GenericSpi3.asl")
}
diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Sensors/GenericSpi3.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Sensors/GenericSpi3.asl
new file mode 100644
index 000000000..830765bf3
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt/Sensors/GenericSpi3.asl
@@ -0,0 +1,38 @@
+/** @file
+
+Copyright (c) 2017 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.SPI3) {
+ Device (TP0) {
+ Name (_HID, "SPT0001")
+ Name (_DDN, "Sensor - SPI3, CS0")
+ Name (_CRS, ResourceTemplate () {
+ SpiSerialBus (
+ 0, // Chip select (0, 1, 2)
+ PolarityLow, // Chip select is active low
+ FourWireMode, // Full duplex
+ 8, // Bits per word is 8 (byte)
+ ControllerInitiated, // Don't care
+ 1000000, // 1 MHz
+ ClockPolarityLow, // SPI mode 0
+ ClockPhaseFirst, // SPI mode 0
+ "\\_SB.PCI0.SPI3", // SPI host controller
+ 0 // Must be 0
+ )
+ })
+ Method (_STA, 0x0, NotSerialized) {
+ Return (0xF)
+ }
+ }
+}
+
--
2.14.1.windows.1
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
Reviewed-by: zwei4 <david.wei@intel.com>
Thanks,
David Wei
Intel SSG/STO/UEFI BIOS
> -----Original Message-----
> From: Rytkonen, Teemu S
> Sent: Wednesday, November 15, 2017 1:16 AM
> To: edk2-devel@lists.01.org
> Cc: Ryu, Misun <misun.ryu@intel.com>; Loeppert, Anthony
> <anthony.loeppert@intel.com>; Jones, Mark L <mark.l.jones@intel.com>;
> Wei, David <david.wei@intel.com>; Guo, Mang <mang.guo@intel.com>
> Subject: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017]
> BensonGlacier: Enable generic SPI device
>
> -Enable generic SPI device for BensonGlacier config to be
> used with SenseHat board.
> -Enable GPIO config to enable SenseHat board programming
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Teemu Rytkonen <teemu.s.rytkonen@intel.com>
> ---
> .../BensonGlacier/BoardInitPostMem/BoardGpios.h | 20 ++++++------
> .../AcpiTablesPCAT/PlatformSsdt/PlatformSsdt.asl | 2 ++
> .../PlatformSsdt/Sensors/GenericSpi3.asl | 38
> ++++++++++++++++++++++
> 3 files changed, 50 insertions(+), 10 deletions(-)
> create mode 100644
> Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSsdt
> /Sensors/GenericSpi3.asl
>
> diff --git
> a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/B
> oardGpios.h
> b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/B
> oardGpios.h
> index d72cd80c9..db48c4e85 100644
> ---
> a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/B
> oardGpios.h
> +++
> b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/B
> oardGpios.h
> @@ -80,13 +80,13 @@ BXT_GPIO_PAD_INIT mBenson_GpioInitData_N[] =
> BXT_GPIO_PAD_CONF(L"GPIO_14", M1 , NA , NA , NA ,
> NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA,
> GPIO_PADBAR+0x0070, NORTH),//Feature: LB
> BXT_GPIO_PAD_CONF(L"GPIO_15", M1 , NA , NA , NA ,
> NA , Wake_Disabled, P_20K_L, NA , NA ,NA , NA,
> GPIO_PADBAR+0x0078, NORTH),//Feature: LB
> BXT_GPIO_PAD_CONF(L"GPIO_16", M0 , GPI , NA , NA ,
> Edge , Wake_Disabled, P_20K_H, Inverted,IOAPIC, HizRx0I ,DisPuPd,
> GPIO_PADBAR+0x0080, NORTH),//Feature:SIM Card Detect Net in Sch:
> SIM_CON_CD1, falling edge trigger
> - BXT_GPIO_PAD_CONF(L"GPIO_17", M0 , GPI , GPIO_D, NA ,
> Edge , Wake_Disabled, P_NONE , NA ,IOAPIC, NA ,DisPuPd,
> GPIO_PADBAR+0x0088, NORTH), // SOC_LSE_HOST_IRQ_N
> + BXT_GPIO_PAD_CONF(L"GPIO_17", M0 , GPI , GPIO_D, NA ,
> Edge , Wake_Disabled, P_NONE , NA ,IOAPIC, NA ,DisPuPd,
> GPIO_PADBAR+0x0088, NORTH), // SOC_LSE_HOST_IRQ_N
> BXT_GPIO_PAD_CONF(L"GPIO_18", M1 , NA , NA , NA ,
> NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA,
> GPIO_PADBAR+0x0090, NORTH),//Feature: LB
> BXT_GPIO_PAD_CONF(L"GPIO_19", M1 , NA , NA , NA ,
> NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA,
> GPIO_PADBAR+0x0098, NORTH),//Feature: LB
> BXT_GPIO_PAD_CONF(L"GPIO_20", M1 , NA , NA , NA ,
> NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA,
> GPIO_PADBAR+0x00A0, NORTH),//Feature: LB
> BXT_GPIO_PAD_CONF(L"GPIO_21", M1 , NA , NA , NA ,
> NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA,
> GPIO_PADBAR+0x00A8, NORTH),//Feature: LB
> BXT_GPIO_PAD_CONF(L"GPIO_22", M0 , GPIO ,GPIO_D , NA ,
> NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA,
> GPIO_PADBAR+0x00B0, NORTH),//Feature: LB
> - BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO ,GPIO_D, LO ,
> NA , Wake_Disabled, P_20K_H, NA , NA, NA , EnPu,
> GPIO_PADBAR+0x00B8, NORTH), // SOC_SUE_RST_N
> + BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO ,GPIO_D, LO ,
> NA , Wake_Disabled, P_20K_H, NA , NA, NA , EnPu,
> GPIO_PADBAR+0x00B8, NORTH), // SOC_SUE_RST_N
> BXT_GPIO_PAD_CONF(L"GPIO_24", M0 , GPO ,GPIO_D , NA ,
> NA , Wake_Disabled, P_20K_H, NA , NA, NA , NA,
> GPIO_PADBAR+0x00C0, NORTH),//SATA_DEVSLP0
> BXT_GPIO_PAD_CONF(L"GPIO_25", M0 , GPO ,GPIO_D , NA ,
> Level , Wake_Disabled, P_20K_H, Inverted, SCI, NA , NA,
> GPIO_PADBAR+0x00C8, NORTH),//Feature:ODD MD/DA SCI Net in Sch:
> SATA_ODD_DA_IN
> BXT_GPIO_PAD_CONF(L"GPIO_26", M0 , GPIO ,GPIO_D , NA ,
> NA , Wake_Disabled, P_20K_L, NA , NA, NA , NA,
> GPIO_PADBAR+0x00D0, NORTH),//SATA_LEDN
> @@ -216,16 +216,16 @@ BXT_GPIO_PAD_INIT mBenson_GpioInitData_NW
> [] =
> BXT_GPIO_PAD_CONF(L"GPIO_106 GP_SSP_0_FS1", M0 , GPI ,
> GPIO_D , NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I ,
> EnPd, GPIO_PADBAR+0x01F8, NORTHWEST),
> BXT_GPIO_PAD_CONF(L"GPIO_109 GP_SSP_0_RXD", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd,
> GPIO_PADBAR+0x0200, NORTHWEST),
> BXT_GPIO_PAD_CONF(L"GPIO_110 GP_SSP_0_TXD", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , EnPd,
> GPIO_PADBAR+0x0208, NORTHWEST),
> - BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 ,
> GPI ,GPIO_D, NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA ,
> NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on RVP
> - BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0218, NORTHWEST),
> - BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0220, NORTHWEST),
> + BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 ,
> GPI ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA ,
> NA ,NA , NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on
> RVP
> + BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M0 ,
> GPI ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA ,
> NA, GPIO_PADBAR+0x0218, NORTHWEST),
> + BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M0 ,
> GPO ,GPIO_D, NA , NA , Wake_Disabled, P_20K_L, NA ,
> NA,NA , NA, GPIO_PADBAR+0x0220, NORTHWEST),
> BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M2 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0228, NORTHWEST),//Feature: LPSS UART Hdr
> BXT_GPIO_PAD_CONF(L"GPIO_117 GP_SSP_1_TXD", M0 , GPIO ,
> GPIO_D , NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA ,
> NA, GPIO_PADBAR+0x0230, NORTHWEST),//Feature: LPSS UART Hdr
> - BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M0 , GPIO , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0238, NORTHWEST),
> - BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M0 , GPIO , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0240, NORTHWEST),
> - BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M0 , GPIO , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0248, NORTHWEST),
> - BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M0 , GPIO , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0250, NORTHWEST),
> - BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M0 , GPIO , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0258, NORTHWEST),
> + BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0238, NORTHWEST),
> + BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0240, NORTHWEST),
> + BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0248, NORTHWEST),
> + BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0250, NORTHWEST),
> + BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0258, NORTHWEST),
> BXT_GPIO_PAD_CONF(L"GPIO_123 GP_SSP_2_TXD", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0260, NORTHWEST),
> BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0020, NORTHWEST),//Feature: DBI_SDA
> BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M1 , NA , NA ,
> NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , NA,
> GPIO_PADBAR+0x0028, NORTHWEST),//Feature: DBI_SCL
> diff --git
> a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs
> dt/PlatformSsdt.asl
> b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs
> dt/PlatformSsdt.asl
> index 1f9da7678..bbab6b63a 100644
> ---
> a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs
> dt/PlatformSsdt.asl
> +++
> b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs
> dt/PlatformSsdt.asl
> @@ -30,6 +30,7 @@ DefinitionBlock (
> External(\_SB.PCI0.URT2, DeviceObj)
> External(\_SB.PCI0.SDIO, DeviceObj)
> External(\_SB.PCI0.SPI1, DeviceObj)
> + External(\_SB.PCI0.SPI3, DeviceObj)
> External(\_SB.GPO0.CWLE, IntObj)
> External(\_SB.GPO0.AVBL, IntObj)
> External(\_SB.PCI0.SDIO.PSTS, IntObj)
> @@ -66,5 +67,6 @@ DefinitionBlock (
>
> include ("Fingerprint/Fingerprint_FPC.asl")
> include ("SueCreek/SueCreek.asl")
> + include ("Sensors/GenericSpi3.asl")
> }
>
> diff --git
> a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs
> dt/Sensors/GenericSpi3.asl
> b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs
> dt/Sensors/GenericSpi3.asl
> new file mode 100644
> index 000000000..830765bf3
> --- /dev/null
> +++
> b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/PlatformSs
> dt/Sensors/GenericSpi3.asl
> @@ -0,0 +1,38 @@
> +/** @file
> +
> +Copyright (c) 2017 Intel Corporation.
> +
> +This program and the accompanying materials
> +are licensed and made available under the terms and conditions of the BSD
> License
> +which accompanies this distribution. The full text of the license may be
> found at
> +http://opensource.org/licenses/bsd-license.php
> +
> +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> +
> +**/
> +
> +Scope (\_SB.PCI0.SPI3) {
> + Device (TP0) {
> + Name (_HID, "SPT0001")
> + Name (_DDN, "Sensor - SPI3, CS0")
> + Name (_CRS, ResourceTemplate () {
> + SpiSerialBus (
> + 0, // Chip select (0, 1, 2)
> + PolarityLow, // Chip select is active low
> + FourWireMode, // Full duplex
> + 8, // Bits per word is 8 (byte)
> + ControllerInitiated, // Don't care
> + 1000000, // 1 MHz
> + ClockPolarityLow, // SPI mode 0
> + ClockPhaseFirst, // SPI mode 0
> + "\\_SB.PCI0.SPI3", // SPI host controller
> + 0 // Must be 0
> + )
> + })
> + Method (_STA, 0x0, NotSerialized) {
> + Return (0xF)
> + }
> + }
> +}
> +
> --
> 2.14.1.windows.1
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