From nobody Tue Dec 24 13:03:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1511981142210210.48866041719657; Wed, 29 Nov 2017 10:45:42 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4E55520359E96; Wed, 29 Nov 2017 10:41:16 -0800 (PST) Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BFA8021A10974 for ; Wed, 29 Nov 2017 10:41:14 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id r78so8362305wme.5 for ; Wed, 29 Nov 2017 10:45:38 -0800 (PST) Received: from localhost.localdomain ([105.137.43.27]) by smtp.gmail.com with ESMTPSA id r14sm3724280wrb.43.2017.11.29.10.45.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 29 Nov 2017 10:45:36 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=K24/y6OIR/qt/x4sGAEPLhG5fhzxXqEBpbHUfnzGBJ8=; b=g1X2fZ79xaNl++slJXJBMYwyyrhTijG7JNNMZka928CtRkv1P7wVwaU+vVaD94VdfO sYJRIzUBTK0/iAdshvWLPNimRnf12byyydNi8NtzxDtyGJuSyCBIo7EUzdYDBLygtWtP rfPYddzL5yvDSK/gVP9j0nrcELT8m967Y/CJw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=K24/y6OIR/qt/x4sGAEPLhG5fhzxXqEBpbHUfnzGBJ8=; b=e1N6U/7UInjWKwGi9a35IXzPdgQYYx+SAkOLd+vKnlMNTJlYdsSyfHwZ/FOvj+OBXe Aem56Zjmz5B7cxzXPPWs1xGp0WVAOAPLd2WiLaa5ZRmFGz15i87yldnG+315YpFNdKpf P29xcQ6qzDo/AxtfkOUaIdh3Jq7K3OTTDoe3V+KzVgP182jM0atDXM7aNEYUigqHS9/g /3XWaKsiw8aZ+E2k6REUDY84NiLjEaLUSBEfiGoIoYwoX90vGWBRg4c8jL941SnFmWBv usj+1lNgJeum2bmlucCJ6wYMRzVXzvdnPukXI4NYa0PBlZ///CKIAwFVC0hyx9m15U76 HdMg== X-Gm-Message-State: AJaThX5m88E3fzrgstnbVzaqHt6UTsHmTw4HCTeIwfXEg+Un8lyNNTPs /BZ6lKANAoN6AAofyOFbmiq8rI1AOcA= X-Google-Smtp-Source: AGs4zMZFNlaZLfK3RL4EMWg8SrNu20IRzAS0jgupn5UJLCjHGR0/HohrOK/EU3fwRjsCQuFz9UlcRQ== X-Received: by 10.28.145.19 with SMTP id t19mr3256869wmd.0.1511981137306; Wed, 29 Nov 2017 10:45:37 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, daniel.thompson@linaro.org Date: Wed, 29 Nov 2017 18:44:59 +0000 Message-Id: <20171129184459.9017-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms] Silicon/SynQuacerPciHostBridgeLib: enable Gen2 speed X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masami.hiramatsu@linaro.org, masahisa.kojima@socionext.com, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" As it turns out, getting the PCIe controllers to switch to Gen2 speed is surprisingly easy. It only involves setting the 'speed change' bit in the controller at initialization time, after which the hardware will automatically attempt to switch to Gen2 speed after training at Gen1 speed has completed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPci= HostBridgeLibConstructor.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/= SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Librar= y/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index 6b42d3e29806..e63b3a4bb23b 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c @@ -113,6 +113,9 @@ #define PROGRAM_INTERFACE 0x0000FF00 #define PROGRAM_INTERFACE_VALUE 0x00 =20 +#define GEN2_CONTROL_OFF 0x80c +#define DIRECT_SPEED_CHANGE BIT17 + #define MISC_CONTROL_1_OFF 0x8BC #define DBI_RO_WR_EN BIT0 =20 @@ -295,6 +298,9 @@ PciInitController ( EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER); =20 + // Force link speed change to Gen2 at link up + MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE); + // Region 0: MMIO32 range ConfigureWindow (DbiBase, 0, RootBridge->Mem.Base, --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel