From nobody Tue Dec 24 16:58:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512127990130960.3749057172937; Fri, 1 Dec 2017 03:33:10 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D71C620352A8F; Fri, 1 Dec 2017 03:28:41 -0800 (PST) Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 15C0720352A8A for ; Fri, 1 Dec 2017 03:28:40 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id n138so2953624wmg.2 for ; Fri, 01 Dec 2017 03:33:07 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id k11sm918430wmi.18.2017.12.01.03.33.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Dec 2017 03:33:04 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QdQhKf8wc7+BsHeOvrJNbhA3uDNlhMt3qDsUEgTTAo0=; b=HqYVhOzJD4rkVzVFfDvnPM+WuDRrXvVPPbC7KosTXFJ3onP2CdfCykLq/ff4mf1gYf 9/mqYM+SRE3rnpqf0+6u+ABrSKcjaT1TSa6BS9dbKaT1icyKnAOaTbCaFNk8z0hap6ri 2bxkY2ViCFhm1pe/Amr6g2i/xI5E+qtbbbNcA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QdQhKf8wc7+BsHeOvrJNbhA3uDNlhMt3qDsUEgTTAo0=; b=mztn97AyDXNal8KfVuiaE/eWXr6nIyIMl5+aNuMxc0cKMA6nhWJENjJ8UL5UC7EAAc p9+7axLHkVGrmBGYXeaK+/Ry/XV8x3zTxIrH057y+4Cns85siw1U0Xb4FGUqRhW77d4z 0H7cDqD9yVHQXH4lGBDvqCrxd68zudh1zfloWTA1/sGLUBytjdI97Di2sSW1/vAqd6yw MYxfwm77jVEK4myJlMSc5EkwneWy/AiaTocA/HUWPJrZKWi8wSdo/w/UIwlTz0vvcBRC f2XHQuK7Wu4k9U+mFh9NavxSdugfFAJSfzUnGPoXxr/INtcHOlCygOOcH2CydO48ZP4S B4oQ== X-Gm-Message-State: AJaThX4q5Wghm0braLhWUpBA7Ja/g2J1qeJ0PiYNvKh47ORWnDZw24k0 pJEcWvjKed2VI5PwdCUnSvIPvep4+YQ= X-Google-Smtp-Source: AGs4zMY7tgP85iLKXeJ6NmlnP3BQay4hTVnLZTxfeYGzZLuL13kheX8mNWYLAEOchOrV46PFKmlyjw== X-Received: by 10.28.208.205 with SMTP id h196mr1075595wmg.160.1512127985701; Fri, 01 Dec 2017 03:33:05 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 1 Dec 2017 11:32:51 +0000 Message-Id: <20171201113255.23581-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171201113255.23581-1-ard.biesheuvel@linaro.org> References: <20171201113255.23581-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 1/5] ArmPlatformPkg: introduce LcdhwLib library class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add the declaration and include file for the new LcdHwLib library class, which will allow us to abstract away from platform variations in the LCD graphics output driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmPlatformPkg.dec | 1 + ArmPlatformPkg/Include/Library/LcdHwLib.h | 65 ++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatform= Pkg.dec index 9d47e459eadc..9ccf540e5b80 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -32,6 +32,7 @@ [Includes.common] Include # Root include for the package =20 [LibraryClasses] + LcdHwLib|Include/Library/LcdHwLib.h PL011UartLib|Include/Library/PL011UartLib.h =20 [Guids.common] diff --git a/ArmPlatformPkg/Include/Library/LcdHwLib.h b/ArmPlatformPkg/Inc= lude/Library/LcdHwLib.h new file mode 100644 index 000000000000..a426cd392357 --- /dev/null +++ b/ArmPlatformPkg/Include/Library/LcdHwLib.h @@ -0,0 +1,65 @@ +/** @file LcdHwLib.h + + This file contains interface functions for LcdHwLib of ArmPlatformPkg + + Copyright (c) 2017, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef LCD_HW_LIB_H_ +#define LCD_HW_LIB_H_ + +#include + +/** Check for presence of display + * + * @retval EFI_SUCCESS Platform implements display. + * @retval EFI_NOT_FOUND Display not found on the platform. + */ +EFI_STATUS +LcdIdentify ( + VOID +); + +/** Initialize display. + * + * @param FrameBaseAddress Address of the frame buffer. + * @retval EFI_SUCCESS Display initialization success. + * @retval !(EFI_SUCCESS) Display initialization failure. + * +**/ +EFI_STATUS +LcdInitialize ( + EFI_PHYSICAL_ADDRESS FrameBaseAddress +); + +/** Set requested mode of the display. + * + * @param ModeNumber Display mode number. + * @retval EFI_SUCCESS Display set mode success. + * @retval EFI_DEVICE_ERROR If mode not found/supported. + * +**/ +EFI_STATUS +LcdSetMode ( + IN UINT32 ModeNumber +); + + +/** De-initializes the display. + * +**/ +VOID +LcdShutdown ( + VOID +); + +#endif /* LCD_HW_LIB_H_ */ --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Dec 24 16:58:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512127992395930.2223072157585; Fri, 1 Dec 2017 03:33:12 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 23EF920352A8C; Fri, 1 Dec 2017 03:28:45 -0800 (PST) Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 70D6620352A8C for ; Fri, 1 Dec 2017 03:28:43 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id t8so2949031wmc.3 for ; Fri, 01 Dec 2017 03:33:09 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id k11sm918430wmi.18.2017.12.01.03.33.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Dec 2017 03:33:07 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VzJPVu4lDVayls0DM83XqoWaUJ7cAtGntSajL+TSdW0=; b=R94od2qeqLtyUbQ+v5hlq9KS+A5WOlEC8ZL7Ix0RT5OxDsZYOPSfl99SdhzQ8sKz49 2tKqzVLerk+RrTmnCAOlEwCWlCZ6Syeol1Ka0RWRDplNpNxqq3vAOmzvUTMQXWrOAl4J Kp9EecAuTd63uWpA1uu9Jji1cT978MqZyF6Pg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VzJPVu4lDVayls0DM83XqoWaUJ7cAtGntSajL+TSdW0=; b=HfSMqyBgDNtI2RFDYYJ9AWrY0WLaIJm2Nmo/6cD/1A8o4i10Dm8E6YqMXke1rOGAdR VZ+iPjJvYFLdN7EWyBknLKxYt20mIjPxanip0U7/ezX/zuasNTHz27sPpsWX88P2omLv EBZfUL79fZaE1YXrPbcBS1cDQ0O0vWnnTSU6PjdreX6PNtRwM4ngh7FmAsKRvXnaWA5P UbI+RwyTG8UBn08UqW4gIKBQNuiJGDd/Qy0evV0YsTKUaxQ9gzuVyRjlZ+89q/yl3TWK e3fPqwPixXWhaBJ698RkMz4nz3x3CJ5wMxjwoTzuJSIkzTc3uWEhdlQ7C7cB8BQUwnB7 lOvQ== X-Gm-Message-State: AJaThX5sug3RBj7ZzFUQTv34Sl5VUtmytGubW+h43Y6kZu1pRT46dloU 1g/J+2WCmZ4dHFhk/bIAhpP9dp//evM= X-Google-Smtp-Source: AGs4zMaeUIlJgucsBlxFQ5EEnKuvXI93wu49hn1yUgqpnHwuZJrdWUDQTDov5lW4usU23/7dENbXIw== X-Received: by 10.28.156.23 with SMTP id f23mr1108140wme.128.1512127987965; Fri, 01 Dec 2017 03:33:07 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 1 Dec 2017 11:32:52 +0000 Message-Id: <20171201113255.23581-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171201113255.23581-1-ard.biesheuvel@linaro.org> References: <20171201113255.23581-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 2/5] ArmPlatformPkg: implement LcdHwLib for PL111 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Convert the PL111 specific code of LcdGraphicsOutputDxe into a LcdHwlib implementation that we will wire up later into LcdGraphicsOutputDxe. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c | 126 +++++++++++++++++ ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h | 149 ++++++++++++++++++++ ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf | 40 ++++++ 3 files changed, 315 insertions(+) diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Li= brary/PL111Lcd/PL111Lcd.c new file mode 100644 index 000000000000..9b4a02045ab7 --- /dev/null +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -0,0 +1,126 @@ +/** @file PL111Lcd.c + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ +#include +#include +#include +#include +#include + +#include "PL111Lcd.h" + +/********************************************************************** + * + * This file contains all the bits of the PL111 that are + * platform independent. + * + **********************************************************************/ + +EFI_STATUS +LcdIdentify ( + VOID + ) +{ + DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n", + PL111_REG_CLCD_PERIPH_ID_0)); + + // Check if this is a PL111 + if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) =3D=3D PL111_CLCD_PERIPH_ID_0= && + MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) =3D=3D PL111_CLCD_PERIPH_ID_1= && + (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) =3D=3D PL111_CLCD_PERI= PH_ID_2 && + MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) =3D=3D PL111_CLCD_PERIPH_ID_3= && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) =3D=3D PL111_CLCD_P_CELL_ID_0= && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) =3D=3D PL111_CLCD_P_CELL_ID_1= && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) =3D=3D PL111_CLCD_P_CELL_ID_2= && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) =3D=3D PL111_CLCD_P_CELL_ID_3= ) { + return EFI_SUCCESS; + } + return EFI_NOT_FOUND; +} + +EFI_STATUS +LcdInitialize ( + IN EFI_PHYSICAL_ADDRESS VramBaseAddress + ) +{ + // Define start of the VRAM. This never changes for any graphics mode + MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress); + MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buff= er + + // Disable all interrupts from the PL111 + MmioWrite32(PL111_REG_LCD_IMSC, 0); + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdSetMode ( + IN UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + UINT32 HRes; + UINT32 HSync; + UINT32 HBackPorch; + UINT32 HFrontPorch; + UINT32 VRes; + UINT32 VSync; + UINT32 VBackPorch; + UINT32 VFrontPorch; + UINT32 LcdControl; + LCD_BPP LcdBpp; + + // Set the video mode timings and other relevant information + Status =3D LcdPlatformGetTimings (ModeNumber, + &HRes,&HSync,&HBackPorch,&HFrontPorch, + &VRes,&VSync,&VBackPorch,&VFrontPorch); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR( Status )) { + return EFI_DEVICE_ERROR; + } + + Status =3D LcdPlatformGetBpp (ModeNumber,&LcdBpp); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR( Status )) { + return EFI_DEVICE_ERROR; + } + + // Disable the CLCD_LcdEn bit + LcdControl =3D MmioRead32( PL111_REG_LCD_CONTROL); + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1); + + // Set Timings + MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPo= rch, HSync, HRes)); + MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPo= rch, VSync, VRes)); + MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes)); + MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); + + // PL111_REG_LCD_CONTROL + LcdControl =3D PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CT= RL_LCD_TFT | PL111_CTRL_BGR; + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); + + // Turn on power to the LCD Panel + LcdControl |=3D PL111_CTRL_LCD_PWR; + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); + + return EFI_SUCCESS; +} + +VOID +LcdShutdown ( + VOID + ) +{ + // Disable the controller + MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); +} diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h b/ArmPlatformPkg/Li= brary/PL111Lcd/PL111Lcd.h new file mode 100644 index 000000000000..18e28af805f6 --- /dev/null +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h @@ -0,0 +1,149 @@ +/** @file PL111Lcd.h + + Copyright (c) 2011, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + **/ + +#ifndef _PL111LCD_H__ +#define _PL111LCD_H__ + +/********************************************************************** + * + * This header file contains all the bits of the PL111 that are + * platform independent. + * + **********************************************************************/ + +// Controller Register Offsets +#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x000) +#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x004) +#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x008) +#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x00C) +#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x010) +#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x014) +#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x018) +#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x01C) +#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x020) +#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x024) +#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x028) +#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x02C) +#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x030) +#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x200) + +// Identification Register Offsets +#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFE0) +#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFE4) +#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFE8) +#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFEC) +#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFF0) +#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFF4) +#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFF8) +#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFFC) + +#define PL111_CLCD_PERIPH_ID_0 0x11 +#define PL111_CLCD_PERIPH_ID_1 0x11 +#define PL111_CLCD_PERIPH_ID_2 0x04 +#define PL111_CLCD_PERIPH_ID_3 0x00 +#define PL111_CLCD_P_CELL_ID_0 0x0D +#define PL111_CLCD_P_CELL_ID_1 0xF0 +#define PL111_CLCD_P_CELL_ID_2 0x05 +#define PL111_CLCD_P_CELL_ID_3 0xB1 + +/**********************************************************************/ + +// Register components (register bits) + +// This should make life easier to program specific settings in the differ= ent registers +// by simplifying the setting up of the individual bits of each register +// and then assembling the final register value. + +/**********************************************************************/ + +// Register: PL111_REG_LCD_TIMING_0 +#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24)= | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-= 1) << 2)) + +// Register: PL111_REG_LCD_TIMING_1 +#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24)= | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1)) + +// Register: PL111_REG_LCD_TIMING_2 +#define PL111_BIT_SHIFT_PCD_HI 27 +#define PL111_BIT_SHIFT_BCD 26 +#define PL111_BIT_SHIFT_CPL 16 +#define PL111_BIT_SHIFT_IOE 14 +#define PL111_BIT_SHIFT_IPC 13 +#define PL111_BIT_SHIFT_IHS 12 +#define PL111_BIT_SHIFT_IVS 11 +#define PL111_BIT_SHIFT_ACB 6 +#define PL111_BIT_SHIFT_CLKSEL 5 +#define PL111_BIT_SHIFT_PCD_LO 0 + +#define PL111_BCD (1 << 26) +#define PL111_IPC (1 << 13) +#define PL111_IHS (1 << 12) +#define PL111_IVS (1 << 11) + +#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC |= PL111_IHS | PL111_IVS | (((hor_res)-1) << 16)) + +// Register: PL111_REG_LCD_TIMING_3 +#define PL111_BIT_SHIFT_LEE 16 +#define PL111_BIT_SHIFT_LED 0 + +#define PL111_CTRL_WATERMARK (1 << 16) +#define PL111_CTRL_LCD_V_COMP (1 << 12) +#define PL111_CTRL_LCD_PWR (1 << 11) +#define PL111_CTRL_BEPO (1 << 10) +#define PL111_CTRL_BEBO (1 << 9) +#define PL111_CTRL_BGR (1 << 8) +#define PL111_CTRL_LCD_DUAL (1 << 7) +#define PL111_CTRL_LCD_MONO_8 (1 << 6) +#define PL111_CTRL_LCD_TFT (1 << 5) +#define PL111_CTRL_LCD_BW (1 << 4) +#define PL111_CTRL_LCD_1BPP (0 << 1) +#define PL111_CTRL_LCD_2BPP (1 << 1) +#define PL111_CTRL_LCD_4BPP (2 << 1) +#define PL111_CTRL_LCD_8BPP (3 << 1) +#define PL111_CTRL_LCD_16BPP (4 << 1) +#define PL111_CTRL_LCD_24BPP (5 << 1) +#define PL111_CTRL_LCD_16BPP_565 (6 << 1) +#define PL111_CTRL_LCD_12BPP_444 (7 << 1) +#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1) +#define PL111_CTRL_LCD_EN 1 + +/**********************************************************************/ + +// Register: PL111_REG_LCD_TIMING_0 +#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24) +#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16) +#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) +#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2) + +// Register: PL111_REG_LCD_TIMING_1 +#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24) +#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16) +#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10) +#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC) + +// Register: PL111_REG_LCD_TIMING_2 +#define PL111_BIT_MASK_PCD_HI 0xF8000000 +#define PL111_BIT_MASK_BCD 0x04000000 +#define PL111_BIT_MASK_CPL 0x03FF0000 +#define PL111_BIT_MASK_IOE 0x00004000 +#define PL111_BIT_MASK_IPC 0x00002000 +#define PL111_BIT_MASK_IHS 0x00001000 +#define PL111_BIT_MASK_IVS 0x00000800 +#define PL111_BIT_MASK_ACB 0x000007C0 +#define PL111_BIT_MASK_CLKSEL 0x00000020 +#define PL111_BIT_MASK_PCD_LO 0x0000001F + +// Register: PL111_REG_LCD_TIMING_3 +#define PL111_BIT_MASK_LEE 0x00010000 +#define PL111_BIT_MASK_LED 0x0000007F + +#endif /* _PL111LCD_H__ */ diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf b/ArmPlatformPkg/= Library/PL111Lcd/PL111Lcd.inf new file mode 100644 index 000000000000..40db77eb079e --- /dev/null +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf @@ -0,0 +1,40 @@ +#/** @file PL111Lcd.inf +# +# Component description file for PL111Lcd module +# +# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PL111Lcd + FILE_GUID =3D 407B4008-BF5B-11DF-9547-CF16E0D72085 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdHwLib + +[Sources.common] + PL111Lcd.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiLib + BaseLib + DebugLib + IoLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdPL111LcdBase --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Dec 24 16:58:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512127994596549.4393264569295; Fri, 1 Dec 2017 03:33:14 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 634DA20352A94; Fri, 1 Dec 2017 03:28:47 -0800 (PST) Received: from mail-wm0-x229.google.com (mail-wm0-x229.google.com [IPv6:2a00:1450:400c:c09::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D1E1720352A89 for ; Fri, 1 Dec 2017 03:28:45 -0800 (PST) Received: by mail-wm0-x229.google.com with SMTP id i11so2815893wmf.4 for ; Fri, 01 Dec 2017 03:33:12 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id k11sm918430wmi.18.2017.12.01.03.33.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Dec 2017 03:33:09 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::229; helo=mail-wm0-x229.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m9sJYt0r8BuVeOBEJGZXRfwWuU6Xatiga80sGeip4h0=; b=jztUVKNzVIozm9rJHcT6zU+PLwCltKCJdpzvhUmyCqhfvYxvVtlpBLyxEvq7hMAVoW y/gu9NKM/1uYRSALWT2psK6CQOjyAgbpAjDYHxXhb6WTuM0XT3KR98WLah92QOR4AD3Z yCHS0UHdpvUx5x4ZIL/BePezo7nzYBmr+6WeA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m9sJYt0r8BuVeOBEJGZXRfwWuU6Xatiga80sGeip4h0=; b=g+IIQAey23s/nSRN8wte4H+N/uhuFUYfC0dbweiOJ1Iiw8E6umnoBiCPfniTr21AhG VV3OIsOOcRXK0wrfShOtll+/1RmPiObGSzHHkMIHs4mrtQP49/sJQuZvksyFGCKMmpaZ 8guh5q3j2AjaZChpoiqB29f/g5HnvvGqpLuHRIw1vsTZp2ziV8hgzANx3Wye+yLMPKWr rAeb4pKU2HUXywDpq9OkFaMNN1UOLZD5itv5iTH9eTArP+us1t/Uy7bV/NnNdnz+/cQ9 no6keVJM5ACr6HrPJPQF9KimxPH7U9ZEkVxyzXTaHPlMQjXGkC+7Ktk5xl+92nUH6a1y Gyxg== X-Gm-Message-State: AJaThX6poMNpj4dvnaZaSDdjqGDIke9PqX/4UTaQeMmqWBZin6Nb4shi eLQy7maWLB4WiCHwI419dmXjS42WSyU= X-Google-Smtp-Source: AGs4zMbfjKzzKkXzsPpiUvmeshhOI2XxJk4a4pt0ww9hQHDKEYIAgXu9FTWIyyJyIHOnPHU2M0eNrw== X-Received: by 10.28.199.133 with SMTP id x127mr937197wmf.156.1512127990295; Fri, 01 Dec 2017 03:33:10 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 1 Dec 2017 11:32:53 +0000 Message-Id: <20171201113255.23581-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171201113255.23581-1-ard.biesheuvel@linaro.org> References: <20171201113255.23581-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 3/5] ArmPlatformPkg: implement LcdHwLib for HdLcd X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Convert the HdLcd specific code of LcdGraphicsOutputDxe into a LcdHwlib implementation that we will wire up later into LcdGraphicsOutputDxe. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/Library/HdLcd/HdLcd.c | 158 ++++++++++++++++++++ ArmPlatformPkg/Library/HdLcd/HdLcd.h | 89 +++++++++++ ArmPlatformPkg/Library/HdLcd/HdLcd.inf | 42 ++++++ 3 files changed, 289 insertions(+) diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.c b/ArmPlatformPkg/Library/= HdLcd/HdLcd.c new file mode 100644 index 000000000000..24efb68f23e3 --- /dev/null +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.c @@ -0,0 +1,158 @@ +/** @file Lcd.c + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include + +#include "HdLcd.h" + +/********************************************************************** + * + * This file contains all the bits of the Lcd that are + * platform independent. + * + **********************************************************************/ + +STATIC +UINTN +GetBytesPerPixel ( + IN LCD_BPP Bpp + ) +{ + switch(Bpp) { + case LCD_BITS_PER_PIXEL_24: + return 4; + + case LCD_BITS_PER_PIXEL_16_565: + case LCD_BITS_PER_PIXEL_16_555: + case LCD_BITS_PER_PIXEL_12_444: + return 2; + + case LCD_BITS_PER_PIXEL_8: + case LCD_BITS_PER_PIXEL_4: + case LCD_BITS_PER_PIXEL_2: + case LCD_BITS_PER_PIXEL_1: + return 1; + + default: + return 0; + } +} + +EFI_STATUS +LcdInitialize ( + IN EFI_PHYSICAL_ADDRESS VramBaseAddress + ) +{ + // Disable the controller + MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); + + // Disable all interrupts + MmioWrite32(HDLCD_REG_INT_MASK, 0); + + // Define start of the VRAM. This never changes for any graphics mode + MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress); + + // Setup various registers that never change + MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8); + MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | = HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH); + MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_P= ER_PIXEL); + MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0)); + MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8)); + MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16)); + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdSetMode ( + IN UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + UINT32 HRes; + UINT32 HSync; + UINT32 HBackPorch; + UINT32 HFrontPorch; + UINT32 VRes; + UINT32 VSync; + UINT32 VBackPorch; + UINT32 VFrontPorch; + UINT32 BytesPerPixel; + LCD_BPP LcdBpp; + + + // Set the video mode timings and other relevant information + Status =3D LcdPlatformGetTimings (ModeNumber, + &HRes,&HSync,&HBackPorch,&HFrontPorch, + &VRes,&VSync,&VBackPorch,&VFrontPorch); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR( Status )) { + return EFI_DEVICE_ERROR; + } + + Status =3D LcdPlatformGetBpp (ModeNumber,&LcdBpp); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR( Status )) { + return EFI_DEVICE_ERROR; + } + + BytesPerPixel =3D GetBytesPerPixel(LcdBpp); + + // Disable the controller + MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); + + // Update the frame buffer information with the new settings + MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel); + MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel); + MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1); + + // Set the vertical timing information + MmioWrite32(HDLCD_REG_V_SYNC, VSync); + MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch); + MmioWrite32(HDLCD_REG_V_DATA, VRes - 1); + MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch); + + // Set the horizontal timing information + MmioWrite32(HDLCD_REG_H_SYNC, HSync); + MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch); + MmioWrite32(HDLCD_REG_H_DATA, HRes - 1); + MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch); + + // Enable the controller + MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE); + + return EFI_SUCCESS; +} + +VOID +LcdShutdown ( + VOID + ) +{ + // Disable the controller + MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); +} + +EFI_STATUS +LcdIdentify ( + VOID + ) +{ + return EFI_SUCCESS; +} diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.h b/ArmPlatformPkg/Library/= HdLcd/HdLcd.h new file mode 100644 index 000000000000..6df97a9dfee6 --- /dev/null +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.h @@ -0,0 +1,89 @@ +/** @file HDLcd.h + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + **/ + +#ifndef _HDLCD_H_ +#define _HDLCD_H_ + +// +// HDLCD Controller Register Offsets +// + +#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x000) +#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x010) +#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x014) +#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x018) +#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x01C) +#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x100) +#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x104) +#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x108) +#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x10C) +#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x110) +#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x200) +#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x204) +#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x208) +#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x20C) +#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x210) +#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x214) +#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x218) +#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x21C) +#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x220) +#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x230) +#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x240) +#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x244) +#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x248) +#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x24C) + + +// +// HDLCD Values of registers +// + +// HDLCD Interrupt mask, clear and status register +#define HDLCD_DMA_END BIT0 /* DMA has finished read= ing a frame */ +#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */ +#define HDLCD_SYNC BIT2 /* Vertical sync */ +#define HDLCD_UNDERRUN BIT3 /* No Data available whi= le DATAEN active */ + +// CLCD_CONTROL Control register +#define HDLCD_DISABLE 0 +#define HDLCD_ENABLE BIT0 + +// Bus Options +#define HDLCD_BURST_1 BIT0 +#define HDLCD_BURST_2 BIT1 +#define HDLCD_BURST_4 BIT2 +#define HDLCD_BURST_8 BIT3 +#define HDLCD_BURST_16 BIT4 + +// Polarities - HIGH +#define HDLCD_VSYNC_HIGH BIT0 +#define HDLCD_HSYNC_HIGH BIT1 +#define HDLCD_DATEN_HIGH BIT2 +#define HDLCD_DATA_HIGH BIT3 +#define HDLCD_PXCLK_HIGH BIT4 +// Polarities - LOW (for completion and for ease of understanding the hard= ware settings) +#define HDLCD_VSYNC_LOW 0 +#define HDLCD_HSYNC_LOW 0 +#define HDLCD_DATEN_LOW 0 +#define HDLCD_DATA_LOW 0 +#define HDLCD_PXCLK_LOW 0 + +// Pixel Format +#define HDLCD_LITTLE_ENDIAN (0 << 31) +#define HDLCD_BIG_ENDIAN (1 << 31) + +// Number of bytes per pixel +#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3) + +#endif /* _HDLCD_H_ */ diff --git a/ArmPlatformPkg/Library/HdLcd/HdLcd.inf b/ArmPlatformPkg/Librar= y/HdLcd/HdLcd.inf new file mode 100644 index 000000000000..67aad05d210b --- /dev/null +++ b/ArmPlatformPkg/Library/HdLcd/HdLcd.inf @@ -0,0 +1,42 @@ +#/** @file +# +# Component description file for HDLCD module +# +# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D HdLcd + FILE_GUID =3D ce660500-824d-11e0-ac72-0002a5d5c51b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdHwLib + +[Sources.common] + HdLcd.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + UefiLib + BaseLib + DebugLib + IoLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Dec 24 16:58:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512127997195375.6725171949421; Fri, 1 Dec 2017 03:33:17 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A3A6F20352A98; Fri, 1 Dec 2017 03:28:49 -0800 (PST) Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D30DC20352A89 for ; Fri, 1 Dec 2017 03:28:47 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id v19so2816415wmh.5 for ; Fri, 01 Dec 2017 03:33:14 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id k11sm918430wmi.18.2017.12.01.03.33.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Dec 2017 03:33:11 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uMx1Q4hd2GUXPCBR2nHMycc8JWye6ZneIVAAgSGnUTI=; b=Te8FUsYk7C8jKYxJ1Rhen7G/A+iGYbOiQvALxTqY0nbulsB0J6L8C8zzou4uqHGP+D vD6MyPHx9NA7A+17AV5mbTp0ZWYzhYVVJhMNEztL4UNG0157m5JXlNHpab9mW7KZKtvg KL3iE+sVLMJ0LYkA/MsJPSNCYWNCsOiPq11fg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uMx1Q4hd2GUXPCBR2nHMycc8JWye6ZneIVAAgSGnUTI=; b=VGFf2nFiNvz8HNSnDE02tMp/J+liv3UGWvKxvNoEh/DeXcgf0Hilo+oEqzvDIUvIat 931U9+A6G7yYLSVhRHoiEe28RK/QV0Qhz28PRroc8njeaVgRgyB8Om0/j+TtAsSEsskp ipuusr3nIReZSKBlgJk0XedgHMJajulSP7uUFiVTV1rQ69TJb5CTzIzmfWHcOhM3opZN 86RdIDBmUbYwTezj9oHBRqOF2mjWWQa8qgiTxWJeT/qCxkWbGSUOSEjfKi2r1C9Ep0Gp 8Rr7yyCgptv4LRHgwjyxsmAE1BC3+3uuaPPvjXyoq79iYK1Yc1omDpoZBGdkqYrJEkOc 5Myw== X-Gm-Message-State: AJaThX4BPiVWAh917FdkDknAchanaMeXKdpXZOF+bhSjHviWqSSKZCyg KtVHEHxL7fKCOmVHII1Z+DnffmQExBo= X-Google-Smtp-Source: AGs4zMaPfp2juF5ulUAU+epftbjhivxDY+ZddN0LvQ5TrpKuxssvL5x+Nnoik4LGpK1qUzZ6qd+WHA== X-Received: by 10.28.125.85 with SMTP id y82mr872241wmc.25.1512127992572; Fri, 01 Dec 2017 03:33:12 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 1 Dec 2017 11:32:54 +0000 Message-Id: <20171201113255.23581-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171201113255.23581-1-ard.biesheuvel@linaro.org> References: <20171201113255.23581-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 4/5] ArmPlatformPkg: create hw-agnostic LcdGraphicsOutputDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Create a new LcdGraphicsOutputDxe driver from the existing sources that takes its hardware abstractions from a LcdHwLib library instance rather than from a .c file linked directly. All we need is a new .inf file, and a minimal tweak to LcdGraphicsOutputDxe.h to reuse the LcdHwlib prototypes rather than open code them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h | 21 = +------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf | 54 = ++++++++++++++++++++ 2 files changed, 55 insertions(+), 20 deletions(-) diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputD= xe.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h index 8856b79901b6..b66efd34561f 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h @@ -18,6 +18,7 @@ #include =20 #include +#include #include #include #include @@ -105,24 +106,4 @@ InitializeDisplay ( IN LCD_INSTANCE* Instance ); =20 -EFI_STATUS -LcdIdentify ( - VOID -); - -EFI_STATUS -LcdInitialize ( - EFI_PHYSICAL_ADDRESS VramBaseAddress -); - -EFI_STATUS -LcdSetMode ( - IN UINT32 ModeNumber -); - -VOID -LcdShutdown ( - VOID -); - #endif /* __ARM_VE_GRAPHICS_DXE_H__ */ diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputD= xe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.i= nf new file mode 100644 index 000000000000..e6424475f79d --- /dev/null +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf @@ -0,0 +1,54 @@ +#/** @file +# +# Component description file for LcdGraphicsOutputDxe module +# +# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D LcdGraphicsOutputDxe + FILE_GUID =3D 89464DAE-8DAA-41FE-A4C8-40D2175AF1E9 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D LcdGraphicsOutputDxeInitialize + +[Sources.common] + LcdGraphicsOutputDxe.c + LcdGraphicsOutputBlt.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + BaseLib + BaseMemoryLib + DebugLib + LcdHwLib + LcdPlatformLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gEfiDevicePathProtocolGuid + gEfiGraphicsOutputProtocolGuid + +[FeaturePcd] + gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices + +[Depex] + TRUE --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Dec 24 16:58:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512128000373682.0309039892953; Fri, 1 Dec 2017 03:33:20 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E532C20352A96; Fri, 1 Dec 2017 03:28:52 -0800 (PST) Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 72B2F20352A8A for ; Fri, 1 Dec 2017 03:28:51 -0800 (PST) Received: by mail-wr0-x244.google.com with SMTP id s66so9737709wrc.9 for ; Fri, 01 Dec 2017 03:33:17 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id k11sm918430wmi.18.2017.12.01.03.33.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Dec 2017 03:33:14 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::244; helo=mail-wr0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pIam5O69u4KL8iDuwjridT9QQ5C6RI8JlxOuI9z5UMQ=; b=h/DeG8/yAAj6PaJ2hBbYUnmFApMhHVOLN8PNAX2AJoCRRMQIaH1BnQkJT1KyY0XKVG 3lVkuiBHdl/Q/6rhAnJev50+mqsH6C10nqLbMhOwB+/vnvr9lvyjUku4cdesktu1t2rZ q7o87Ddj11OqZJqz8fqcjdz4AhyGgOFmzgT+I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pIam5O69u4KL8iDuwjridT9QQ5C6RI8JlxOuI9z5UMQ=; b=JZTaPtH6nBsqzJj04jVjzXO0cF7E+LKliEonP0HqyVtFVT8nrwgBf8sxdtUNw49ahc dOPr80jryHj2DCXuxet+wRcs1mLYpeQqtsilTQ94whPuo8vbGDu41biXSE0B+c30iu26 Qy4VkLufdD64dAj92jlUoM8KY5O+JIX3RYdxcbrcZNxZY19x/StdgkQa4pxN4zWTqwDG 7kHuDmuqCKsMRM0dHPVlQw2eyGuwsoiMIYOCkTvMIwoPlMFIOMy5yv2SVTxnbj7uJgV3 RX9pcLgdHIK278jbyxlMfYDGxLVTWBBx/jJHx684+6iuMaRIWE5E/bq7DV9zUw2eNXdM qGWA== X-Gm-Message-State: AJaThX4S5WFNW9jvhRpkg7LEdKvsdCnGG6Tld/x+pBaYJnsWmasgLyxs MvD6Jx3QhMESn7gbkGw1JU5V6jBZm8U= X-Google-Smtp-Source: AGs4zMb+Avbc70nVvQlY9wBY57k3hnvjCcSzSlPql6BPydg3Kp297YrnOnidSgfk264O1NdUeZKYRw== X-Received: by 10.223.184.125 with SMTP id u58mr5081844wrf.33.1512127995299; Fri, 01 Dec 2017 03:33:15 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Fri, 1 Dec 2017 11:32:55 +0000 Message-Id: <20171201113255.23581-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171201113255.23581-1-ard.biesheuvel@linaro.org> References: <20171201113255.23581-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH 5/5] ArmPlatformPkg: remove old PL111/HdLcd driver code X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Now that LcdGraphicsOutputDxe has been refactored, remove the old code that is no longer used. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Girish Pathak Signed-off-by: Evan Lloyd Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c | 285 --------------- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf | 45 --- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c | 370 -------------------- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf | 44 --- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c = | 133 ------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf = | 63 ---- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c = | 126 ------- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf = | 59 ---- ArmPlatformPkg/Include/Drivers/HdLcd.h = | 89 ----- ArmPlatformPkg/Include/Drivers/PL111Lcd.h = | 149 -------- 10 files changed, 1363 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/= HdLcdArmVExpress.c deleted file mode 100644 index b1106ee19b98..000000000000 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= press.c +++ /dev/null @@ -1,285 +0,0 @@ -/** - - Copyright (c) 2012, ARM Ltd. All rights reserved. - - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -typedef struct { - UINT32 Mode; - UINT32 HorizontalResolution; - UINT32 VerticalResolution; - LCD_BPP Bpp; - UINT32 OscFreq; - - // These are used by HDLCD - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; -} LCD_RESOLUTION; - - -LCD_RESOLUTION mResolutions[] =3D { - { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OS= C_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH - }, - { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVG= A_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH - }, - { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OS= C_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH - }, - { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SX= GA_OSC_FREQUENCY/2), - SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, - SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH - }, - { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UX= GA_OSC_FREQUENCY/2), - UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, - UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH - }, - { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_F= REQUENCY/2), - HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, - HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH - } -}; - -EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered =3D { - 0, - NULL -}; - -EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { - 0, - NULL -}; - -EFI_STATUS -LcdPlatformInitializeDisplay ( - IN EFI_HANDLE Handle - ) -{ - EFI_STATUS Status; - - // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); - if (EFI_ERROR(Status)) { - return Status; - } - - // Install the EDID Protocols - Status =3D gBS->InstallMultipleProtocolInterfaces ( - &Handle, - &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, - &gEfiEdidActiveProtocolGuid, &mEdidActive, - NULL - ); - - return Status; -} - -EFI_STATUS -LcdPlatformGetVram ( - OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, - OUT UINTN* VramSize - ) -{ - EFI_STATUS Status; - EFI_ALLOCATE_TYPE AllocationType; - - // Set the vram size - *VramSize =3D LCD_VRAM_SIZE; - - *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE; - - // Allocate the VRAM from the DRAM so that nobody else uses it. - if (*VramBaseAddress =3D=3D 0) { - AllocationType =3D AllocateAnyPages; - } else { - AllocationType =3D AllocateAddress; - } - Status =3D gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_= SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); - if (EFI_ERROR(Status)) { - return Status; - } - - // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which = is cacheable. - Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, - EFI_MEMORY_WC); - ASSERT_EFI_ERROR(Status); - if (EFI_ERROR(Status)) { - gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); - return Status; - } - - return EFI_SUCCESS; -} - -UINT32 -LcdPlatformGetMaxMode ( - VOID - ) -{ - // - // The following line will report correctly the total number of graphics= modes - // that could be supported by the graphics driver: - // - return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION)); -} - -EFI_STATUS -LcdPlatformSetMode ( - IN UINT32 ModeNumber - ) -{ - EFI_STATUS Status; - - if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { - return EFI_INVALID_PARAMETER; - } - - // Set the video mode oscillator - do { - Status =3D ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(= PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq); - } while (Status =3D=3D EFI_TIMEOUT); - if (EFI_ERROR(Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - // Set the DVI into the new mode - do { - Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mode= Number].Mode); - } while (Status =3D=3D EFI_TIMEOUT); - if (EFI_ERROR(Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - // Set the multiplexer - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); - if (EFI_ERROR(Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - return Status; -} - -EFI_STATUS -LcdPlatformQueryMode ( - IN UINT32 ModeNumber, - OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info - ) -{ - if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { - return EFI_INVALID_PARAMETER; - } - - Info->Version =3D 0; - Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; - Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; - Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; - - switch (mResolutions[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; - - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT(FALSE); - break; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -LcdPlatformGetTimings ( - IN UINT32 ModeNumber, - OUT UINT32* HRes, - OUT UINT32* HSync, - OUT UINT32* HBackPorch, - OUT UINT32* HFrontPorch, - OUT UINT32* VRes, - OUT UINT32* VSync, - OUT UINT32* VBackPorch, - OUT UINT32* VFrontPorch - ) -{ - if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { - return EFI_INVALID_PARAMETER; - } - - *HRes =3D mResolutions[ModeNumber].HorizontalResolution; - *HSync =3D mResolutions[ModeNumber].HSync; - *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; - *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; - *VRes =3D mResolutions[ModeNumber].VerticalResolution; - *VSync =3D mResolutions[ModeNumber].VSync; - *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; - *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; - - return EFI_SUCCESS; -} - -EFI_STATUS -LcdPlatformGetBpp ( - IN UINT32 ModeNumber, - OUT LCD_BPP * Bpp - ) -{ - if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { - return EFI_INVALID_PARAMETER; - } - - *Bpp =3D mResolutions[ModeNumber].Bpp; - - return EFI_SUCCESS; -} diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpres= sLib/HdLcdArmVExpressLib.inf deleted file mode 100644 index dff17e86fd3e..000000000000 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVEx= pressLib.inf +++ /dev/null @@ -1,45 +0,0 @@ -#/** @file -# -# Component description file for HdLcdArmLib module -# -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the B= SD License -# which accompanies this distribution. The full text of the license may = be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -# -#**/ - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D HdLcdArmVExpress - FILE_GUID =3D 535a720e-06c0-4bb9-b563-452216abbed4 - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D LcdPlatformLib - -[Sources.common] - -HdLcdArmVExpress.c - -[Packages] - MdePkg/MdePkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec - -[LibraryClasses] - ArmPlatformSysConfigLib - BaseLib - DxeServicesTableLib - -[Protocols] - gEfiEdidDiscoveredProtocolGuid # Produced - gEfiEdidActiveProtocolGuid # Produced - -[Pcd] - gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode - gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVEx= pressLib/PL111LcdArmVExpress.c deleted file mode 100644 index 3f3ceb3d2fa8..000000000000 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpress.c +++ /dev/null @@ -1,370 +0,0 @@ -/** @file - - Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
- This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -typedef struct { - UINT32 Mode; - UINT32 HorizontalResolution; - UINT32 VerticalResolution; - LCD_BPP Bpp; - UINT32 OscFreq; - - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; -} LCD_RESOLUTION; - - -LCD_RESOLUTION mResolutions[] =3D { - { // Mode 0 : VGA : 640 x 480 x 24 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_= OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH - }, - { // Mode 1 : SVGA : 800 x 600 x 24 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, S= VGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH - }, - { // Mode 2 : XGA : 1024 x 768 x 24 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_= OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH - }, - { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp - SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= SXGA_OSC_FREQUENCY/2), - SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, - SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH - }, - { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp - UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= UXGA_OSC_FREQUENCY/2), - UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, - UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH - }, - { // Mode 5 : HD : 1920 x 1080 x 24 bpp - HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC= _FREQUENCY/2), - HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, - HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH - }, - { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH - }, - { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_56= 5, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH - }, - { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH - }, - { // Mode 9 : VGA : 640 x 480 x 15 bpp - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH - }, - { // Mode 10 : SVGA : 800 x 600 x 15 bpp - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_55= 5, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH - }, - { // Mode 11 : XGA : 1024 x 768 x 15 bpp - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH - }, - { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derive= d from Linux Kernel Driver Settings - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = 63500000, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH - }, - { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode) - VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = VGA_OSC_FREQUENCY, - VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, - VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH - }, - { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode) - SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_44= 4, SVGA_OSC_FREQUENCY, - SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, - SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH - }, - { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode) - XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = XGA_OSC_FREQUENCY, - XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, - XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH - } -}; - -EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered =3D { - 0, - NULL -}; - -EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { - 0, - NULL -}; - - -EFI_STATUS -LcdPlatformInitializeDisplay ( - IN EFI_HANDLE Handle - ) -{ - EFI_STATUS Status; - - // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE); - if (!EFI_ERROR(Status)) { - // Install the EDID Protocols - Status =3D gBS->InstallMultipleProtocolInterfaces( - &Handle, - &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, - &gEfiEdidActiveProtocolGuid, &mEdidActive, - NULL - ); - } - - return Status; -} - -EFI_STATUS -LcdPlatformGetVram ( - OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, - OUT UINTN* VramSize - ) -{ - EFI_STATUS Status; - - Status =3D EFI_SUCCESS; - - // Is it on the motherboard or on the daughterboard? - switch(PL111_CLCD_SITE) { - - case ARM_VE_MOTHERBOARD_SITE: - *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOAR= D_BASE; - *VramSize =3D LCD_VRAM_SIZE; - break; - - case ARM_VE_DAUGHTERBOARD_1_SITE: - *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE; - *VramSize =3D LCD_VRAM_SIZE; - - // Allocate the VRAM from the DRAM so that nobody else uses it. - Status =3D gBS->AllocatePages( AllocateAddress, EfiBootServicesData, E= FI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); - if (EFI_ERROR(Status)) { - return Status; - } - - // Mark the VRAM as write-combining. The VRAM is inside the DRAM, whic= h is cacheable. - Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, - EFI_MEMORY_WC); - ASSERT_EFI_ERROR(Status); - if (EFI_ERROR(Status)) { - gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize)); - return Status; - } - break; - - default: - // Unsupported site - Status =3D EFI_UNSUPPORTED; - break; - } - - return Status; -} - -UINT32 -LcdPlatformGetMaxMode ( - VOID - ) -{ - // The following line will report correctly the total number of graphics= modes - // supported by the PL111CLCD. - //return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1; - - // However, on some platforms it is desirable to ignore some graphics mo= des. - // This could be because the specific implementation of PL111 has certai= n limitations. - - // Set the maximum mode allowed - return (PcdGet32(PcdPL111LcdMaxMode)); -} - -EFI_STATUS -LcdPlatformSetMode ( - IN UINT32 ModeNumber - ) -{ - EFI_STATUS Status; - UINT32 LcdSite; - UINT32 OscillatorId; - SYS_CONFIG_FUNCTION Function; - UINT32 SysId; - - if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { - return EFI_INVALID_PARAMETER; - } - - LcdSite =3D PL111_CLCD_SITE; - - switch(LcdSite) { - case ARM_VE_MOTHERBOARD_SITE: - Function =3D SYS_CFG_OSC; - OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; - break; - case ARM_VE_DAUGHTERBOARD_1_SITE: - Function =3D SYS_CFG_OSC_SITE1; - OscillatorId =3D (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId); - break; - default: - return EFI_UNSUPPORTED; - } - - // Set the video mode oscillator - Status =3D ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResol= utions[ModeNumber].OscFreq); - if (EFI_ERROR(Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - // The FVP foundation model does not have an LCD. - // On the FVP models the GIC variant in encoded in bits [15:12]. - // Note: The DVI Mode is not modelled by RTSM or FVP models. - SysId =3D MmioRead32 (ARM_VE_SYS_ID_REG); - if (SysId !=3D ARM_RTSM_SYS_ID) { - // Take out the FVP GIC variant to reduce the permutations. - SysId &=3D ~ARM_FVP_SYS_ID_VARIANT_MASK; - if (SysId !=3D ARM_FVP_BASE_BOARD_SYS_ID) { - // Set the DVI into the new mode - Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mo= deNumber].Mode); - if (EFI_ERROR(Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - } - } - - // Set the multiplexer - Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite); - if (EFI_ERROR(Status)) { - ASSERT_EFI_ERROR (Status); - return Status; - } - - return Status; -} - -EFI_STATUS -LcdPlatformQueryMode ( - IN UINT32 ModeNumber, - OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info - ) -{ - if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { - return EFI_INVALID_PARAMETER; - } - - Info->Version =3D 0; - Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; - Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; - Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; - - switch (mResolutions[ModeNumber].Bpp) { - case LCD_BITS_PER_PIXEL_24: - Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; - Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; - Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; - Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; - Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; - break; - - case LCD_BITS_PER_PIXEL_16_555: - case LCD_BITS_PER_PIXEL_16_565: - case LCD_BITS_PER_PIXEL_12_444: - case LCD_BITS_PER_PIXEL_8: - case LCD_BITS_PER_PIXEL_4: - case LCD_BITS_PER_PIXEL_2: - case LCD_BITS_PER_PIXEL_1: - default: - // These are not supported - ASSERT(FALSE); - break; - } - - return EFI_SUCCESS; -} - -EFI_STATUS -LcdPlatformGetTimings ( - IN UINT32 ModeNumber, - OUT UINT32* HRes, - OUT UINT32* HSync, - OUT UINT32* HBackPorch, - OUT UINT32* HFrontPorch, - OUT UINT32* VRes, - OUT UINT32* VSync, - OUT UINT32* VBackPorch, - OUT UINT32* VFrontPorch - ) -{ - if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { - return EFI_INVALID_PARAMETER; - } - - *HRes =3D mResolutions[ModeNumber].HorizontalResolution; - *HSync =3D mResolutions[ModeNumber].HSync; - *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; - *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; - *VRes =3D mResolutions[ModeNumber].VerticalResolution; - *VSync =3D mResolutions[ModeNumber].VSync; - *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; - *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; - - return EFI_SUCCESS; -} - -EFI_STATUS -LcdPlatformGetBpp ( - IN UINT32 ModeNumber, - OUT LCD_BPP * Bpp - ) -{ - if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { - return EFI_INVALID_PARAMETER; - } - - *Bpp =3D mResolutions[ModeNumber].Bpp; - - return EFI_SUCCESS; -} diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdA= rmVExpressLib/PL111LcdArmVExpressLib.inf deleted file mode 100644 index 658558ab1523..000000000000 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111Lcd= ArmVExpressLib.inf +++ /dev/null @@ -1,44 +0,0 @@ -#/** @file -# -# Component description file for ArmVeGraphicsDxe module -# -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the B= SD License -# which accompanies this distribution. The full text of the license may = be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -# -#**/ - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D PL111LcdArmVExpressLib - FILE_GUID =3D b7f06f20-496f-11e0-a8e8-0002a5d5c51b - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D LcdPlatformLib - -[Sources.common] - PL111LcdArmVExpress.c - -[Packages] - MdePkg/MdePkg.dec - ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - -[LibraryClasses] - ArmPlatformSysConfigLib - BaseLib - DxeServicesTableLib - -[Protocols] - gEfiEdidDiscoveredProtocolGuid # Produced - gEfiEdidActiveProtocolGuid # Produced - -[Pcd] - gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode - gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatf= ormPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c deleted file mode 100644 index 2bfe2c0fe2dc..000000000000 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ /dev/null @@ -1,133 +0,0 @@ -/** @file Lcd.c - - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#include -#include -#include -#include -#include - -#include - -#include "LcdGraphicsOutputDxe.h" - -/********************************************************************** - * - * This file contains all the bits of the Lcd that are - * platform independent. - * - **********************************************************************/ - -EFI_STATUS -LcdInitialize ( - IN EFI_PHYSICAL_ADDRESS VramBaseAddress - ) -{ - // Disable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); - - // Disable all interrupts - MmioWrite32(HDLCD_REG_INT_MASK, 0); - - // Define start of the VRAM. This never changes for any graphics mode - MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress); - - // Setup various registers that never change - MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8); - MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | = HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH); - MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_P= ER_PIXEL); - MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0)); - MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8)); - MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16)); - - return EFI_SUCCESS; -} - -EFI_STATUS -LcdSetMode ( - IN UINT32 ModeNumber - ) -{ - EFI_STATUS Status; - UINT32 HRes; - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VRes; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; - UINT32 BytesPerPixel; - LCD_BPP LcdBpp; - - - // Set the video mode timings and other relevant information - Status =3D LcdPlatformGetTimings (ModeNumber, - &HRes,&HSync,&HBackPorch,&HFrontPorch, - &VRes,&VSync,&VBackPorch,&VFrontPorch); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { - return EFI_DEVICE_ERROR; - } - - Status =3D LcdPlatformGetBpp (ModeNumber,&LcdBpp); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { - return EFI_DEVICE_ERROR; - } - - BytesPerPixel =3D GetBytesPerPixel(LcdBpp); - - // Disable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); - - // Update the frame buffer information with the new settings - MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel); - MmioWrite32(HDLCD_REG_FB_LINE_PITCH, HRes * BytesPerPixel); - MmioWrite32(HDLCD_REG_FB_LINE_COUNT, VRes - 1); - - // Set the vertical timing information - MmioWrite32(HDLCD_REG_V_SYNC, VSync); - MmioWrite32(HDLCD_REG_V_BACK_PORCH, VBackPorch); - MmioWrite32(HDLCD_REG_V_DATA, VRes - 1); - MmioWrite32(HDLCD_REG_V_FRONT_PORCH, VFrontPorch); - - // Set the horizontal timing information - MmioWrite32(HDLCD_REG_H_SYNC, HSync); - MmioWrite32(HDLCD_REG_H_BACK_PORCH, HBackPorch); - MmioWrite32(HDLCD_REG_H_DATA, HRes - 1); - MmioWrite32(HDLCD_REG_H_FRONT_PORCH, HFrontPorch); - - // Enable the controller - MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE); - - return EFI_SUCCESS; -} - -VOID -LcdShutdown ( - VOID - ) -{ - // Disable the controller - MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE); -} - -EFI_STATUS -LcdIdentify ( - VOID - ) -{ - return EFI_SUCCESS; -} diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutpu= tDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputD= xe.inf deleted file mode 100644 index 462d1fa402d7..000000000000 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf +++ /dev/null @@ -1,63 +0,0 @@ -#/** @file -# -# Component description file for HDLCD module -# -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the B= SD License -# which accompanies this distribution. The full text of the license may = be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -# -#**/ - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D HdLcdGraphicsDxe - FILE_GUID =3D ce660500-824d-11e0-ac72-0002a5d5c51b - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - ENTRY_POINT =3D LcdGraphicsOutputDxeInitialize - -[Sources.common] - LcdGraphicsOutputDxe.c - LcdGraphicsOutputBlt.c - HdLcd.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - -[LibraryClasses] - ArmLib - UefiLib - BaseLib - DebugLib - TimerLib - UefiDriverEntryPoint - UefiBootServicesTableLib - IoLib - BaseMemoryLib - LcdPlatformLib - -[Protocols] - gEfiDevicePathProtocolGuid - gEfiGraphicsOutputProtocolGuid # Produced - gEfiEdidDiscoveredProtocolGuid # Produced - gEfiEdidActiveProtocolGuid # Produced - gEfiEdidOverrideProtocolGuid # Produced - -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase - -[FeaturePcd] - gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices - -[Depex] - gEfiCpuArchProtocolGuid diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPl= atformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c deleted file mode 100644 index b5e113b844d4..000000000000 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c +++ /dev/null @@ -1,126 +0,0 @@ -/** @file PL111Lcd.c - - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#include -#include - -#include - -#include "LcdGraphicsOutputDxe.h" - -/********************************************************************** - * - * This file contains all the bits of the PL111 that are - * platform independent. - * - **********************************************************************/ - -EFI_STATUS -LcdIdentify ( - VOID - ) -{ - DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n", - PL111_REG_CLCD_PERIPH_ID_0)); - - // Check if this is a PL111 - if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) =3D=3D PL111_CLCD_PERIPH_ID_0= && - MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) =3D=3D PL111_CLCD_PERIPH_ID_1= && - (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) =3D=3D PL111_CLCD_PERI= PH_ID_2 && - MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) =3D=3D PL111_CLCD_PERIPH_ID_3= && - MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) =3D=3D PL111_CLCD_P_CELL_ID_0= && - MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) =3D=3D PL111_CLCD_P_CELL_ID_1= && - MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) =3D=3D PL111_CLCD_P_CELL_ID_2= && - MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) =3D=3D PL111_CLCD_P_CELL_ID_3= ) { - return EFI_SUCCESS; - } - return EFI_NOT_FOUND; -} - -EFI_STATUS -LcdInitialize ( - IN EFI_PHYSICAL_ADDRESS VramBaseAddress - ) -{ - // Define start of the VRAM. This never changes for any graphics mode - MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress); - MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buff= er - - // Disable all interrupts from the PL111 - MmioWrite32(PL111_REG_LCD_IMSC, 0); - - return EFI_SUCCESS; -} - -EFI_STATUS -LcdSetMode ( - IN UINT32 ModeNumber - ) -{ - EFI_STATUS Status; - UINT32 HRes; - UINT32 HSync; - UINT32 HBackPorch; - UINT32 HFrontPorch; - UINT32 VRes; - UINT32 VSync; - UINT32 VBackPorch; - UINT32 VFrontPorch; - UINT32 LcdControl; - LCD_BPP LcdBpp; - - // Set the video mode timings and other relevant information - Status =3D LcdPlatformGetTimings (ModeNumber, - &HRes,&HSync,&HBackPorch,&HFrontPorch, - &VRes,&VSync,&VBackPorch,&VFrontPorch); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { - return EFI_DEVICE_ERROR; - } - - Status =3D LcdPlatformGetBpp (ModeNumber,&LcdBpp); - ASSERT_EFI_ERROR (Status); - if (EFI_ERROR( Status )) { - return EFI_DEVICE_ERROR; - } - - // Disable the CLCD_LcdEn bit - LcdControl =3D MmioRead32( PL111_REG_LCD_CONTROL); - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1); - - // Set Timings - MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPo= rch, HSync, HRes)); - MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPo= rch, VSync, VRes)); - MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes)); - MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); - - // PL111_REG_LCD_CONTROL - LcdControl =3D PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CT= RL_LCD_TFT | PL111_CTRL_BGR; - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); - - // Turn on power to the LCD Panel - LcdControl |=3D PL111_CTRL_LCD_PWR; - MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); - - return EFI_SUCCESS; -} - -VOID -LcdShutdown ( - VOID - ) -{ - // Disable the controller - MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); -} diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOu= tputDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsO= utputDxe.inf deleted file mode 100644 index 003cc2ffa912..000000000000 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe= .inf +++ /dev/null @@ -1,59 +0,0 @@ -#/** @file -# -# Component description file for PL111LcdGraphicsOutputDxe module -# -# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
-# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the B= SD License -# which accompanies this distribution. The full text of the license may = be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -# -#**/ - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D PL111LcdGraphicsDxe - FILE_GUID =3D 407B4008-BF5B-11DF-9547-CF16E0D72085 - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - ENTRY_POINT =3D LcdGraphicsOutputDxeInitialize - -[Sources.common] - LcdGraphicsOutputDxe.c - LcdGraphicsOutputBlt.c - PL111Lcd.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - -[LibraryClasses] - ArmLib - UefiLib - BaseLib - DebugLib - TimerLib - UefiDriverEntryPoint - UefiBootServicesTableLib - IoLib - BaseMemoryLib - LcdPlatformLib - -[Protocols] - gEfiDevicePathProtocolGuid - gEfiGraphicsOutputProtocolGuid - -[FixedPcd] - gArmPlatformTokenSpaceGuid.PcdPL111LcdBase - -[FeaturePcd] - gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices - -[Depex] - gEfiCpuArchProtocolGuid diff --git a/ArmPlatformPkg/Include/Drivers/HdLcd.h b/ArmPlatformPkg/Includ= e/Drivers/HdLcd.h deleted file mode 100644 index 6df97a9dfee6..000000000000 --- a/ArmPlatformPkg/Include/Drivers/HdLcd.h +++ /dev/null @@ -1,89 +0,0 @@ -/** @file HDLcd.h - - Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD= License - which accompanies this distribution. The full text of the license may be= found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. - - **/ - -#ifndef _HDLCD_H_ -#define _HDLCD_H_ - -// -// HDLCD Controller Register Offsets -// - -#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x000) -#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x010) -#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x014) -#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x018) -#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x01C) -#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x100) -#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x104) -#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x108) -#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x10C) -#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x110) -#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x200) -#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x204) -#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x208) -#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x20C) -#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x210) -#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x214) -#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x218) -#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x21C) -#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x220) -#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x230) -#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x240) -#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x244) -#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x248) -#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBas= e) + 0x24C) - - -// -// HDLCD Values of registers -// - -// HDLCD Interrupt mask, clear and status register -#define HDLCD_DMA_END BIT0 /* DMA has finished read= ing a frame */ -#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */ -#define HDLCD_SYNC BIT2 /* Vertical sync */ -#define HDLCD_UNDERRUN BIT3 /* No Data available whi= le DATAEN active */ - -// CLCD_CONTROL Control register -#define HDLCD_DISABLE 0 -#define HDLCD_ENABLE BIT0 - -// Bus Options -#define HDLCD_BURST_1 BIT0 -#define HDLCD_BURST_2 BIT1 -#define HDLCD_BURST_4 BIT2 -#define HDLCD_BURST_8 BIT3 -#define HDLCD_BURST_16 BIT4 - -// Polarities - HIGH -#define HDLCD_VSYNC_HIGH BIT0 -#define HDLCD_HSYNC_HIGH BIT1 -#define HDLCD_DATEN_HIGH BIT2 -#define HDLCD_DATA_HIGH BIT3 -#define HDLCD_PXCLK_HIGH BIT4 -// Polarities - LOW (for completion and for ease of understanding the hard= ware settings) -#define HDLCD_VSYNC_LOW 0 -#define HDLCD_HSYNC_LOW 0 -#define HDLCD_DATEN_LOW 0 -#define HDLCD_DATA_LOW 0 -#define HDLCD_PXCLK_LOW 0 - -// Pixel Format -#define HDLCD_LITTLE_ENDIAN (0 << 31) -#define HDLCD_BIG_ENDIAN (1 << 31) - -// Number of bytes per pixel -#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3) - -#endif /* _HDLCD_H_ */ diff --git a/ArmPlatformPkg/Include/Drivers/PL111Lcd.h b/ArmPlatformPkg/Inc= lude/Drivers/PL111Lcd.h deleted file mode 100644 index 18e28af805f6..000000000000 --- a/ArmPlatformPkg/Include/Drivers/PL111Lcd.h +++ /dev/null @@ -1,149 +0,0 @@ -/** @file PL111Lcd.h - - Copyright (c) 2011, ARM Ltd. All rights reserved.
- This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD= License - which accompanies this distribution. The full text of the license may be= found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. - - **/ - -#ifndef _PL111LCD_H__ -#define _PL111LCD_H__ - -/********************************************************************** - * - * This header file contains all the bits of the PL111 that are - * platform independent. - * - **********************************************************************/ - -// Controller Register Offsets -#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x000) -#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x004) -#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x008) -#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x00C) -#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x010) -#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x014) -#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x018) -#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x01C) -#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x020) -#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x024) -#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x028) -#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x02C) -#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x030) -#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0x200) - -// Identification Register Offsets -#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFE0) -#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFE4) -#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFE8) -#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFEC) -#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFF0) -#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFF4) -#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFF8) -#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBas= e) + 0xFFC) - -#define PL111_CLCD_PERIPH_ID_0 0x11 -#define PL111_CLCD_PERIPH_ID_1 0x11 -#define PL111_CLCD_PERIPH_ID_2 0x04 -#define PL111_CLCD_PERIPH_ID_3 0x00 -#define PL111_CLCD_P_CELL_ID_0 0x0D -#define PL111_CLCD_P_CELL_ID_1 0xF0 -#define PL111_CLCD_P_CELL_ID_2 0x05 -#define PL111_CLCD_P_CELL_ID_3 0xB1 - -/**********************************************************************/ - -// Register components (register bits) - -// This should make life easier to program specific settings in the differ= ent registers -// by simplifying the setting up of the individual bits of each register -// and then assembling the final register value. - -/**********************************************************************/ - -// Register: PL111_REG_LCD_TIMING_0 -#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24)= | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-= 1) << 2)) - -// Register: PL111_REG_LCD_TIMING_1 -#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24)= | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1)) - -// Register: PL111_REG_LCD_TIMING_2 -#define PL111_BIT_SHIFT_PCD_HI 27 -#define PL111_BIT_SHIFT_BCD 26 -#define PL111_BIT_SHIFT_CPL 16 -#define PL111_BIT_SHIFT_IOE 14 -#define PL111_BIT_SHIFT_IPC 13 -#define PL111_BIT_SHIFT_IHS 12 -#define PL111_BIT_SHIFT_IVS 11 -#define PL111_BIT_SHIFT_ACB 6 -#define PL111_BIT_SHIFT_CLKSEL 5 -#define PL111_BIT_SHIFT_PCD_LO 0 - -#define PL111_BCD (1 << 26) -#define PL111_IPC (1 << 13) -#define PL111_IHS (1 << 12) -#define PL111_IVS (1 << 11) - -#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC |= PL111_IHS | PL111_IVS | (((hor_res)-1) << 16)) - -// Register: PL111_REG_LCD_TIMING_3 -#define PL111_BIT_SHIFT_LEE 16 -#define PL111_BIT_SHIFT_LED 0 - -#define PL111_CTRL_WATERMARK (1 << 16) -#define PL111_CTRL_LCD_V_COMP (1 << 12) -#define PL111_CTRL_LCD_PWR (1 << 11) -#define PL111_CTRL_BEPO (1 << 10) -#define PL111_CTRL_BEBO (1 << 9) -#define PL111_CTRL_BGR (1 << 8) -#define PL111_CTRL_LCD_DUAL (1 << 7) -#define PL111_CTRL_LCD_MONO_8 (1 << 6) -#define PL111_CTRL_LCD_TFT (1 << 5) -#define PL111_CTRL_LCD_BW (1 << 4) -#define PL111_CTRL_LCD_1BPP (0 << 1) -#define PL111_CTRL_LCD_2BPP (1 << 1) -#define PL111_CTRL_LCD_4BPP (2 << 1) -#define PL111_CTRL_LCD_8BPP (3 << 1) -#define PL111_CTRL_LCD_16BPP (4 << 1) -#define PL111_CTRL_LCD_24BPP (5 << 1) -#define PL111_CTRL_LCD_16BPP_565 (6 << 1) -#define PL111_CTRL_LCD_12BPP_444 (7 << 1) -#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1) -#define PL111_CTRL_LCD_EN 1 - -/**********************************************************************/ - -// Register: PL111_REG_LCD_TIMING_0 -#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24) -#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16) -#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) -#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2) - -// Register: PL111_REG_LCD_TIMING_1 -#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24) -#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16) -#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10) -#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC) - -// Register: PL111_REG_LCD_TIMING_2 -#define PL111_BIT_MASK_PCD_HI 0xF8000000 -#define PL111_BIT_MASK_BCD 0x04000000 -#define PL111_BIT_MASK_CPL 0x03FF0000 -#define PL111_BIT_MASK_IOE 0x00004000 -#define PL111_BIT_MASK_IPC 0x00002000 -#define PL111_BIT_MASK_IHS 0x00001000 -#define PL111_BIT_MASK_IVS 0x00000800 -#define PL111_BIT_MASK_ACB 0x000007C0 -#define PL111_BIT_MASK_CLKSEL 0x00000020 -#define PL111_BIT_MASK_PCD_LO 0x0000001F - -// Register: PL111_REG_LCD_TIMING_3 -#define PL111_BIT_MASK_LEE 0x00010000 -#define PL111_BIT_MASK_LED 0x0000007F - -#endif /* _PL111LCD_H__ */ --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel