From nobody Wed Dec 25 04:16:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512425602945803.1605446524628; Mon, 4 Dec 2017 14:13:22 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 90481221523A5; Mon, 4 Dec 2017 14:08:50 -0800 (PST) Received: from mail-wm0-x233.google.com (mail-wm0-x233.google.com [IPv6:2a00:1450:400c:c09::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7F0A620359E96 for ; Mon, 4 Dec 2017 14:08:48 -0800 (PST) Received: by mail-wm0-x233.google.com with SMTP id g75so8645772wme.0 for ; Mon, 04 Dec 2017 14:13:18 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id i3sm12021318wre.33.2017.12.04.14.13.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Dec 2017 14:13:13 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::233; helo=mail-wm0-x233.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+S0cCGKHIEXEfbh85im4EVhstlXkx4VjsrIV+haNtIM=; b=PKTensKV8w4X+yqOx2ZpQPPQnDB0BcoELYpR5Su0zQJYRCesxFB94uBkyRDm4gplc/ ZaOooTLQmzkv+9J3T+Ymc0yynxuci5P8+g6lvDLXDneoPoWS072EK5juZRx4qbfv+ool 6pHFNsVj2T4Tqzn4BMq5PSvhlGG+cGU05ZoEo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+S0cCGKHIEXEfbh85im4EVhstlXkx4VjsrIV+haNtIM=; b=CtgvF2eUFRrf4rJbw3wP6DpuZ2QAYV2X7cIBTYALufAmFrE+p/jA09EG0GJaaCAkq8 Q/MeH7Pgn+4lK1SEKQkpky2Y2jjebKdR9Zy/iYuz2ypXKnXHtotl5AgA27DoQimXf7mI YF0zmk/K+gyVHVoHr2XUNARqeprz09Z/UypPXrVmK89ED/zGzdPh+gRO/K625FUbJST8 N10FG0gwsDhvIocJKiajAFUURPEUhgK09cZIzBO13jHGWJ/fyWE00LhFFR2AGXs2uoGb Rdn4oubK8wrdt4Vq9uFKQDBzVnxejA/YkzF+L46lcp/YFoeaEa38tSoJ85lAW9ThxHCY BRmA== X-Gm-Message-State: AKGB3mK7ABlYuvNFNCORk0uUgog1UUZQhvTt19NgAl1ekAXIPHUWgfpE 7TPCmbt24s2uScjiV4jxeON4nHGZP9E= X-Google-Smtp-Source: AGs4zMbilQORPWbaPRpo1PFVNH5+PhvrBS2EIYHh6/7bj+owokzVX5QxFJm3+hPMDyVwm0FpMKbe6A== X-Received: by 10.28.9.195 with SMTP id 186mr3734792wmj.122.1512425594696; Mon, 04 Dec 2017 14:13:14 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Mon, 4 Dec 2017 22:12:34 +0000 Message-Id: <20171204221235.11807-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171204221235.11807-1-ard.biesheuvel@linaro.org> References: <20171204221235.11807-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v3 edk2-platforms 1/2] Platform/ARM/VExpress: import VExpressPkg from EDK2 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Import the pieces that are closely tied to the ARM Versatile Express development platforms into edk2-platforms, so they can be removed from upstream EDK2. Note that this includes the LCD drivers, and the ArmPlatformSysConfigLib library class, which is not used anywhere else. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf = | 3 +- Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc = | 29 +- Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf = | 6 +- Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc = | 19 +- Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf = | 2 +- Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc = | 8 +- Platform/ARM/VExpressPkg/ArmVExpressPkg.dec = | 60 +++ Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c = | 90 ++++ Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf = | 40 ++ Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.c = | 38 ++ Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.inf = | 37 ++ Platform/ARM/VExpressPkg/Drivers/ArmVExpressFastBootDxe/ArmVExpressFastBoo= t.c | 519 ++++++++++++++++++++ Platform/ARM/VExpressPkg/Drivers/ArmVExpressFastBootDxe/ArmVExpressFastBoo= tDxe.inf | 51 ++ Platform/ARM/VExpressPkg/Include/Library/ArmPlatformSysConfigLib.h = | 63 +++ Platform/ARM/VExpressPkg/Include/Library/LcdPlatformLib.h = | 221 +++++++++ Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h = | 154 ++++++ Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h = | 79 +++ Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h = | 140 ++++++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf= | 54 ++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c = | 182 +++++++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.S = | 81 +++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helper.asm= | 96 ++++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c = | 182 +++++++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/AArch64/RTSMHelper.S = | 61 +++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.S = | 97 ++++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.asm = | 118 +++++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf = | 63 +++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf = | 59 +++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c = | 195 ++++++++ Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c = | 161 ++++++ Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysCon= fig.c | 273 ++++++++++ Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysCon= figLib.inf | 35 ++ Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigRuntimeLib/ArmVExpres= sSysConfigRuntimeLib.c | 283 +++++++++++ Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigRuntimeLib/ArmVExpres= sSysConfigRuntimeLib.inf | 37 ++ Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c = | 285 +++++++++++ Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.i= nf | 45 ++ Platform/ARM/VExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpres= s.c | 84 ++++ Platform/ARM/VExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpres= sLib.inf | 33 ++ Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= s.c | 370 ++++++++++++++ Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpres= sLib.inf | 44 ++ Platform/ARM/VExpressPkg/Library/ResetSystemLib/ResetSystemLib.c = | 111 +++++ Platform/ARM/VExpressPkg/Library/ResetSystemLib/ResetSystemLib.inf = | 36 ++ 42 files changed, 4509 insertions(+), 35 deletions(-) diff --git a/Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf b/Platform/= ARM/VExpressPkg/AcpiTables/AcpiTables.inf index cc0f06f53323..35685274a041 100644 --- a/Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf +++ b/Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf @@ -31,11 +31,10 @@ [Sources] [Packages] ArmPkg/ArmPkg.dec ArmPlatformPkg/ArmPlatformPkg.dec - ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec - + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec =20 [FixedPcd] gArmTokenSpaceGuid.PcdGicDistributorBase diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc b/Platform/A= RM/VExpressPkg/ArmVExpress-CTA15-A7.dsc index 98513b282fa7..3be4d9d25ff5 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc +++ b/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.dsc @@ -40,22 +40,21 @@ [Defines] [LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf - ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15= -A7/ArmVExpressLib.inf + ArmPlatformLib|Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/A= rmVExpressLib.inf =20 - ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpres= sSysConfigLib/ArmVExpressSysConfigLib.inf - NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVEx= pressLib/NorFlashArmVExpressLib.inf + ArmPlatformSysConfigLib|Platform/ARM/VExpressPkg/Library/ArmVExpressSysC= onfigLib/ArmVExpressSysConfigLib.inf =20 - #DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTime= rLib/DebugAgentTimerLib.inf + #DebugAgentTimerLib|Platform/ARM/VExpressPkg/Library/DebugAgentTimerLib/= DebugAgentTimerLib.inf =20 # ARM General Interrupt Driver in Secure and Non-secure ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf =20 - LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib= /HdLcdArmVExpressLib.inf + LcdPlatformLib|Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLc= dArmVExpressLib.inf =20 ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf =20 [LibraryClasses.common.DXE_RUNTIME_DRIVER] - ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpres= sSysConfigRuntimeLib/ArmVExpressSysConfigRuntimeLib.inf + ArmPlatformSysConfigLib|Platform/ARM/VExpressPkg/Library/ArmVExpressSysC= onfigRuntimeLib/ArmVExpressSysConfigRuntimeLib.inf =20 [LibraryClasses.ARM] # @@ -64,7 +63,7 @@ [LibraryClasses.ARM] # syscfg MMIO register implementation on ARM. # This will not work at actual runtime. # - ResetSystemLib|ArmPlatformPkg/ArmVExpressPkg/Library/ResetSystemLib/Rese= tSystemLib.inf + ResetSystemLib|Platform/ARM/VExpressPkg/Library/ResetSystemLib/ResetSyst= emLib.inf =20 [BuildOptions] !ifdef ARM_BIGLITTLE_TC2 @@ -72,11 +71,11 @@ [BuildOptions] *_*_ARM_PP_FLAGS =3D -DARM_BIGLITTLE_TC2=3D1 !endif =20 - RVCT:*_*_ARM_PLATFORM_FLAGS =3D=3D --cpu Cortex-A15 -I$(WORKSPACE)/ArmPl= atformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressP= kg/Include/Platform/CTA15-A7 + RVCT:*_*_ARM_PLATFORM_FLAGS =3D=3D --cpu Cortex-A15 -I$(WORKSPACE)/Platf= orm/ARM/VExpressPkg/Include/Platform/CTA15-A7 =20 - GCC:*_*_ARM_PLATFORM_FLAGS =3D=3D -mcpu=3Dcortex-a15 -I$(WORKSPACE)/ArmP= latformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpress= Pkg/Include/Platform/CTA15-A7 + GCC:*_*_ARM_PLATFORM_FLAGS =3D=3D -mcpu=3Dcortex-a15 -I$(WORKSPACE)/Plat= form/ARM/VExpressPkg/Include/Platform/CTA15-A7 =20 - XCODE:*_*_ARM_PLATFORM_FLAGS =3D -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpre= ssPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform= /CTA15-A7 + XCODE:*_*_ARM_PLATFORM_FLAGS =3D -I$(WORKSPACE)/Platform/ARM/VExpressPkg= /Include/Platform/CTA15-A7 =20 ##########################################################################= ###### # @@ -156,8 +155,8 @@ [PcdsFixedAtBuild.common] =20 !ifdef ARM_BIGLITTLE_TC2 ## PL111 Lcd & HdLcd - gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000 - gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x2B000000 + gArmVExpressTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000 + gArmVExpressTokenSpaceGuid.PcdArmHdLcdBase|0x2B000000 gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|5 !endif =20 @@ -206,7 +205,7 @@ [Components.common] # ArmPlatformPkg/PrePi/PeiMPCore.inf { - ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibC= TA15-A7/ArmVExpressLib.inf + ArmPlatformLib|Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-= A7/ArmVExpressLib.inf } =20 # @@ -245,7 +244,7 @@ [Components.common] =20 ArmPkg/Drivers/ArmGic/ArmGicDxe.inf ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf - #ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.i= nf + #ArmplatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.i= nf ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf ArmPkg/Drivers/TimerDxe/TimerDxe.inf ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf @@ -253,7 +252,7 @@ [Components.common] # # Platform # - ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.inf + Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.inf =20 # # Filesystems diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf b/Platform/A= RM/VExpressPkg/ArmVExpress-CTA15-A7.fdf index 3c75a51570b8..5ceba5fa13c3 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf +++ b/Platform/ARM/VExpressPkg/ArmVExpress-CTA15-A7.fdf @@ -104,7 +104,7 @@ [FV.FvMain] # # Platform # - INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.inf + INF Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.inf =20 # # Multimedia Card Interface @@ -140,7 +140,7 @@ [FV.FvMain] # INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransport= UsbDxe.inf - INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressFastBootDxe/ArmVExpressFast= BootDxe.inf + INF Platform/ARM/VExpressPkg/Drivers/ArmVExpressFastBootDxe/ArmVExpressF= astBootDxe.inf =20 # ACPI Support INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf @@ -178,7 +178,7 @@ [FV.FvMain] =20 # Example to add a Device Tree to the Firmware Volume #FILE FREEFORM =3D PCD(gArmVExpressTokenSpaceGuid.PcdFdtVExpressHwA15x2A= 7x3) { - # SECTION RAW =3D ArmPlatformPkg/ArmVExpressPkg/Fdts/vexpress-v2p-ca15_= a7.dtb + # SECTION RAW =3D Platform/ARM/VExpressPkg/Fdts/vexpress-v2p-ca15_a7.dtb #} =20 [FV.FVMAIN_COMPACT] diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc b/Platfor= m/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc index a04159bb9741..3dc74ffe9df5 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc +++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc @@ -41,13 +41,12 @@ [Defines] =20 [LibraryClasses.common] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf - ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/= ArmVExpressLib.inf + ArmPlatformLib|Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVE= xpressLib.inf ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf =20 - ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpres= sSysConfigLib/ArmVExpressSysConfigLib.inf - NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVEx= pressLib/NorFlashArmVExpressLib.inf + ArmPlatformSysConfigLib|Platform/ARM/VExpressPkg/Library/ArmVExpressSysC= onfigLib/ArmVExpressSysConfigLib.inf !ifdef EDK2_ENABLE_PL111 - LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf + LcdPlatformLib|Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpressLib.inf !endif =20 # Virtio Support @@ -60,16 +59,16 @@ [LibraryClasses.common] DtPlatformDtbLoaderLib|Platform/ARM/VExpressPkg/Library/ArmVExpressDtPla= tformDtbLoaderLib/ArmVExpressDtPlatformDtbLoaderLib.inf =20 [LibraryClasses.common.DXE_RUNTIME_DRIVER] - ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpres= sSysConfigRuntimeLib/ArmVExpressSysConfigRuntimeLib.inf + ArmPlatformSysConfigLib|Platform/ARM/VExpressPkg/Library/ArmVExpressSysC= onfigRuntimeLib/ArmVExpressSysConfigRuntimeLib.inf =20 [LibraryClasses.common.SEC] - ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/= ArmVExpressLibSec.inf + ArmPlatformLib|Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVE= xpressLibSec.inf =20 [LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION= , LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVE= R] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf =20 [BuildOptions] - GCC:*_*_AARCH64_PLATFORM_FLAGS =3D=3D -I$(WORKSPACE)/ArmPlatformPkg/ArmV= ExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Pla= tform/RTSM + GCC:*_*_AARCH64_PLATFORM_FLAGS =3D=3D -I$(WORKSPACE)/Platform/ARM/VExpre= ssPkg/Include/Platform/RTSM =20 =20 ##########################################################################= ###### @@ -141,7 +140,7 @@ [PcdsFixedAtBuild.common] =20 !ifdef EDK2_ENABLE_PL111 ## PL111 Versatile Express Motherboard controller - gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000 + gArmVExpressTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000 !endif =20 ## PL180 MMC/SD card controller @@ -193,7 +192,7 @@ [Components.common] # UEFI is placed in RAM by bootloader ArmPlatformPkg/PrePi/PeiUniCore.inf { - ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibR= TSM/ArmVExpressLib.inf + ArmPlatformLib|Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/A= rmVExpressLib.inf } !else # UEFI lives in FLASH and copies itself to RAM @@ -295,7 +294,7 @@ [Components.common] # # Platform Driver # - ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf + Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf OvmfPkg/VirtioBlkDxe/VirtioBlk.inf =20 # diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf b/Platfor= m/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf index 1084eda3d367..0bac8ae91dab 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf +++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf @@ -145,7 +145,7 @@ [FV.FvMain] # # Platform Driver # - INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf + INF Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf =20 !ifdef EDK2_ENABLE_SMSC_91X diff --git a/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc b/Platform/ARM/VE= xpressPkg/ArmVExpress.dsc.inc index 1d6cd79333ef..5a3b787afb89 100644 --- a/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc +++ b/Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc @@ -79,12 +79,12 @@ [LibraryClasses.common] =20 # Versatile Express Specific Libraries PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf - ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpres= sSysConfigLib/ArmVExpressSysConfigLib.inf - NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVEx= pressLib/NorFlashArmVExpressLib.inf + ArmPlatformSysConfigLib|Platform/ARM/VExpressPkg/Library/ArmVExpressSysC= onfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|Platform/ARM/VExpressPkg/Library/NorFlashArmVExpress= Lib/NorFlashArmVExpressLib.inf ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf !ifdef EDK2_ENABLE_PL111 # ARM PL111 Lcd Driver - LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf + LcdPlatformLib|Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpressLib.inf !endif # ARM PL031 RTC Driver RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealT= imeClockLib.inf @@ -460,7 +460,7 @@ [Components.common] # EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbD= xe.inf - ArmPlatformPkg/ArmVExpressPkg/ArmVExpressFastBootDxe/ArmVExpressFastBoot= Dxe.inf + Platform/ARM/VExpressPkg/Drivers/ArmVExpressFastBootDxe/ArmVExpressFastB= ootDxe.inf =20 # FV Filesystem MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf diff --git a/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec b/Platform/ARM/VEx= pressPkg/ArmVExpressPkg.dec new file mode 100644 index 000000000000..4c004275d2e2 --- /dev/null +++ b/Platform/ARM/VExpressPkg/ArmVExpressPkg.dec @@ -0,0 +1,60 @@ +#/** @file +# Arm Versatile Express package. +# +# Copyright (c) 2012-2015, ARM Limited. All rights reserved. +# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D ArmVExpressPkg + PACKAGE_GUID =3D 9c0aaed4-74c5-4043-b417-a3223814ce76 + PACKAGE_VERSION =3D 0.1 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package + +[LibraryClasses] + ArmPlatformSysConfigLib|Include/Library/ArmPlatformSysConfigLib.h + LcdPlatformLib|Include/Library/LcdPlatformLib.h + +[Guids.common] + gArmVExpressTokenSpaceGuid =3D { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4,= 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } } + +[PcdsFeatureFlag.common] + +[PcdsFixedAtBuild.common] + # + # MaxMode must be one number higher than the actual max mode, + # i.e. for actual maximum mode 2, set the value to 3. + # + # For a list of mode numbers look in LcdArmVExpress.c + # + gArmVExpressTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000001 + gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode|3|UINT32|0x00000002 + gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId|1|UINT32|0x00000003 + + gArmVExpressTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000004 + gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|0|UINT32|0x00000005 + + # + # Device path of block device on which Fastboot will flash partitions + # + gArmVExpressTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath|""|VOID*|0x00= 000006 diff --git a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c b/= Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c new file mode 100644 index 000000000000..7827c50d8bbf --- /dev/null +++ b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c @@ -0,0 +1,90 @@ +/** @file + + Copyright (c) 2013-2015, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include +#include +#include +#include +#include + +#include + +#define ARM_FVP_BASE_VIRTIO_BLOCK_BASE 0x1c130000 + +#pragma pack(1) +typedef struct { + VENDOR_DEVICE_PATH Vendor; + EFI_DEVICE_PATH_PROTOCOL End; +} VIRTIO_BLK_DEVICE_PATH; +#pragma pack() + +VIRTIO_BLK_DEVICE_PATH mVirtioBlockDevicePath =3D +{ + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)( sizeof(VENDOR_DEVICE_PATH) ), + (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8) + } + }, + EFI_CALLER_ID_GUID, + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + sizeof (EFI_DEVICE_PATH_PROTOCOL), + 0 + } + } +}; + +/** + * Generic UEFI Entrypoint for 'ArmFvpDxe' driver + * See UEFI specification for the details of the parameters + */ +EFI_STATUS +EFIAPI +ArmFvpInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status =3D gBS->InstallProtocolInterface (&ImageHandle, + &gEfiDevicePathProtocolGuid, EFI_NATIVE_INTERFACE, + &mVirtioBlockDevicePath); + if (EFI_ERROR (Status)) { + return Status; + } + + // Declare the Virtio BlockIo device + Status =3D VirtioMmioInstallDevice (ARM_FVP_BASE_VIRTIO_BLOCK_BASE, Imag= eHandle); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "ArmFvpDxe: Failed to install Virtio block device= \n")); + } + + // Install dynamic Shell command to run baremetal binaries. + Status =3D ShellDynCmdRunAxfInstall (ImageHandle); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "ArmFvpDxe: Failed to install ShellDynCmdRunAxf\n= ")); + } + + return Status; +} diff --git a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf = b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf new file mode 100644 index 000000000000..3b19028dd982 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf @@ -0,0 +1,40 @@ +#/** @file +# +# Copyright (c) 2013-2015, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010006 + BASE_NAME =3D ArmFvpDxe + FILE_GUID =3D 405b2307-6839-4d52-aeb9-bece64252800 + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ArmFvpInitialise + +[Sources.common] + ArmFvpDxe.c + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + OvmfPkg/OvmfPkg.dec + Platform/ARM/ARM.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + ArmShellCmdRunAxfLib + BaseMemoryLib + UefiDriverEntryPoint + UefiBootServicesTableLib + VirtioMmioDeviceLib + diff --git a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.c b/P= latform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.c new file mode 100644 index 000000000000..19efa3c23dea --- /dev/null +++ b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.c @@ -0,0 +1,38 @@ +/** @file + + Copyright (c) 2013-2015, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include + +/** + * Generic UEFI Entrypoint for 'ArmHwDxe' driver + * See UEFI specification for the details of the parameters + */ +EFI_STATUS +EFIAPI +ArmHwInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // Install dynamic Shell command to run baremetal binaries. + Status =3D ShellDynCmdRunAxfInstall (ImageHandle); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "ArmHwDxe: Failed to install ShellDynCmdRunAxf\n"= )); + } + + return Status; +} diff --git a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.inf b= /Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.inf new file mode 100644 index 000000000000..1ecdbb0b231e --- /dev/null +++ b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmHwDxe.inf @@ -0,0 +1,37 @@ +#/** @file +# +# Copyright (c) 2013-2015, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010006 + BASE_NAME =3D ArmHwDxe + FILE_GUID =3D fe61bb5f-1b67-4c24-b346-73db42e873e5 + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ArmHwInitialise + +[Sources.common] + ArmHwDxe.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmShellCmdRunAxfLib + DxeServicesTableLib + MemoryAllocationLib + UefiDriverEntryPoint + +[Protocols] + gEfiDevicePathProtocolGuid diff --git a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressFastBootDxe/ArmVEx= pressFastBoot.c b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressFastBootDxe/A= rmVExpressFastBoot.c new file mode 100644 index 000000000000..a01bf3c671ad --- /dev/null +++ b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressFastBootDxe/ArmVExpressFa= stBoot.c @@ -0,0 +1,519 @@ +/** @file + + Copyright (c) 2014, ARM Ltd. All rights reserved.
+ Copyright (c) 2016, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +/* + Implementation of the Android Fastboot Platform protocol, to be used by = the + Fastboot UEFI application, for ARM Versatile Express platforms. +*/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define FLASH_DEVICE_PATH_SIZE(DevPath) ( GetDevicePathSize (DevPath) - \ + sizeof (EFI_DEVICE_PATH_PROTOC= OL)) + +#define PARTITION_NAME_MAX_LENGTH 72/2 + +#define IS_ALPHA(Char) (((Char) <=3D L'z' && (Char) >=3D L'a') || \ + ((Char) <=3D L'Z' && (Char) >=3D L'Z')) + +typedef struct _FASTBOOT_PARTITION_LIST { + LIST_ENTRY Link; + CHAR16 PartitionName[PARTITION_NAME_MAX_LENGTH]; + EFI_HANDLE PartitionHandle; +} FASTBOOT_PARTITION_LIST; + +STATIC LIST_ENTRY mPartitionListHead; + +/* + Helper to free the partition list +*/ +STATIC +VOID +FreePartitionList ( + VOID + ) +{ + FASTBOOT_PARTITION_LIST *Entry; + FASTBOOT_PARTITION_LIST *NextEntry; + + Entry =3D (FASTBOOT_PARTITION_LIST *) GetFirstNode (&mPartitionListHead); + while (!IsNull (&mPartitionListHead, &Entry->Link)) { + NextEntry =3D (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionList= Head, &Entry->Link); + + RemoveEntryList (&Entry->Link); + FreePool (Entry); + + Entry =3D NextEntry; + } +} +/* + Read the PartitionName fields from the GPT partition entries, putting th= em + into an allocated array that should later be freed. +*/ +STATIC +EFI_STATUS +ReadPartitionEntries ( + IN EFI_BLOCK_IO_PROTOCOL *BlockIo, + OUT EFI_PARTITION_ENTRY **PartitionEntries + ) +{ + UINTN EntrySize; + UINTN NumEntries; + UINTN BufferSize; + UINT32 MediaId; + EFI_PARTITION_TABLE_HEADER *GptHeader; + EFI_STATUS Status; + + MediaId =3D BlockIo->Media->MediaId; + + // + // Read size of Partition entry and number of entries from GPT header + // + + GptHeader =3D AllocatePool (BlockIo->Media->BlockSize); + if (GptHeader =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status =3D BlockIo->ReadBlocks (BlockIo, MediaId, 1, BlockIo->Media->Blo= ckSize, (VOID *) GptHeader); + if (EFI_ERROR (Status)) { + return Status; + } + + // Check there is a GPT on the media + if (GptHeader->Header.Signature !=3D EFI_PTAB_HEADER_ID || + GptHeader->MyLBA !=3D 1) { + DEBUG ((EFI_D_ERROR, + "Fastboot platform: No GPT on flash. " + "Fastboot on Versatile Express does not support MBR.\n" + )); + return EFI_DEVICE_ERROR; + } + + EntrySize =3D GptHeader->SizeOfPartitionEntry; + NumEntries =3D GptHeader->NumberOfPartitionEntries; + + FreePool (GptHeader); + + ASSERT (EntrySize !=3D 0); + ASSERT (NumEntries !=3D 0); + + BufferSize =3D ALIGN_VALUE (EntrySize * NumEntries, BlockIo->Media->Bloc= kSize); + *PartitionEntries =3D AllocatePool (BufferSize); + if (PartitionEntries =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status =3D BlockIo->ReadBlocks (BlockIo, MediaId, 2, BufferSize, (VOID *= ) *PartitionEntries); + if (EFI_ERROR (Status)) { + FreePool (PartitionEntries); + return Status; + } + + return Status; +} + + +/* + Do any initialisation that needs to be done in order to be able to respo= nd to + commands. + + @retval EFI_SUCCESS Initialised successfully. + @retval !EFI_SUCCESS Error in initialisation. +*/ +STATIC +EFI_STATUS +ArmFastbootPlatformInit ( + VOID + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *FlashDevicePath; + EFI_DEVICE_PATH_PROTOCOL *FlashDevicePathDup; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_DEVICE_PATH_PROTOCOL *NextNode; + HARDDRIVE_DEVICE_PATH *PartitionNode; + UINTN NumHandles; + EFI_HANDLE *AllHandles; + UINTN LoopIndex; + EFI_HANDLE FlashHandle; + EFI_BLOCK_IO_PROTOCOL *FlashBlockIo; + EFI_PARTITION_ENTRY *PartitionEntries; + FASTBOOT_PARTITION_LIST *Entry; + + InitializeListHead (&mPartitionListHead); + + // + // Get EFI_HANDLES for all the partitions on the block devices pointed t= o by + // PcdFastbootFlashDevicePath, also saving their GPT partition labels. + // We will use these labels as the key in ArmFastbootPlatformFlashPartit= ion. + // There's no way to find all of a device's children, so we get every ha= ndle + // in the system supporting EFI_BLOCK_IO_PROTOCOL and then filter out on= es + // that don't represent partitions on the flash device. + // + + FlashDevicePath =3D ConvertTextToDevicePath ((CHAR16*)FixedPcdGetPtr (Pc= dAndroidFastbootNvmDevicePath)); + + // + // Open the Disk IO protocol on the flash device - this will be used to = read + // partition names out of the GPT entries + // + // Create another device path pointer because LocateDevicePath will modi= fy it. + FlashDevicePathDup =3D FlashDevicePath; + Status =3D gBS->LocateDevicePath (&gEfiBlockIoProtocolGuid, &FlashDevice= PathDup, &FlashHandle); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Warning: Couldn't locate Android NVM device (sta= tus: %r)\n", Status)); + // Failing to locate partitions should not prevent to do other Android= FastBoot actions + return EFI_SUCCESS; + } + + Status =3D gBS->OpenProtocol ( + FlashHandle, + &gEfiBlockIoProtocolGuid, + (VOID **) &FlashBlockIo, + gImageHandle, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Fastboot platform: Couldn't open Android NVM dev= ice (status: %r)\n", Status)); + return EFI_DEVICE_ERROR; + } + + // Read the GPT partition entry array into memory so we can get the part= ition names + Status =3D ReadPartitionEntries (FlashBlockIo, &PartitionEntries); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Warning: Failed to read partitions from Android = NVM device (status: %r)\n", Status)); + // Failing to locate partitions should not prevent to do other Android= FastBoot actions + return EFI_SUCCESS; + } + + // Get every Block IO protocol instance installed in the system + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiBlockIoProtocolGuid, + NULL, + &NumHandles, + &AllHandles + ); + ASSERT_EFI_ERROR (Status); + + // Filter out handles that aren't children of the flash device + for (LoopIndex =3D 0; LoopIndex < NumHandles; LoopIndex++) { + // Get the device path for the handle + Status =3D gBS->OpenProtocol ( + AllHandles[LoopIndex], + &gEfiDevicePathProtocolGuid, + (VOID **) &DevicePath, + gImageHandle, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + ASSERT_EFI_ERROR (Status); + + // Check if it is a sub-device of the flash device + if (!CompareMem (DevicePath, FlashDevicePath, FLASH_DEVICE_PATH_SIZE (= FlashDevicePath))) { + // Device path starts with path of flash device. Check it isn't the = flash + // device itself. + NextNode =3D NextDevicePathNode (DevicePath); + if (IsDevicePathEndType (NextNode)) { + continue; + } + + // Assert that this device path node represents a partition. + ASSERT (NextNode->Type =3D=3D MEDIA_DEVICE_PATH && + NextNode->SubType =3D=3D MEDIA_HARDDRIVE_DP); + + PartitionNode =3D (HARDDRIVE_DEVICE_PATH *) NextNode; + + // Assert that the partition type is GPT. ReadPartitionEntries check= s for + // presence of a GPT, so we should never find MBR partitions. + // ("MBRType" is a misnomer - this field is actually called "Partiti= on + // Format") + ASSERT (PartitionNode->MBRType =3D=3D MBR_TYPE_EFI_PARTITION_TABLE_H= EADER); + + // The firmware may install a handle for "partition 0", representing= the + // whole device. Ignore it. + if (PartitionNode->PartitionNumber =3D=3D 0) { + continue; + } + + // + // Add the partition handle to the list + // + + // Create entry + Entry =3D AllocatePool (sizeof (FASTBOOT_PARTITION_LIST)); + if (Entry =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + FreePartitionList (); + goto Exit; + } + + // Copy handle and partition name + Entry->PartitionHandle =3D AllHandles[LoopIndex]; + CopyMem ( + Entry->PartitionName, + PartitionEntries[PartitionNode->PartitionNumber - 1].PartitionName= , // Partition numbers start from 1. + PARTITION_NAME_MAX_LENGTH + ); + InsertTailList (&mPartitionListHead, &Entry->Link); + + // Print a debug message if the partition label is empty or looks li= ke + // garbage. + if (!IS_ALPHA (Entry->PartitionName[0])) { + DEBUG ((EFI_D_ERROR, + "Warning: Partition %d doesn't seem to have a GPT partition labe= l. " + "You won't be able to flash it with Fastboot.\n", + PartitionNode->PartitionNumber + )); + } + } + } + +Exit: + FreePool (PartitionEntries); + FreePool (FlashDevicePath); + FreePool (AllHandles); + return Status; + +} + +/* + To be called when Fastboot is finished and we aren't rebooting or bootin= g an + image. Undo initialisation, free resrouces. +*/ +STATIC +VOID +ArmFastbootPlatformUnInit ( + VOID + ) +{ + FreePartitionList (); +} + +/* + Flash the partition named (according to a platform-specific scheme) + PartitionName, with the image pointed to by Buffer, whose size is Buffer= Size. + + @param[in] PartitionName Null-terminated name of partition to write. + @param[in] BufferSize Size of Buffer in byets. + @param[in] Buffer Data to write to partition. + + @retval EFI_NOT_FOUND No such partition. + @retval EFI_DEVICE_ERROR Flashing failed. +*/ +STATIC +EFI_STATUS +ArmFastbootPlatformFlashPartition ( + IN CHAR8 *PartitionName, + IN UINTN Size, + IN VOID *Image + ) +{ + EFI_STATUS Status; + EFI_BLOCK_IO_PROTOCOL *BlockIo; + EFI_DISK_IO_PROTOCOL *DiskIo; + UINT32 MediaId; + UINTN PartitionSize; + FASTBOOT_PARTITION_LIST *Entry; + CHAR16 PartitionNameUnicode[60]; + BOOLEAN PartitionFound; + + AsciiStrToUnicodeStrS (PartitionName, PartitionNameUnicode, + ARRAY_SIZE (PartitionNameUnicode)); + + PartitionFound =3D FALSE; + Entry =3D (FASTBOOT_PARTITION_LIST *) GetFirstNode (&(mPartitionListHead= )); + while (!IsNull (&mPartitionListHead, &Entry->Link)) { + // Search the partition list for the partition named by PartitionName + if (StrCmp (Entry->PartitionName, PartitionNameUnicode) =3D=3D 0) { + PartitionFound =3D TRUE; + break; + } + + Entry =3D (FASTBOOT_PARTITION_LIST *) GetNextNode (&mPartitionListHead,= &(Entry)->Link); + } + if (!PartitionFound) { + return EFI_NOT_FOUND; + } + + Status =3D gBS->OpenProtocol ( + Entry->PartitionHandle, + &gEfiBlockIoProtocolGuid, + (VOID **) &BlockIo, + gImageHandle, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status)) { + DEBUG ((EFI_D_ERROR, "Fastboot platform: couldn't open Block IO for fl= ash: %r\n", Status)); + return EFI_NOT_FOUND; + } + + // Check image will fit on device + PartitionSize =3D (BlockIo->Media->LastBlock + 1) * BlockIo->Media->Bloc= kSize; + if (PartitionSize < Size) { + DEBUG ((EFI_D_ERROR, "Partition not big enough.\n")); + DEBUG ((EFI_D_ERROR, "Partition Size:\t%d\nImage Size:\t%d\n", Partiti= onSize, Size)); + + return EFI_VOLUME_FULL; + } + + MediaId =3D BlockIo->Media->MediaId; + + Status =3D gBS->OpenProtocol ( + Entry->PartitionHandle, + &gEfiDiskIoProtocolGuid, + (VOID **) &DiskIo, + gImageHandle, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + ASSERT_EFI_ERROR (Status); + + Status =3D DiskIo->WriteDisk (DiskIo, MediaId, 0, Size, Image); + if (EFI_ERROR (Status)) { + return Status; + } + + BlockIo->FlushBlocks(BlockIo); + + return Status; +} + +/* + Erase the partition named PartitionName. + + @param[in] PartitionName Null-terminated name of partition to erase. + + @retval EFI_NOT_FOUND No such partition. + @retval EFI_DEVICE_ERROR Erasing failed. +*/ +STATIC +EFI_STATUS +ArmFastbootPlatformErasePartition ( + IN CHAR8 *Partition + ) +{ + return EFI_SUCCESS; +} + +/* + If the variable referred to by Name exists, copy it (as a null-terminated + string) into Value. If it doesn't exist, put the Empty string in Value. + + Variable names and values may not be larger than 60 bytes, excluding the + terminal null character. This is a limitation of the Fastboot protocol. + + The Fastboot application will handle platform-nonspecific variables + (Currently "version" is the only one of these.) + + @param[in] Name Null-terminated name of Fastboot variable to retrieve. + @param[out] Value Caller-allocated buffer for null-terminated value of + variable. + + @retval EFI_SUCCESS The variable was retrieved, or it doesn't exis= t. + @retval EFI_DEVICE_ERROR There was an error looking up the variable. Th= is + does _not_ include the variable not existing. +*/ +STATIC +EFI_STATUS +ArmFastbootPlatformGetVar ( + IN CHAR8 *Name, + OUT CHAR8 *Value + ) +{ + if (AsciiStrCmp (Name, "product")) { + AsciiStrCpyS (Value, 61, FixedPcdGetPtr (PcdFirmwareVendor)); + } else { + *Value =3D '\0'; + } + return EFI_SUCCESS; +} + +/* + React to an OEM-specific command. + + Future versions of this function might want to allow the platform to do = some + extra communication with the host. A way to do this would be to add a fu= nction + to the FASTBOOT_TRANSPORT_PROTOCOL that allows the implementation of + DoOemCommand to replace the ReceiveEvent with its own, and to restore th= e old + one when it's finished. + + However at the moment although the specification allows it, the AOSP fas= tboot + host application doesn't handle receiving any data from the client, and = it + doesn't support a data phase for OEM commands. + + @param[in] Command Null-terminated command string. + + @retval EFI_SUCCESS The command executed successfully. + @retval EFI_NOT_FOUND The command wasn't recognised. + @retval EFI_DEVICE_ERROR There was an error executing the command. +*/ +STATIC +EFI_STATUS +ArmFastbootPlatformOemCommand ( + IN CHAR8 *Command + ) +{ + CHAR16 CommandUnicode[65]; + + AsciiStrToUnicodeStrS (Command, CommandUnicode, ARRAY_SIZE (CommandUnico= de)); + + if (AsciiStrCmp (Command, "Demonstrate") =3D=3D 0) { + DEBUG ((EFI_D_ERROR, "ARM OEM Fastboot command 'Demonstrate' received.= \n")); + return EFI_SUCCESS; + } else { + DEBUG ((EFI_D_ERROR, + "VExpress: Unrecognised Fastboot OEM command: %s\n", + CommandUnicode + )); + return EFI_NOT_FOUND; + } +} + +STATIC FASTBOOT_PLATFORM_PROTOCOL mPlatformProtocol =3D { + ArmFastbootPlatformInit, + ArmFastbootPlatformUnInit, + ArmFastbootPlatformFlashPartition, + ArmFastbootPlatformErasePartition, + ArmFastbootPlatformGetVar, + ArmFastbootPlatformOemCommand +}; + +EFI_STATUS +EFIAPI +ArmAndroidFastbootPlatformEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return gBS->InstallProtocolInterface ( + &ImageHandle, + &gAndroidFastbootPlatformProtocolGuid, + EFI_NATIVE_INTERFACE, + &mPlatformProtocol + ); +} diff --git a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressFastBootDxe/ArmVEx= pressFastBootDxe.inf b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressFastBoot= Dxe/ArmVExpressFastBootDxe.inf new file mode 100644 index 000000000000..07c5e1e230e9 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressFastBootDxe/ArmVExpressFa= stBootDxe.inf @@ -0,0 +1,51 @@ +#/** @file +# +# Copyright (c) 2014, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ArmVExpressFastBootDxe + FILE_GUID =3D 4004e454-89a0-11e3-89aa-97ef9d942abc + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ArmAndroidFastbootPlatformEntryPoint + +[Sources.common] + ArmVExpressFastBoot.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + MemoryAllocationLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gAndroidFastbootPlatformProtocolGuid + gEfiBlockIoProtocolGuid + gEfiDiskIoProtocolGuid + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[Pcd] + gArmVExpressTokenSpaceGuid.PcdAndroidFastbootNvmDevicePath + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor diff --git a/Platform/ARM/VExpressPkg/Include/Library/ArmPlatformSysConfigL= ib.h b/Platform/ARM/VExpressPkg/Include/Library/ArmPlatformSysConfigLib.h new file mode 100644 index 000000000000..39a0cc7f734c --- /dev/null +++ b/Platform/ARM/VExpressPkg/Include/Library/ArmPlatformSysConfigLib.h @@ -0,0 +1,63 @@ +/** @file ArmPlatformSysConfigLib.h + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __ARM_PLATFORM_SYS_CONFIG_H__ +#define __ARM_PLATFORM_SYS_CONFIG_H__ + +#include + +/* This header file makes it easier to access the System Configuration Reg= isters + * in the ARM Versatile Express motherboard. + */ + +// +// Typedef +// +typedef UINT32 SYS_CONFIG_FUNCTION; + +// +// Functions +// +RETURN_STATUS +ArmPlatformSysConfigInitialize ( + VOID + ); + +RETURN_STATUS +ArmPlatformSysConfigGet ( + IN SYS_CONFIG_FUNCTION Function, + OUT UINT32* Value + ); + +RETURN_STATUS +ArmPlatformSysConfigGetValues ( + IN SYS_CONFIG_FUNCTION Function, + IN UINTN Size, + OUT UINT32* Values + ); + +RETURN_STATUS +ArmPlatformSysConfigSet ( + IN SYS_CONFIG_FUNCTION Function, + IN UINT32 Value + ); + +RETURN_STATUS +ArmPlatformSysConfigSetDevice ( + IN SYS_CONFIG_FUNCTION Function, + IN UINT32 Device, + IN UINT32 Value + ); + +#endif /* __SYS_CFG_REGISTERS_H__ */ diff --git a/Platform/ARM/VExpressPkg/Include/Library/LcdPlatformLib.h b/Pl= atform/ARM/VExpressPkg/Include/Library/LcdPlatformLib.h new file mode 100644 index 000000000000..b9bdf471e2d6 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Include/Library/LcdPlatformLib.h @@ -0,0 +1,221 @@ +/** @file + + Copyright (c) 2011, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + **/ + +#ifndef __LCDPLATFORMLIB_H +#define __LCDPLATFORMLIB_H + +#include + +#define LCD_VRAM_SIZE SIZE_8MB + +// +// Modes definitions +// +#define VGA 0 +#define SVGA 1 +#define XGA 2 +#define SXGA 3 +#define WSXGA 4 +#define UXGA 5 +#define HD 6 + +// +// VGA Mode: 640 x 480 +// +#define VGA_H_RES_PIXELS 640 +#define VGA_V_RES_PIXELS 480 +#define VGA_OSC_FREQUENCY 23750000 /* 0x016A6570 */ + +#define VGA_H_SYNC ( 80 - 1) +#define VGA_H_FRONT_PORCH ( 16 - 1) +#define VGA_H_BACK_PORCH ( 64 - 1) + +#define VGA_V_SYNC ( 4 - 1) +#define VGA_V_FRONT_PORCH ( 3 - 1) +#define VGA_V_BACK_PORCH ( 13 - 1) + +// +// SVGA Mode: 800 x 600 +// +#define SVGA_H_RES_PIXELS 800 +#define SVGA_V_RES_PIXELS 600 +#define SVGA_OSC_FREQUENCY 38250000 /* 0x0247A610 */ + +#define SVGA_H_SYNC ( 80 - 1) +#define SVGA_H_FRONT_PORCH ( 32 - 1) +#define SVGA_H_BACK_PORCH (112 - 1) + +#define SVGA_V_SYNC ( 4 - 1) +#define SVGA_V_FRONT_PORCH ( 3 - 1) +#define SVGA_V_BACK_PORCH ( 17 - 1) + +// +// XGA Mode: 1024 x 768 +// +#define XGA_H_RES_PIXELS 1024 +#define XGA_V_RES_PIXELS 768 +#define XGA_OSC_FREQUENCY 63500000 /* 0x03C8EEE0 */ + +#define XGA_H_SYNC (104 - 1) +#define XGA_H_FRONT_PORCH ( 48 - 1) +#define XGA_H_BACK_PORCH (152 - 1) + +#define XGA_V_SYNC ( 4 - 1) +#define XGA_V_FRONT_PORCH ( 3 - 1) +#define XGA_V_BACK_PORCH ( 23 - 1) + +// +// SXGA Mode: 1280 x 1024 +// +#define SXGA_H_RES_PIXELS 1280 +#define SXGA_V_RES_PIXELS 1024 +#define SXGA_OSC_FREQUENCY 109000000 /* 0x067F3540 */ + +#define SXGA_H_SYNC (136 - 1) +#define SXGA_H_FRONT_PORCH ( 80 - 1) +#define SXGA_H_BACK_PORCH (216 - 1) + +#define SXGA_V_SYNC ( 7 - 1) +#define SXGA_V_FRONT_PORCH ( 3 - 1) +#define SXGA_V_BACK_PORCH ( 29 - 1) + +// +// WSXGA+ Mode: 1680 x 1050 +// +#define WSXGA_H_RES_PIXELS 1680 +#define WSXGA_V_RES_PIXELS 1050 +#define WSXGA_OSC_FREQUENCY 147000000 /* 0x08C30AC0 */ + +#define WSXGA_H_SYNC (170 - 1) +#define WSXGA_H_FRONT_PORCH (104 - 1) +#define WSXGA_H_BACK_PORCH (274 - 1) + +#define WSXGA_V_SYNC ( 5 - 1) +#define WSXGA_V_FRONT_PORCH ( 4 - 1) +#define WSXGA_V_BACK_PORCH ( 41 - 1) + +// +// UXGA Mode: 1600 x 1200 +// +#define UXGA_H_RES_PIXELS 1600 +#define UXGA_V_RES_PIXELS 1200 +#define UXGA_OSC_FREQUENCY 161000000 /* 0x0998AA40 */ + +#define UXGA_H_SYNC (168 - 1) +#define UXGA_H_FRONT_PORCH (112 - 1) +#define UXGA_H_BACK_PORCH (280 - 1) + +#define UXGA_V_SYNC ( 4 - 1) +#define UXGA_V_FRONT_PORCH ( 3 - 1) +#define UXGA_V_BACK_PORCH ( 38 - 1) + +// +// HD Mode: 1920 x 1080 +// +#define HD_H_RES_PIXELS 1920 +#define HD_V_RES_PIXELS 1080 +#define HD_OSC_FREQUENCY 165000000 /* 0x09D5B340 */ + +#define HD_H_SYNC ( 79 - 1) +#define HD_H_FRONT_PORCH (128 - 1) +#define HD_H_BACK_PORCH (328 - 1) + +#define HD_V_SYNC ( 5 - 1) +#define HD_V_FRONT_PORCH ( 3 - 1) +#define HD_V_BACK_PORCH ( 32 - 1) + +// +// Colour Masks +// + +#define LCD_24BPP_RED_MASK 0x00FF0000 +#define LCD_24BPP_GREEN_MASK 0x0000FF00 +#define LCD_24BPP_BLUE_MASK 0x000000FF +#define LCD_24BPP_RESERVED_MASK 0xFF000000 + +#define LCD_16BPP_555_RED_MASK 0x00007C00 +#define LCD_16BPP_555_GREEN_MASK 0x000003E0 +#define LCD_16BPP_555_BLUE_MASK 0x0000001F +#define LCD_16BPP_555_RESERVED_MASK 0x00000000 + +#define LCD_16BPP_565_RED_MASK 0x0000F800 +#define LCD_16BPP_565_GREEN_MASK 0x000007E0 +#define LCD_16BPP_565_BLUE_MASK 0x0000001F +#define LCD_16BPP_565_RESERVED_MASK 0x00008000 + +#define LCD_12BPP_444_RED_MASK 0x00000F00 +#define LCD_12BPP_444_GREEN_MASK 0x000000F0 +#define LCD_12BPP_444_BLUE_MASK 0x0000000F +#define LCD_12BPP_444_RESERVED_MASK 0x0000F000 + + +// The enumeration indexes maps the PL111 LcdBpp values used in the LCD Co= ntrol Register +typedef enum { + LCD_BITS_PER_PIXEL_1 =3D 0, + LCD_BITS_PER_PIXEL_2, + LCD_BITS_PER_PIXEL_4, + LCD_BITS_PER_PIXEL_8, + LCD_BITS_PER_PIXEL_16_555, + LCD_BITS_PER_PIXEL_24, + LCD_BITS_PER_PIXEL_16_565, + LCD_BITS_PER_PIXEL_12_444 +} LCD_BPP; + + +EFI_STATUS +LcdPlatformInitializeDisplay ( + IN EFI_HANDLE Handle + ); + +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, + OUT UINTN* VramSize + ); + +UINT32 +LcdPlatformGetMaxMode ( + VOID + ); + +EFI_STATUS +LcdPlatformSetMode ( + IN UINT32 ModeNumber + ); + +EFI_STATUS +LcdPlatformQueryMode ( + IN UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info + ); + +EFI_STATUS +LcdPlatformGetTimings ( + IN UINT32 ModeNumber, + OUT UINT32* HRes, + OUT UINT32* HSync, + OUT UINT32* HBackPorch, + OUT UINT32* HFrontPorch, + OUT UINT32* VRes, + OUT UINT32* VSync, + OUT UINT32* VBackPorch, + OUT UINT32* VFrontPorch + ); + +EFI_STATUS +LcdPlatformGetBpp ( + IN UINT32 ModeNumber, + OUT LCD_BPP* Bpp + ); + +#endif diff --git a/Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/ArmPlatform= .h b/Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h new file mode 100644 index 000000000000..b52f89a5cbf8 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h @@ -0,0 +1,154 @@ +/** @file +* Header defining Versatile Express constants (Base addresses, sizes, fla= gs) +* +* Copyright (c) 2012, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __ARM_VEXPRESS_CTA15A7_H__ +#define __ARM_VEXPRESS_CTA15A7_H__ + +#include + +/*************************************************************************= ********** +// Platform Memory Map +**************************************************************************= **********/ + +// Motherboard Peripheral and On-chip peripheral +#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000 + +#ifdef ARM_BIGLITTLE_TC2 + +// Secure NOR Flash +#define ARM_VE_SEC_NOR0_BASE 0x00000000 +#define ARM_VE_SEC_NOR0_SZ SIZE_64MB + +// Secure RAM +#define ARM_VE_SEC_RAM0_BASE 0x04000000 +#define ARM_VE_SEC_RAM0_SZ SIZE_64MB + +#endif + +// NOR Flash 0 +#define ARM_VE_SMB_NOR0_BASE 0x08000000 +#define ARM_VE_SMB_NOR0_SZ SIZE_64MB +// NOR Flash 1 +#define ARM_VE_SMB_NOR1_BASE 0x0C000000 +#define ARM_VE_SMB_NOR1_SZ SIZE_64MB + +// SRAM +#define ARM_VE_SMB_SRAM_BASE 0x14000000 +#define ARM_VE_SMB_SRAM_SZ SIZE_32MB + +// USB, Ethernet, VRAM +#ifdef ARM_BIGLITTLE_TC2 +#define ARM_VE_SMB_PERIPH_BASE 0x18000000 +#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_32MB + SIZ= E_16MB) +#else +#define ARM_VE_SMB_PERIPH_BASE 0x1C000000 +#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_16MB) +#endif +#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE + +// On-Chip non-secure ROM +#ifdef ARM_BIGLITTLE_TC2 +#define ARM_VE_TC2_NON_SECURE_ROM_BASE 0x1F000000 +#define ARM_VE_TC2_NON_SECURE_ROM_SZ SIZE_16MB +#endif + +// On-Chip Peripherals +#define ARM_VE_ONCHIP_PERIPH_BASE 0x20000000 +#define ARM_VE_ONCHIP_PERIPH_SZ 0x10000000 + +// On-Chip non-secure SRAM +#ifdef ARM_BIGLITTLE_TC2 +#define ARM_VE_TC2_NON_SECURE_SRAM_BASE 0x2E000000 +#define ARM_VE_TC2_NON_SECURE_SRAM_SZ SIZE_64KB +#endif + +// Allocate a section for the VRAM (Video RAM) +// If 0 then allow random memory allocation +#define LCD_VRAM_CORE_TILE_BASE 0 + +// Define SEC phase sync point +#define ARM_SEC_EVENT_BOOT_IMAGE_TABLE_IS_AVAILABLE (ARM_SEC_EVENT_MAX += 1) + +/*************************************************************************= ********** + Core Tile memory-mapped Peripherals +**************************************************************************= **********/ + +// PL354 Static Memory Controller Base +#ifdef ARM_BIGLITTLE_TC2 +#define ARM_VE_SMC_CTRL_BASE 0x7FFD0000 +#else +#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE = + 0xE1000) +#endif + +#define ARM_CTA15A7_SCC_BASE 0x7FFF0000 +#define ARM_CTA15A7_SCC_CFGREG48 (ARM_CTA15A7_SCC_BASE + 0x= 700) + +#define ARM_CTA15A7_SCC_SYSINFO ARM_CTA15A7_SCC_CFGREG48 + +#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val) (((val) >>= 20) & 0xF) +#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val) (((val) >>= 16) & 0xF) +#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15 (1 << 0) +#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7 (1 << 1) +#define ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH (1 << 4) + +#define ARM_CTA15A7_SPC_BASE 0x7FFF0B00 +#define ARM_CTA15A7_SPC_WAKE_INT_MASK (ARM_CTA15A7_SPC_BASE + 0x= 24) +#define ARM_CTA15A7_SPC_STANDBYWFI_STAT (ARM_CTA15A7_SPC_BASE + 0x= 3C) +#define ARM_CTA15A7_SPC_A15_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x= 68) +#define ARM_CTA15A7_SPC_A15_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x= 6C) +#define ARM_CTA15A7_SPC_A15_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x= 70) +#define ARM_CTA15A7_SPC_A15_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x= 74) +#define ARM_CTA15A7_SPC_A7_BX_ADDR0 (ARM_CTA15A7_SPC_BASE + 0x= 78) +#define ARM_CTA15A7_SPC_A7_BX_ADDR1 (ARM_CTA15A7_SPC_BASE + 0x= 7C) +#define ARM_CTA15A7_SPC_A7_BX_ADDR2 (ARM_CTA15A7_SPC_BASE + 0x= 80) +#define ARM_CTA15A7_SPC_A7_BX_ADDR3 (ARM_CTA15A7_SPC_BASE + 0x= 84) + +#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_0 (1 << 0) +#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A15_MASK_1 (1 << 1) +#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_0 (1 << 2) +#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A15_MASK_1 (1 << 3) +#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_0 (1 << 4) +#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_1 (1 << 5) +#define ARM_CTA15A7_SPC_WAKE_INT_MASK_IRQ_A7_MASK_2 (1 << 6) +#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_0 (1 << 7) +#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_1 (1 << 8) +#define ARM_CTA15A7_SPC_WAKE_INT_MASK_FIQ_A7_MASK_2 (1 << 9) + +#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_0 (1 << 0) +#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_1 (1 << 1) +#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A15_L2 (1 << 2) +#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_0 (1 << 3) +#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_1 (1 << 4) +#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_2 (1 << 5) +#define ARM_CTA15A7_SPC_STANDBYWFI_STAT_A7_L2 (1 << 6) + + +/*************************************************************************= ********** +// Memory-mapped peripherals +**************************************************************************= **********/ + +/*// SP810 Controller +#undef SP810_CTRL_BASE +#define SP810_CTRL_BASE 0x1C020000 + +// PL111 Colour LCD Controller +#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE +#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1 +#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1 + +// VRAM offset for the PL111 Colour LCD Controller on the motherboard +#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE = + 0x00000)*/ + +#endif diff --git a/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h b= /Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h new file mode 100644 index 000000000000..d856b6daa1d7 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h @@ -0,0 +1,79 @@ +/** @file +* Header defining Versatile Express constants (Base addresses, sizes, fla= gs) +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __ARM_VEXPRESS_H__ +#define __ARM_VEXPRESS_H__ + +#include + +/*************************************************************************= ********** +// Platform Memory Map +**************************************************************************= **********/ + +// Can be NOR0, NOR1, DRAM +#define ARM_VE_REMAP_BASE 0x00000000 +#define ARM_VE_REMAP_SZ SIZE_64MB + +// Motherboard Peripheral and On-chip peripheral +#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000 + +// NOR Flash 1 +// There is typo in the reference manual for the Base address of NOR Flash= 1 +#define ARM_VE_SMB_NOR0_BASE 0x08000000 +#define ARM_VE_SMB_NOR0_SZ SIZE_64MB +// NOR Flash 2 +#define ARM_VE_SMB_NOR1_BASE 0x0C000000 +#define ARM_VE_SMB_NOR1_SZ SIZE_64MB +// SRAM +#define ARM_VE_SMB_SRAM_BASE 0x2E000000 +#define ARM_VE_SMB_SRAM_SZ SIZE_64KB +// USB, Ethernet, VRAM +#define ARM_VE_SMB_PERIPH_BASE 0x18800000 +#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB) + +#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000 +#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE 0x800000 + +// DRAM +#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryB= ase) +#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemoryS= ize) + +// This can be any value since we only support motherboard PL111 +#define LCD_VRAM_CORE_TILE_BASE 0x00000000 + +// On-chip peripherals (Snoop Control Unit etc...) +#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000 +// Note: The TRM says not all the peripherals are implemented +#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB + + +// External AXI between daughterboards (Logic Tile) +#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled +#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */ + +/*************************************************************************= ********** +// Memory-mapped peripherals +**************************************************************************= **********/ + +// SP810 Controller +#undef SP810_CTRL_BASE +#define SP810_CTRL_BASE 0x1C020000 + +// PL111 Colour LCD Controller +#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE +#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1 +#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1 + +#endif diff --git a/Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h b/Platf= orm/ARM/VExpressPkg/Include/VExpressMotherBoard.h new file mode 100644 index 000000000000..38691c35828b --- /dev/null +++ b/Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h @@ -0,0 +1,140 @@ +/** @file +* Header defining Versatile Express constants (Base addresses, sizes, fla= gs) +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __VEXPRESSMOTHERBOARD_H_ +#define __VEXPRESSMOTHERBOARD_H_ + +#include + +/*************************************************************************= ********** +// Motherboard memory-mapped peripherals +**************************************************************************= **********/ + +// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE) +#define ARM_VE_SYS_ID_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x00000) +#define ARM_VE_SYS_SW_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x00004) +#define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x00008) +#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x00030) +#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x00030) +#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x00034) +#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x00038) +#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x00038) +#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x0003C) +#define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BAS= E + 0x0004C) +#define ARM_VE_SYS_CFGSWR_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x00058) +#define ARM_VE_SYS_MISC (ARM_VE_BOARD_PERIPH_BAS= E + 0x00060) +#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x00084) +#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x00088) +#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x000A0) +#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x000A4) +#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BAS= E + 0x000A8) + +// SP810 Controller +#ifndef SP810_CTRL_BASE +#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BAS= E + 0x01000) +#endif + +// PL111 Colour LCD Controller - motherboard +#define PL111_CLCD_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BAS= E + 0x1F000) +#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1 + +// VRAM offset for the PL111 Colour LCD Controller on the motherboard +#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE = + 0x00000) + +#define ARM_VE_SYS_PROC_ID_HBI 0xFFF +#define ARM_VE_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24) +#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (UINT32)(0xFFU << 24) +#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24) +#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (UINT32)(0x12U << 24) +#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (UINT32)(0x14U << 24) +#define ARM_VE_SYS_PROC_ID_CORTEX_A7 (UINT32)(0x18U << 24) +#define ARM_VE_SYS_PROC_ID_CORTEX_A12 (UINT32)(0x1CU << 24) + +// Boot Master Select: +// 0 =3D Site 1 boot master +// 1 =3D Site 2 boot master +#define ARM_VE_SYS_MISC_MASTERSITE (1 << 14) +// +// Sites where the peripheral is fitted +// +#define ARM_VE_UNSUPPORTED ~0 +#define ARM_VE_MOTHERBOARD_SITE 0 +#define ARM_VE_DAUGHTERBOARD_1_SITE 1 +#define ARM_VE_DAUGHTERBOARD_2_SITE 2 + +#define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func)) + +// +// System Configuration Control Functions +// +#define SYS_CFG_OSC 1 +#define SYS_CFG_VOLT 2 +#define SYS_CFG_AMP 3 +#define SYS_CFG_TEMP 4 +#define SYS_CFG_RESET 5 +#define SYS_CFG_SCC 6 +#define SYS_CFG_MUXFPGA 7 +#define SYS_CFG_SHUTDOWN 8 +#define SYS_CFG_REBOOT 9 +#define SYS_CFG_DVIMODE 11 +#define SYS_CFG_POWER 12 +// Oscillator for Site 1 +#define SYS_CFG_OSC_SITE1 VIRTUAL_SYS_CFG(ARM_VE_D= AUGHTERBOARD_1_SITE,SYS_CFG_OSC) +// Oscillator for Site 2 +#define SYS_CFG_OSC_SITE2 VIRTUAL_SYS_CFG(ARM_VE_D= AUGHTERBOARD_2_SITE,SYS_CFG_OSC) +// Can not access the battery backed-up hardware clock on the Versatile Ex= press motherboard +#define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_U= NSUPPORTED,1) + +// +// System ID +// +// All RTSM VE models have the same System ID : 0x225F500 +// +// FVP models have a different System ID. +// Default Base model System ID : 0x00201100 +// [31:28] Rev - Board revision: 0x0 =3D Rev A +// [27:16] HBI - HBI board number in BCD: 0x020 =3D v8 Base Platform +// [15:12] Variant - Build variant of board: 0x1 =3D Variant B. (GIC = 64k map) +// [11:8] Plat - Platform type: 0x1 =3D Model +// [7:0] FPGA - FPGA build, BCD coded: 0x00 +// +//HBI =3D 010 =3D Foundation Model +//HBI =3D 020 =3D Base Platform +// +// And specifically, the GIC register banks start at the following +// addresses: +// Variant =3D 0 Variant =3D 1 +//GICD 0x2c001000 0x2f000000 +//GICC 0x2c002000 0x2c000000 +//GICH 0x2c004000 0x2c010000 +//GICV 0x2c006000 0x2c020000 + +#define ARM_FVP_BASE_BOARD_SYS_ID (0x00200100) +#define ARM_FVP_FOUNDATION_BOARD_SYS_ID (0x00100100) + +#define ARM_FVP_SYS_ID_REV_MASK (UINT32)(0xFUL << 28) +#define ARM_FVP_SYS_ID_HBI_MASK (UINT32)(0xFFFUL << 16) +#define ARM_FVP_SYS_ID_VARIANT_MASK (UINT32)(0xFUL << 12) +#define ARM_FVP_SYS_ID_PLAT_MASK (UINT32)(0xFUL << 8 ) +#define ARM_FVP_SYS_ID_FPGA_MASK (UINT32)(0xFFUL << 0 ) +#define ARM_FVP_GIC_VE_MMAP 0x0 +#define ARM_FVP_GIC_BASE_MMAP (UINT32)(1 << 12) + +// The default SYS_IDs. These can be changed when starting the model. +#define ARM_RTSM_SYS_ID (0x225F500) +#define ARM_FVP_BASE_SYS_ID (ARM_FVP_BASE_BOARD_SYS_ID | ARM_FV= P_GIC_BASE_MMAP) +#define ARM_FVP_FOUNDATION_SYS_ID (ARM_FVP_FOUNDATION_BOARD_SYS_ID | = ARM_FVP_GIC_BASE_MMAP) + +#endif /* VEXPRESSMOTHERBOARD_H_ */ diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVEx= pressLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmV= ExpressLib.inf new file mode 100644 index 000000000000..9e81b1c1cc16 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLi= b.inf @@ -0,0 +1,54 @@ +#/* @file +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#*/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D CTA15A7ArmVExpressLib + FILE_GUID =3D b98a6cb7-d472-4128-ad62-a7347f85ce13 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + IoLib + ArmLib + MemoryAllocationLib + SerialPortLib + +[Sources.common] + CTA15-A7.c + CTA15-A7Mem.c + CTA15-A7Helper.asm | RVCT + CTA15-A7Helper.S | GCC + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdFvBaseAddress + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-= A7.c b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c new file mode 100644 index 000000000000..a6ddd1b792c9 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7.c @@ -0,0 +1,182 @@ +/** @file +* +* Copyright (c) 2012, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include + +#include + +#include + +ARM_CORE_INFO mVersatileExpressCTA15A7InfoTable[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR0, + (UINT64)0 + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR1, + (UINT64)0 + }, +#ifndef ARM_BIGLITTLE_TC2 + { + // Cluster 0, Core 2 + 0x0, 0x2, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR2, + (UINT64)0 + }, + { + // Cluster 0, Core 3 + 0x0, 0x3, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A15_BX_ADDR3, + (UINT64)0 + }, +#endif + { + // Cluster 1, Core 0 + 0x1, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR0, + (UINT64)0 + }, + { + // Cluster 1, Core 1 + 0x1, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR1, + (UINT64)0 + }, + { + // Cluster 1, Core 2 + 0x1, 0x2, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR2, + (UINT64)0 + } +#ifndef ARM_BIGLITTLE_TC2 + ,{ + // Cluster 1, Core 3 + 0x1, 0x3, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3, + (EFI_PHYSICAL_ADDRESS)ARM_CTA15A7_SPC_A7_BX_ADDR3, + (UINT64)0 + } +#endif +}; + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + if (MmioRead32(ARM_CTA15A7_SCC_SYSINFO) & ARM_CTA15A7_SCC_SYSINFO_UEFI_R= ESTORE_DEFAULT_NORFLASH) { + return BOOT_WITH_DEFAULT_SETTINGS; + } else { + return BOOT_WITH_FULL_CONFIGURATION; + } +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/= PlatformPeim + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + if (!ArmPlatformIsPrimaryCore (MpId)) { + return RETURN_SUCCESS; + } + + // Nothing to do here + + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + // Only support one cluster + *CoreCount =3D sizeof(mVersatileExpressCTA15A7InfoTable) / sizeof(ARM= _CORE_INFO); + *ArmCoreTable =3D mVersatileExpressCTA15A7InfoTable; + return EFI_SUCCESS; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof(gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-= A7Helper.S b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-= A7Helper.S new file mode 100644 index 000000000000..3719a5ace604 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helpe= r.S @@ -0,0 +1,81 @@ +// +// Copyright (c) 2012-2013, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the = BSD License +// which accompanies this distribution. The full text of the license may= be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. +// +// + +#include +#include + +#include + +ASM_FUNC(ArmPlatformPeiBootAction) + bx lr + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformGetCorePosition) + and r1, r0, #ARM_CORE_MASK + and r0, r0, #ARM_CLUSTER_MASK + add r0, r1, r0, LSR #7 + bx lr + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48 + // with cpu_id[0:3] and cluster_id[4:7] + MOV32 (r1, ARM_CTA15A7_SCC_CFGREG48) + ldr r1, [r1] + lsr r1, #24 + + // Shift the SCC value to get the cluster ID at the offset #8 + lsl r2, r1, #4 + and r2, r2, #0xF00 + + // Keep only the cpu ID from the original SCC + and r1, r1, #0x0F + // Add the Cluster ID to the Cpu ID + orr r1, r1, r2 + + // Keep the Cluster ID and Core ID from the MPID + MOV32 (r2, ARM_CLUSTER_MASK | ARM_CORE_MASK) + and r0, r0, r2 + + // Compare mpid and boot cpu from ARM_SCC_CFGREG48 + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48 + // with cpu_id[0:3] and cluster_id[4:7] + MOV32 (r0, ARM_CTA15A7_SCC_CFGREG48) + ldr r0, [r0] + lsr r0, #24 + + // Shift the SCC value to get the cluster ID at the offset #8 + lsl r1, r0, #4 + and r1, r1, #0xF00 + + // Keep only the cpu ID from the original SCC + and r0, r0, #0x0F + // Add the Cluster ID to the Cpu ID + orr r0, r0, r1 + bx lr diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-= A7Helper.asm b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA1= 5-A7Helper.asm new file mode 100644 index 000000000000..c035843da078 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Helpe= r.asm @@ -0,0 +1,96 @@ +// +// Copyright (c) 2012-2013, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the = BSD License +// which accompanies this distribution. The full text of the license may= be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. +// +// + +#include + +#include + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformPeiBootAction + EXPORT ArmPlatformGetCorePosition + EXPORT ArmPlatformIsPrimaryCore + EXPORT ArmPlatformGetPrimaryCoreMpId + + PRESERVE8 + AREA CTA15A7Helper, CODE, READONLY + +ArmPlatformPeiBootAction FUNCTION + bx lr + ENDFUNC + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ArmPlatformGetCorePosition FUNCTION + and r1, r0, #ARM_CORE_MASK + and r0, r0, #ARM_CLUSTER_MASK + add r0, r1, r0, LSR #7 + bx lr + ENDFUNC + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ArmPlatformIsPrimaryCore FUNCTION + // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48 + // with cpu_id[0:3] and cluster_id[4:7] + mov32 r1, ARM_CTA15A7_SCC_CFGREG48 + ldr r1, [r1] + lsr r1, #24 + + // Shift the SCC value to get the cluster ID at the offset #8 + lsl r2, r1, #4 + and r2, r2, #0xF00 + + // Keep only the cpu ID from the original SCC + and r1, r1, #0x0F + // Add the Cluster ID to the Cpu ID + orr r1, r1, r2 + + // Keep the Cluster ID and Core ID from the MPID + mov32 r2, ARM_CLUSTER_MASK :OR: ARM_CORE_MASK + and r0, r0, r2 + + // Compare mpid and boot cpu from ARM_SCC_CFGREG48 + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr + ENDFUNC + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ArmPlatformGetPrimaryCoreMpId FUNCTION + // Extract cpu_id and cluster_id from ARM_SCC_CFGREG48 + // with cpu_id[0:3] and cluster_id[4:7] + mov32 r0, ARM_CTA15A7_SCC_CFGREG48 + ldr r0, [r0] + lsr r0, #24 + + // Shift the SCC value to get the cluster ID at the offset #8 + lsl r1, r0, #4 + and r1, r1, #0xF00 + + // Keep only the cpu ID from the original SCC + and r0, r0, #0x0F + // Add the Cluster ID to the Cpu ID + orr r0, r0, r1 + bx lr + ENDFUNC + + END diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-= A7Mem.c b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7M= em.c new file mode 100644 index 000000000000..4403cbacb881 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibCTA15-A7/CTA15-A7Mem.c @@ -0,0 +1,182 @@ +/** @file +* +* Copyright (c) 2012, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include +#include + +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_= BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACH= ED_UNBUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR = describing a Physical-to- + Virtual Memory mapping. This array mus= t be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index =3D 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT (VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_= SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MA= P_DESCRIPTORS)); + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) =3D=3D TRUE) { + CacheAttributes =3D DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes =3D DDR_ATTRIBUTES_UNCACHED; + } + +#ifdef ARM_BIGLITTLE_TC2 + // Secure NOR0 Flash + VirtualMemoryTable[Index].PhysicalBase =3D ARM_VE_SEC_NOR0_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SEC_NOR0_BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_SEC_NOR0_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + // Secure RAM + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SEC_RAM0_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SEC_RAM0_BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_SEC_RAM0_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; +#endif + + // SMB CS0 - NOR0 Flash + VirtualMemoryTable[Index].PhysicalBase =3D ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].Length =3D SIZE_256KB * 255; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + // Environment Variables region + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_NOR0_BASE + (SI= ZE_256KB * 255); + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_NOR0_BASE + (SI= ZE_256KB * 255); + VirtualMemoryTable[Index].Length =3D SIZE_64KB * 4; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // SMB CS1 or CS4 - NOR1 Flash + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_NOR1_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_NOR1_BASE; + VirtualMemoryTable[Index].Length =3D SIZE_256KB * 255; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + // Environment Variables region + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_NOR1_BASE + (SI= ZE_256KB * 255); + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_NOR1_BASE + (SI= ZE_256KB * 255); + VirtualMemoryTable[Index].Length =3D SIZE_64KB * 4; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // SMB CS3 or CS1 - PSRAM + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_SRAM_BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_SMB_SRAM_SZ; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // Motherboard peripherals + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_SMB_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + +#ifdef ARM_BIGLITTLE_TC2 + // Non-secure ROM + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_TC2_NON_SECURE_ROM_= BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_TC2_NON_SECURE_ROM_= BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_TC2_NON_SECURE_ROM_= SZ; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; +#endif + + // OnChip peripherals + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_ONCHIP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_ONCHIP_PERIPH_BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_ONCHIP_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + + // SCC Region + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_CTA15A7_SCC_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_CTA15A7_SCC_BASE; + VirtualMemoryTable[Index].Length =3D SIZE_64KB; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; + +#ifdef ARM_BIGLITTLE_TC2 + // TC2 OnChip non-secure SRAM + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_TC2_NON_SECURE_SRAM= _BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_TC2_NON_SECURE_SRAM= _BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_TC2_NON_SECURE_SRAM= _SZ; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; +#endif + +#ifndef ARM_BIGLITTLE_TC2 + // Workaround for SRAM bug in RTSM + if (PcdGet64 (PcdSystemMemoryBase) !=3D 0x80000000) { + VirtualMemoryTable[++Index].PhysicalBase =3D 0x80000000; + VirtualMemoryTable[Index].VirtualBase =3D 0x80000000; + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemor= yBase) - 0x80000000; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + } +#endif + + // DDR + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemoryB= ase); + VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemoryS= ize); + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // Detect if it is a 1GB or 2GB Test Chip + // [16:19]: 0=3D1GB TC2, 1=3D2GB TC2 + if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) { + DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n")); + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZE= D | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUT= E_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize), + SIZE_1GB + ); + + // Map the additional 1GB into the MMU + VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdSystemMemor= yBase) + PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemor= yBase) + PcdGet64 (PcdSystemMemorySize); + VirtualMemoryTable[Index].Length =3D SIZE_1GB; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + } + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBU= TES)0; + + ASSERT((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/AArch64/RT= SMHelper.S b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/AArch64/RT= SMHelper.S new file mode 100644 index 000000000000..db6d83c3cce9 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/AArch64/RTSMHelpe= r.S @@ -0,0 +1,61 @@ +# +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +#include +#include + +ASM_FUNC(ArmPlatformPeiBootAction) + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore)) + ret + +# IN None +# OUT x0 =3D number of cores present in the system +ASM_FUNC(ArmGetCpuCountPerCluster) + MOV32 (w0, FixedPcdGet32 (PcdCoreCount)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask)) + and x0, x0, x1 + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore)) + cmp w0, w1 + b.ne 1f + mov x0, #1 + ret +1: + mov x0, #0 + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 4) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition) + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHe= lper.S b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper= .S new file mode 100644 index 000000000000..35743b08dc88 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.S @@ -0,0 +1,97 @@ +# +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +#include +#include + +#include + +ASM_FUNC(ArmPlatformPeiBootAction) + bx lr + +# IN None +# OUT r0 =3D SCU Base Address +ASM_FUNC(ArmGetScuBaseAddress) + # Read Configuration Base Address Register. ArmCBar cannot be called to = get + # the Configuration BAR as a stack is not necessary setup. The SCU is at= the + # offset 0x0000 from the Private Memory Region. + mrc p15, 4, r0, c15, c0, 0 + bx lr + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (r0, FixedPcdGet32 (PcdArmPrimaryCore)) + bx lr + +# IN None +# OUT r0 =3D number of cores present in the system +ASM_FUNC(ArmGetCpuCountPerCluster) + stmfd SP!, {r1-r2} + + # Read CP15 MIDR + mrc p15, 0, r1, c0, c0, 0 + + # Check if the CPU is A15 + mov r1, r1, LSR #4 + MOV32 (r0, ARM_CPU_TYPE_MASK) + and r1, r1, r0 + + MOV32 (r0, ARM_CPU_TYPE_A15) + cmp r1, r0 + beq _Read_cp15_reg + +_CPU_is_not_A15: + mov r2, lr @ Save link register + bl ArmGetScuBaseAddress @ Read SCU Base Address + mov lr, r2 @ Restore link register val + ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get C= PU count + b _Return + +_Read_cp15_reg: + mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get= CPU count + lsr r0, #24 + +_Return: + and r0, r0, #3 + # Add '1' to the number of CPU on the Cluster + add r0, r0, #1 + ldmfd SP!, {r1-r2} + bx lr + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCoreMask)) + and r0, r0, r1 + MOV32 (r1, FixedPcdGet32 (PcdArmPrimaryCore)) + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformGetCorePosition) + and r1, r0, #ARM_CORE_MASK + and r0, r0, #ARM_CLUSTER_MASK + add r0, r1, r0, LSR #7 + bx lr + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHe= lper.asm b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelp= er.asm new file mode 100644 index 000000000000..66068e6595db --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.asm @@ -0,0 +1,118 @@ +// +// Copyright (c) 2011-2013, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the = BSD License +// which accompanies this distribution. The full text of the license may= be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. +// +// + +#include +#include +#include + +#include + +#include + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformPeiBootAction + EXPORT ArmGetCpuCountPerCluster + EXPORT ArmPlatformIsPrimaryCore + EXPORT ArmPlatformGetPrimaryCoreMpId + EXPORT ArmPlatformGetCorePosition + + AREA RTSMHelper, CODE, READONLY + +ArmPlatformPeiBootAction FUNCTION + bx lr + ENDFUNC + +// IN None +// OUT r0 =3D SCU Base Address +ArmGetScuBaseAddress FUNCTION + // Read Configuration Base Address Register. ArmCBar cannot be called to= get + // the Configuration BAR as a stack is not necessary setup. The SCU is a= t the + // offset 0x0000 from the Private Memory Region. + mrc p15, 4, r0, c15, c0, 0 + bx lr + ENDFUNC + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ArmPlatformGetPrimaryCoreMpId FUNCTION + mov32 r0, FixedPcdGet32(PcdArmPrimaryCore) + bx lr + ENDFUNC + +// IN None +// OUT r0 =3D number of cores present in the system +ArmGetCpuCountPerCluster FUNCTION + stmfd SP!, {r1-r2} + + // Read CP15 MIDR + mrc p15, 0, r1, c0, c0, 0 + + // Check if the CPU is A15 + mov r1, r1, LSR #4 + mov r0, #ARM_CPU_TYPE_MASK + and r1, r1, r0 + + mov r0, #ARM_CPU_TYPE_A15 + cmp r1, r0 + beq _Read_cp15_reg + +_CPU_is_not_A15 + mov r2, lr ; Save link register + bl ArmGetScuBaseAddress ; Read SCU Base Address + mov lr, r2 ; Restore link register val + ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get C= PU count + b _Return + +_Read_cp15_reg + mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get= CPU count + lsr r0, #24 + + +_Return + and r0, r0, #3 + // Add '1' to the number of CPU on the Cluster + add r0, r0, #1 + ldmfd SP!, {r1-r2} + bx lr + ENDFUNC + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ArmPlatformIsPrimaryCore FUNCTION + mov32 r1, FixedPcdGet32(PcdArmPrimaryCoreMask) + and r0, r0, r1 + mov32 r1, FixedPcdGet32(PcdArmPrimaryCore) + ldr r1, [r1] + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr + ENDFUNC + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ArmPlatformGetCorePosition FUNCTION + and r1, r0, #ARM_CORE_MASK + and r0, r0, #ARM_CLUSTER_MASK + add r0, r1, r0, LSR #7 + bx lr + ENDFUNC + + END diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpres= sLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressL= ib.inf new file mode 100644 index 000000000000..2322ee6a2cc5 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf @@ -0,0 +1,63 @@ +#/* @file +# Copyright (c) 2011-2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#*/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RTSMArmVExpressLib + FILE_GUID =3D b98a6cb7-d472-4128-ad62-a7347f85ce13 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + IoLib + ArmLib + MemoryAllocationLib + SerialPortLib + HobLib + +[Sources.common] + RTSM.c + RTSMMem.c + +[Sources.ARM] + Arm/RTSMHelper.asm | RVCT + Arm/RTSMHelper.S | GCC + +[Sources.AARCH64] + AArch64/RTSMHelper.S + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gArmPlatformTokenSpaceGuid.PcdCoreCount + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpres= sLibSec.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpre= ssLibSec.inf new file mode 100644 index 000000000000..e659f44ad232 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec= .inf @@ -0,0 +1,59 @@ +#/* @file +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#*/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RTSMArmVExpressLibSec + FILE_GUID =3D a79eed97-4b98-4974-9690-37b32d6a5b56 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + IoLib + ArmLib + SerialPortLib + +[Sources.common] + RTSM.c + +[Sources.ARM] + Arm/RTSMHelper.asm | RVCT + Arm/RTSMHelper.S | GCC + +[Sources.AARCH64] + AArch64/RTSMHelper.S + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gArmPlatformTokenSpaceGuid.PcdCoreCount + +[Ppis] + gArmMpCoreInfoPpiGuid diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c b/P= latform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c new file mode 100644 index 000000000000..7760e8252125 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSM.c @@ -0,0 +1,195 @@ +/** @file +* +* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include + +#include + +#include + +/** + Return the core per cluster. The method may differ per core type + + This function might be called from assembler before any stack is set. + + @return Return the core count per cluster + +**/ +UINTN +ArmGetCpuCountPerCluster ( + VOID + ); + +ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 2 + 0x0, 0x2, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 3 + 0x0, 0x3, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 0 + 0x1, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 1 + 0x1, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 2 + 0x1, 0x2, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 1, Core 3 + 0x1, 0x3, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + } +}; + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/= PlatformPeim + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + if (!ArmPlatformIsPrimaryCore (MpId)) { + return RETURN_SUCCESS; + } + + // Disable memory remapping and return to normal mapping + MmioOr32 (SP810_CTRL_BASE, BIT8); + + return RETURN_SUCCESS; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + UINT32 ProcType; + + ProcType =3D MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MA= SK; + if ((ProcType =3D=3D ARM_VE_SYS_PROC_ID_CORTEX_A9) || (ProcType =3D=3D A= RM_VE_SYS_PROC_ID_CORTEX_A15)) { + // Only support one cluster on all but ARMv8 FVP platform. FVP still u= ses CortexA9 ID. + *CoreCount =3D ArmGetCpuCountPerCluster (); + *ArmCoreTable =3D mVersatileExpressMpCoreInfoTable; + return EFI_SUCCESS; + } else { + return EFI_UNSUPPORTED; + } +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof(gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c = b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c new file mode 100644 index 000000000000..6379e81751fc --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -0,0 +1,161 @@ +/** @file +* +* Copyright (c) 2011-2016, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include + +// Number of Virtual Memory Map Descriptors +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUF= FERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize + the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR + describing a Physical-to-Virtual Memory + mapping. This array must be ended by a + zero-filled entry. + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + UINTN Index =3D 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + UINT32 SysId; + BOOLEAN HasSparseMemory; + EFI_VIRTUAL_ADDRESS SparseMemoryBase; + UINT64 SparseMemorySize; + + ASSERT (VirtualMemoryMap !=3D NULL); + + // The FVP model has Sparse memory + SysId =3D MmioRead32 (ARM_VE_SYS_ID_REG); + if (SysId !=3D ARM_RTSM_SYS_ID) { + HasSparseMemory =3D TRUE; + + ResourceAttributes =3D + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + + // Declared the additional DRAM from 2GB to 4GB + SparseMemoryBase =3D 0x0880000000; + SparseMemorySize =3D SIZE_2GB; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + SparseMemoryBase, + SparseMemorySize); + } else { + HasSparseMemory =3D FALSE; + SparseMemoryBase =3D 0x0; + SparseMemorySize =3D 0x0; + } + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*) + AllocatePages (EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) + * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS= )); + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + CacheAttributes =3D (FeaturePcdGet(PcdCacheEnable)) + ? DDR_ATTRIBUTES_CACHED + : DDR_ATTRIBUTES_UNCACHED; + + // ReMap (Either NOR Flash or DRAM) + VirtualMemoryTable[Index].PhysicalBase =3D ARM_VE_REMAP_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_REMAP_BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_REMAP_SZ; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // DDR + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_DRAM_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_DRAM_BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_DRAM_SZ; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // CPU peripherals. TRM. Manual says not all of them are implemented. + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_ON_CHIP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_ON_CHIP_PERIPH_BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_ON_CHIP_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_DEV= ICE; + + // SMB CS0-CS1 - NOR Flash 1 & 2 + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR= 1_SZ; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // SMB CS2 - SRAM + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_SRAM_BASE; + VirtualMemoryTable[Index].Length =3D ARM_VE_SMB_SRAM_SZ; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // Peripheral CS2 and CS3 + VirtualMemoryTable[++Index].PhysicalBase =3D ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase =3D ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].Length =3D 2 * ARM_VE_SMB_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_DEV= ICE; + + // VRAM + VirtualMemoryTable[++Index].PhysicalBase =3D PL111_CLCD_VRAM_MOTHERBOARD= _BASE; + VirtualMemoryTable[Index].VirtualBase =3D PL111_CLCD_VRAM_MOTHERBOARD_BA= SE; + VirtualMemoryTable[Index].Length =3D PL111_CLCD_VRAM_MOTHERBOARD_SIZE; + // + // Map the VRAM region as Normal Non-Cacheable memory and not device mem= ory, + // so that we can use the accelerated string routines that may use unali= gned + // accesses or DC ZVA instructions. The enum identifier is slightly awkw= ard + // here, but it maps to a memory type that allows buffering and reorderi= ng. + // + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_UNC= ACHED_UNBUFFERED; + + // Map sparse memory region if present + if (HasSparseMemory) { + VirtualMemoryTable[++Index].PhysicalBase =3D SparseMemoryBase; + VirtualMemoryTable[Index].VirtualBase =3D SparseMemoryBase; + VirtualMemoryTable[Index].Length =3D SparseMemorySize; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + } + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT (Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + *VirtualMemoryMap =3D VirtualMemoryTable; +} diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigLib/ArmVE= xpressSysConfig.c b/Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigLi= b/ArmVExpressSysConfig.c new file mode 100644 index 000000000000..6dfbacd11762 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressS= ysConfig.c @@ -0,0 +1,273 @@ +/** @file ArmVExpressSysConfig.c + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include + +#include +#include + +// +// SYS_CFGCTRL Bits +// +#define SYS_CFGCTRL_START BIT31 +#define SYS_CFGCTRL_READ (0 << 30) +#define SYS_CFGCTRL_WRITE (1 << 30) +#define SYS_CFGCTRL_FUNCTION(fun) (((fun ) & 0x3F) << 20) +#define SYS_CFGCTRL_SITE(site) (((site) & 0x3) << 16) +#define SYS_CFGCTRL_POSITION(pos) (((pos ) & 0xF) << 12) +#define SYS_CFGCTRL_DEVICE(dev) ((dev ) & 0xFFF) + +// +// SYS_CFGSTAT Bits +// +#define SYS_CFGSTAT_ERROR BIT1 +#define SYS_CFGSTAT_COMPLETE BIT0 + +/*************************************************************************= *** + * + * This file makes it easier to access the System Configuration Registers + * in the ARM Versatile Express motherboard. + * + *************************************************************************= ***/ + +RETURN_STATUS +ArmPlatformSysConfigInitialize ( + VOID + ) +{ + return RETURN_SUCCESS; +} + +/*************************************** + * GENERAL FUNCTION: AccessSysCfgRegister + * Interacts with + * SYS_CFGSTAT + * SYS_CFGDATA + * SYS_CFGCTRL + * for setting and for reading out values + ***************************************/ + +RETURN_STATUS +AccessSysCfgRegister ( + IN UINT32 ReadWrite, + IN UINT32 Function, + IN UINT32 Site, + IN UINT32 Position, + IN UINT32 Device, + IN OUT UINT32* Data + ) +{ + UINT32 SysCfgCtrl; + + // Clear the COMPLETE bit + MmioAnd32(ARM_VE_SYS_CFGSTAT_REG, ~SYS_CFGSTAT_COMPLETE); + + // If writing, then set the data value + if(ReadWrite =3D=3D SYS_CFGCTRL_WRITE) { + MmioWrite32(ARM_VE_SYS_CFGDATA_REG, *Data); + } + + // Set the control value + SysCfgCtrl =3D SYS_CFGCTRL_START | ReadWrite | SYS_CFGCTRL_FUNCTION(Func= tion) | SYS_CFGCTRL_SITE(Site) | + SYS_CFGCTRL_POSITION(Position) | SYS_CFGCTRL_DEVICE(Device); + MmioWrite32(ARM_VE_SYS_CFGCTRL_REG, SysCfgCtrl); + + // Wait until the COMPLETE bit is set + while ((MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_COMPLETE) =3D= =3D 0); + + // Check for errors + if(MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_ERROR) { + return RETURN_DEVICE_ERROR; + } + + // If reading then get the data value + if(ReadWrite =3D=3D SYS_CFGCTRL_READ) { + *Data =3D MmioRead32(ARM_VE_SYS_CFGDATA_REG); + } + + return RETURN_SUCCESS; +} + +RETURN_STATUS +ArmPlatformSysConfigGet ( + IN SYS_CONFIG_FUNCTION Function, + OUT UINT32* Value + ) +{ + UINT32 Site; + UINT32 Position; + UINT32 Device; + + Position =3D 0; + Device =3D 0; + + // Intercept some functions + switch(Function) { + + case SYS_CFG_OSC_SITE1: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_1_SITE; + break; + + case SYS_CFG_OSC_SITE2: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_2_SITE; + break; + + case SYS_CFG_MUXFPGA: + Site =3D *Value; + break; + + case SYS_CFG_OSC: + case SYS_CFG_VOLT: + case SYS_CFG_AMP: + case SYS_CFG_TEMP: + case SYS_CFG_RESET: + case SYS_CFG_SCC: + case SYS_CFG_DVIMODE: + case SYS_CFG_POWER: + Site =3D ARM_VE_MOTHERBOARD_SITE; + break; + + case SYS_CFG_SHUTDOWN: + case SYS_CFG_REBOOT: + case SYS_CFG_RTC: + default: + return RETURN_UNSUPPORTED; + } + + return AccessSysCfgRegister (SYS_CFGCTRL_READ, Function, Site, Position,= Device, Value); +} + +RETURN_STATUS +ArmPlatformSysConfigGetValues ( + IN SYS_CONFIG_FUNCTION Function, + IN UINTN Size, + OUT UINT32* Values + ) +{ + return RETURN_UNSUPPORTED; +} + +RETURN_STATUS +ArmPlatformSysConfigSet ( + IN SYS_CONFIG_FUNCTION Function, + IN UINT32 Value + ) +{ + UINT32 Site; + UINT32 Position; + UINT32 Device; + + Position =3D 0; + Device =3D 0; + + // Intercept some functions + switch(Function) { + + case SYS_CFG_OSC_SITE1: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_1_SITE; + break; + + case SYS_CFG_OSC_SITE2: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_2_SITE; + break; + + case SYS_CFG_MUXFPGA: + Site =3D Value; + break; + + case SYS_CFG_RESET: + case SYS_CFG_SCC: + case SYS_CFG_SHUTDOWN: + case SYS_CFG_REBOOT: + case SYS_CFG_DVIMODE: + case SYS_CFG_POWER: + Site =3D ARM_VE_MOTHERBOARD_SITE; + break; + + case SYS_CFG_OSC: + case SYS_CFG_VOLT: + case SYS_CFG_AMP: + case SYS_CFG_TEMP: + case SYS_CFG_RTC: + default: + return RETURN_UNSUPPORTED; + } + + return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position= , Device, &Value); +} + +RETURN_STATUS +ArmPlatformSysConfigSetDevice ( + IN SYS_CONFIG_FUNCTION Function, + IN UINT32 Device, + IN UINT32 Value + ) +{ + UINT32 Site; + UINT32 Position; + + Position =3D 0; + + // Intercept some functions + switch(Function) { + case SYS_CFG_SCC: +#ifdef ARM_VE_SCC_BASE + MmioWrite32 ((ARM_VE_SCC_BASE + (Device * 4)),Value); + return RETURN_SUCCESS; +#else + // There is no System Configuration Controller on the Model + return RETURN_UNSUPPORTED; +#endif + + case SYS_CFG_OSC_SITE1: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_1_SITE; + break; + + case SYS_CFG_OSC_SITE2: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_2_SITE; + break; + + case SYS_CFG_MUXFPGA: + Site =3D Value; + break; + + case SYS_CFG_RTC: + return RETURN_UNSUPPORTED; + //break; + + case SYS_CFG_OSC: + case SYS_CFG_VOLT: + case SYS_CFG_AMP: + case SYS_CFG_TEMP: + case SYS_CFG_RESET: + case SYS_CFG_SHUTDOWN: + case SYS_CFG_REBOOT: + case SYS_CFG_DVIMODE: + case SYS_CFG_POWER: + Site =3D ARM_VE_MOTHERBOARD_SITE; + break; + default: + return RETURN_UNSUPPORTED; + } + + return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position= , Device, &Value); +} diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigLib/ArmVE= xpressSysConfigLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressSysCon= figLib/ArmVExpressSysConfigLib.inf new file mode 100644 index 000000000000..c400ab831ab1 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressS= ysConfigLib.inf @@ -0,0 +1,35 @@ +#/** @file +# +# Component description file for ArmVExpressSysConfigLib module +# +# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ArmVExpressSysConfigLib + FILE_GUID =3D a05b5cc0-82d2-11e0-82cb-0002a5d5c51b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformSysConfigLib|SEC DXE_DRIVER + +[Sources.common] + ArmVExpressSysConfig.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + BaseLib + IoLib diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigRuntimeLi= b/ArmVExpressSysConfigRuntimeLib.c b/Platform/ARM/VExpressPkg/Library/ArmVE= xpressSysConfigRuntimeLib/ArmVExpressSysConfigRuntimeLib.c new file mode 100644 index 000000000000..1f915e3b0225 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigRuntimeLib/ArmVE= xpressSysConfigRuntimeLib.c @@ -0,0 +1,283 @@ +/** @file ArmVExpressSysConfig.c + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include + +#include +#include + +#include +#include + +// +// SYS_CFGCTRL Bits +// +#define SYS_CFGCTRL_START BIT31 +#define SYS_CFGCTRL_READ (0 << 30) +#define SYS_CFGCTRL_WRITE (1 << 30) +#define SYS_CFGCTRL_FUNCTION(fun) (((fun ) & 0x3F) << 20) +#define SYS_CFGCTRL_SITE(site) (((site) & 0x3) << 16) +#define SYS_CFGCTRL_POSITION(pos) (((pos ) & 0xF) << 12) +#define SYS_CFGCTRL_DEVICE(dev) ((dev ) & 0xFFF) + +// +// SYS_CFGSTAT Bits +// +#define SYS_CFGSTAT_ERROR BIT1 +#define SYS_CFGSTAT_COMPLETE BIT0 + +/*************************************************************************= *** + * + * This file makes it easier to access the System Configuration Registers + * in the ARM Versatile Express motherboard. + * + *************************************************************************= ***/ + +RETURN_STATUS +ArmPlatformSysConfigInitialize ( + VOID + ) +{ + return RETURN_SUCCESS; +} + +/*************************************** + * GENERAL FUNCTION: AccessSysCfgRegister + * Interacts with + * SYS_CFGSTAT + * SYS_CFGDATA + * SYS_CFGCTRL + * for setting and for reading out values + ***************************************/ + +RETURN_STATUS +AccessSysCfgRegister ( + IN UINT32 ReadWrite, + IN UINT32 Function, + IN UINT32 Site, + IN UINT32 Position, + IN UINT32 Device, + IN OUT UINT32* Data + ) +{ + UINT32 SysCfgCtrl; + + if (EfiAtRuntime ()) { + return RETURN_UNSUPPORTED; + } + + // Clear the COMPLETE bit + MmioAnd32(ARM_VE_SYS_CFGSTAT_REG, ~SYS_CFGSTAT_COMPLETE); + + // If writing, then set the data value + if(ReadWrite =3D=3D SYS_CFGCTRL_WRITE) { + MmioWrite32(ARM_VE_SYS_CFGDATA_REG, *Data); + } + + // Set the control value + SysCfgCtrl =3D SYS_CFGCTRL_START | ReadWrite | SYS_CFGCTRL_FUNCTION(Func= tion) | SYS_CFGCTRL_SITE(Site) | + SYS_CFGCTRL_POSITION(Position) | SYS_CFGCTRL_DEVICE(Device); + MmioWrite32(ARM_VE_SYS_CFGCTRL_REG, SysCfgCtrl); + + // Wait until the COMPLETE bit is set + while ((MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_COMPLETE) =3D= =3D 0); + + // Check for errors + if(MmioRead32(ARM_VE_SYS_CFGSTAT_REG) & SYS_CFGSTAT_ERROR) { + return RETURN_DEVICE_ERROR; + } + + // If reading then get the data value + if(ReadWrite =3D=3D SYS_CFGCTRL_READ) { + *Data =3D MmioRead32(ARM_VE_SYS_CFGDATA_REG); + } + + return RETURN_SUCCESS; +} + +RETURN_STATUS +ArmPlatformSysConfigGet ( + IN SYS_CONFIG_FUNCTION Function, + OUT UINT32* Value + ) +{ + UINT32 Site; + UINT32 Position; + UINT32 Device; + + Position =3D 0; + Device =3D 0; + + // Intercept some functions + switch(Function) { + + case SYS_CFG_OSC_SITE1: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_1_SITE; + break; + + case SYS_CFG_OSC_SITE2: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_2_SITE; + break; + + case SYS_CFG_MUXFPGA: + Site =3D *Value; + break; + + case SYS_CFG_OSC: + case SYS_CFG_VOLT: + case SYS_CFG_AMP: + case SYS_CFG_TEMP: + case SYS_CFG_RESET: + case SYS_CFG_SCC: + case SYS_CFG_DVIMODE: + case SYS_CFG_POWER: + Site =3D ARM_VE_MOTHERBOARD_SITE; + break; + + case SYS_CFG_SHUTDOWN: + case SYS_CFG_REBOOT: + case SYS_CFG_RTC: + default: + return RETURN_UNSUPPORTED; + } + + return AccessSysCfgRegister (SYS_CFGCTRL_READ, Function, Site, Position,= Device, Value); +} + +RETURN_STATUS +ArmPlatformSysConfigGetValues ( + IN SYS_CONFIG_FUNCTION Function, + IN UINTN Size, + OUT UINT32* Values + ) +{ + return RETURN_UNSUPPORTED; +} + +RETURN_STATUS +ArmPlatformSysConfigSet ( + IN SYS_CONFIG_FUNCTION Function, + IN UINT32 Value + ) +{ + UINT32 Site; + UINT32 Position; + UINT32 Device; + + Position =3D 0; + Device =3D 0; + + // Intercept some functions + switch(Function) { + + case SYS_CFG_OSC_SITE1: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_1_SITE; + break; + + case SYS_CFG_OSC_SITE2: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_2_SITE; + break; + + case SYS_CFG_MUXFPGA: + Site =3D Value; + break; + + case SYS_CFG_RESET: + case SYS_CFG_SCC: + case SYS_CFG_SHUTDOWN: + case SYS_CFG_REBOOT: + case SYS_CFG_DVIMODE: + case SYS_CFG_POWER: + Site =3D ARM_VE_MOTHERBOARD_SITE; + break; + + case SYS_CFG_OSC: + case SYS_CFG_VOLT: + case SYS_CFG_AMP: + case SYS_CFG_TEMP: + case SYS_CFG_RTC: + default: + return RETURN_UNSUPPORTED; + } + + return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position= , Device, &Value); +} + +RETURN_STATUS +ArmPlatformSysConfigSetDevice ( + IN SYS_CONFIG_FUNCTION Function, + IN UINT32 Device, + IN UINT32 Value + ) +{ + UINT32 Site; + UINT32 Position; + + Position =3D 0; + + // Intercept some functions + switch(Function) { + case SYS_CFG_SCC: +#ifdef ARM_VE_SCC_BASE + if (EfiAtRuntime ()) { + return RETURN_UNSUPPORTED; + } + MmioWrite32 ((ARM_VE_SCC_BASE + (Device * 4)),Value); + return RETURN_SUCCESS; +#else + // There is no System Configuration Controller on the Model + return RETURN_UNSUPPORTED; +#endif + + case SYS_CFG_OSC_SITE1: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_1_SITE; + break; + + case SYS_CFG_OSC_SITE2: + Function =3D SYS_CFG_OSC; + Site =3D ARM_VE_DAUGHTERBOARD_2_SITE; + break; + + case SYS_CFG_MUXFPGA: + Site =3D Value; + break; + + case SYS_CFG_RTC: + return RETURN_UNSUPPORTED; + //break; + + case SYS_CFG_OSC: + case SYS_CFG_VOLT: + case SYS_CFG_AMP: + case SYS_CFG_TEMP: + case SYS_CFG_RESET: + case SYS_CFG_SHUTDOWN: + case SYS_CFG_REBOOT: + case SYS_CFG_DVIMODE: + case SYS_CFG_POWER: + Site =3D ARM_VE_MOTHERBOARD_SITE; + break; + default: + return RETURN_UNSUPPORTED; + } + + return AccessSysCfgRegister (SYS_CFGCTRL_WRITE, Function, Site, Position= , Device, &Value); +} diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigRuntimeLi= b/ArmVExpressSysConfigRuntimeLib.inf b/Platform/ARM/VExpressPkg/Library/Arm= VExpressSysConfigRuntimeLib/ArmVExpressSysConfigRuntimeLib.inf new file mode 100644 index 000000000000..cce8b9096f6d --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigRuntimeLib/ArmVE= xpressSysConfigRuntimeLib.inf @@ -0,0 +1,37 @@ +#/** @file +# +# Component description file for ArmVExpressSysConfigRuntimeLib module +# +# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# Copyright (c) 2015, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ArmVExpressSysConfigRuntimeLib + FILE_GUID =3D 6275b819-615c-4a36-814a-c1f330b4e5d9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformSysConfigLib|DXE_RUNTIME_D= RIVER + +[Sources.common] + ArmVExpressSysConfigRuntimeLib.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + BaseLib + IoLib + UefiRuntimeLib diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= Express.c b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVE= xpress.c new file mode 100644 index 000000000000..b1106ee19b98 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= .c @@ -0,0 +1,285 @@ +/** + + Copyright (c) 2012, ARM Ltd. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +typedef struct { + UINT32 Mode; + UINT32 HorizontalResolution; + UINT32 VerticalResolution; + LCD_BPP Bpp; + UINT32 OscFreq; + + // These are used by HDLCD + UINT32 HSync; + UINT32 HBackPorch; + UINT32 HFrontPorch; + UINT32 VSync; + UINT32 VBackPorch; + UINT32 VFrontPorch; +} LCD_RESOLUTION; + + +LCD_RESOLUTION mResolutions[] =3D { + { // Mode 0 : VGA : 640 x 480 x 24 bpp + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_OS= C_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + }, + { // Mode 1 : SVGA : 800 x 600 x 24 bpp + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, SVG= A_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + }, + { // Mode 2 : XGA : 1024 x 768 x 24 bpp + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_OS= C_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + }, + { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (SX= GA_OSC_FREQUENCY/2), + SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, + SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + }, + { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (UX= GA_OSC_FREQUENCY/2), + UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, + UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + }, + { // Mode 5 : HD : 1920 x 1080 x 24 bpp + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC_F= REQUENCY/2), + HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, + HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + } +}; + +EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered =3D { + 0, + NULL +}; + +EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { + 0, + NULL +}; + +EFI_STATUS +LcdPlatformInitializeDisplay ( + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + + // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard + Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); + if (EFI_ERROR(Status)) { + return Status; + } + + // Install the EDID Protocols + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, + &gEfiEdidActiveProtocolGuid, &mEdidActive, + NULL + ); + + return Status; +} + +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, + OUT UINTN* VramSize + ) +{ + EFI_STATUS Status; + EFI_ALLOCATE_TYPE AllocationType; + + // Set the vram size + *VramSize =3D LCD_VRAM_SIZE; + + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS)LCD_VRAM_CORE_TILE_BASE; + + // Allocate the VRAM from the DRAM so that nobody else uses it. + if (*VramBaseAddress =3D=3D 0) { + AllocationType =3D AllocateAnyPages; + } else { + AllocationType =3D AllocateAddress; + } + Status =3D gBS->AllocatePages (AllocationType, EfiBootServicesData, EFI_= SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); + if (EFI_ERROR(Status)) { + return Status; + } + + // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which = is cacheable. + Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, + EFI_MEMORY_WC); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); + return Status; + } + + return EFI_SUCCESS; +} + +UINT32 +LcdPlatformGetMaxMode ( + VOID + ) +{ + // + // The following line will report correctly the total number of graphics= modes + // that could be supported by the graphics driver: + // + return (sizeof(mResolutions) / sizeof(LCD_RESOLUTION)); +} + +EFI_STATUS +LcdPlatformSetMode ( + IN UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + // Set the video mode oscillator + do { + Status =3D ArmPlatformSysConfigSetDevice (SYS_CFG_OSC_SITE1, PcdGet32(= PcdHdLcdVideoModeOscId), mResolutions[ModeNumber].OscFreq); + } while (Status =3D=3D EFI_TIMEOUT); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // Set the DVI into the new mode + do { + Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mode= Number].Mode); + } while (Status =3D=3D EFI_TIMEOUT); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // Set the multiplexer + Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, ARM_VE_DAUGHTERBOAR= D_1_SITE); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + return Status; +} + +EFI_STATUS +LcdPlatformQueryMode ( + IN UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + Info->Version =3D 0; + Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; + Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; + Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; + + switch (mResolutions[ModeNumber].Bpp) { + case LCD_BITS_PER_PIXEL_24: + Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; + Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; + break; + + case LCD_BITS_PER_PIXEL_16_555: + case LCD_BITS_PER_PIXEL_16_565: + case LCD_BITS_PER_PIXEL_12_444: + case LCD_BITS_PER_PIXEL_8: + case LCD_BITS_PER_PIXEL_4: + case LCD_BITS_PER_PIXEL_2: + case LCD_BITS_PER_PIXEL_1: + default: + // These are not supported + ASSERT(FALSE); + break; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdPlatformGetTimings ( + IN UINT32 ModeNumber, + OUT UINT32* HRes, + OUT UINT32* HSync, + OUT UINT32* HBackPorch, + OUT UINT32* HFrontPorch, + OUT UINT32* VRes, + OUT UINT32* VSync, + OUT UINT32* VBackPorch, + OUT UINT32* VFrontPorch + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + *HRes =3D mResolutions[ModeNumber].HorizontalResolution; + *HSync =3D mResolutions[ModeNumber].HSync; + *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; + *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; + *VRes =3D mResolutions[ModeNumber].VerticalResolution; + *VSync =3D mResolutions[ModeNumber].VSync; + *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; + *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdPlatformGetBpp ( + IN UINT32 ModeNumber, + OUT LCD_BPP * Bpp + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + *Bpp =3D mResolutions[ModeNumber].Bpp; + + return EFI_SUCCESS; +} diff --git a/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmV= ExpressLib.inf b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcd= ArmVExpressLib.inf new file mode 100644 index 000000000000..fc51c781b451 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress= Lib.inf @@ -0,0 +1,45 @@ +#/** @file +# +# Component description file for HdLcdArmLib module +# +# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D HdLcdArmVExpress + FILE_GUID =3D 535a720e-06c0-4bb9-b563-452216abbed4 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdPlatformLib + +[Sources.common] + +HdLcdArmVExpress.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + ArmPlatformSysConfigLib + BaseLib + DxeServicesTableLib + +[Protocols] + gEfiEdidDiscoveredProtocolGuid # Produced + gEfiEdidActiveProtocolGuid # Produced + +[Pcd] + gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode + gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId diff --git a/Platform/ARM/VExpressPkg/Library/NorFlashArmVExpressLib/NorFla= shArmVExpress.c b/Platform/ARM/VExpressPkg/Library/NorFlashArmVExpressLib/N= orFlashArmVExpress.c new file mode 100644 index 000000000000..a136bff4a1d6 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVE= xpress.c @@ -0,0 +1,84 @@ +/** @file + + Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + **/ + +#include +#include +#include +#include +#include + +#define NOR_FLASH_DEVICE_COUNT 4 + +NOR_FLASH_DESCRIPTION mNorFlashDevices[NOR_FLASH_DEVICE_COUNT] =3D { + { // BootMon + ARM_VE_SMB_NOR0_BASE, + ARM_VE_SMB_NOR0_BASE, + SIZE_256KB * 255, + SIZE_256KB, + { 0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x= 5E, 0x59 } } + }, + { // BootMon non-volatile storage + ARM_VE_SMB_NOR0_BASE, + ARM_VE_SMB_NOR0_BASE + SIZE_256KB * 255, + SIZE_64KB * 4, + SIZE_64KB, + { 0x02118005, 0x9DA7, 0x443A, { 0x92, 0xD5, 0x78, 0x1F, 0x02, 0x2A, 0x= ED, 0xBB } } + }, + { // UEFI + ARM_VE_SMB_NOR1_BASE, + ARM_VE_SMB_NOR1_BASE, + SIZE_256KB * 255, + SIZE_256KB, + { 0x1F15DA3C, 0x37FF, 0x4070, { 0xB4, 0x71, 0xBB, 0x4A, 0xF1, 0x2A, 0x= 72, 0x4A } } + }, + { // UEFI Variable Services non-volatile storage + ARM_VE_SMB_NOR1_BASE, + ARM_VE_SMB_NOR1_BASE + SIZE_256KB * 255, + SIZE_64KB * 3, //FIXME: Set 3 blocks because I did not succeed to copy= 4 blocks into the ARM Versatile Express NOR Flash in the last NOR Flash. I= t should be 4 blocks + SIZE_64KB, + { 0xCC2CBF29, 0x1498, 0x4CDD, { 0x81, 0x71, 0xF8, 0xB6, 0xB4, 0x1D, 0x= 09, 0x09 } } + } +}; + +EFI_STATUS +NorFlashPlatformInitialization ( + VOID + ) +{ + // Everything seems ok so far, so now we need to disable the platform-sp= ecific + // flash write protection for Versatile Express + if ((MmioRead32 (ARM_VE_SYS_FLASH) & 0x1) =3D=3D 0) { + // Writing to NOR FLASH is disabled, so enable it + MmioWrite32 (ARM_VE_SYS_FLASH,1); + DEBUG((DEBUG_BLKIO, "NorFlashWriteBlocks: informational - Had to enabl= e HSYS_FLASH flag.\n" )); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashPlatformGetDevices ( + OUT NOR_FLASH_DESCRIPTION **NorFlashDevices, + OUT UINT32 *Count + ) +{ + if ((NorFlashDevices =3D=3D NULL) || (Count =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + *NorFlashDevices =3D mNorFlashDevices; + *Count =3D NOR_FLASH_DEVICE_COUNT; + + return EFI_SUCCESS; +} diff --git a/Platform/ARM/VExpressPkg/Library/NorFlashArmVExpressLib/NorFla= shArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/NorFlashArmVExpress= Lib/NorFlashArmVExpressLib.inf new file mode 100644 index 000000000000..6c0ca97c9900 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVE= xpressLib.inf @@ -0,0 +1,33 @@ +#/** @file +# +# Copyright (c) 2011, ARM Ltd. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D NorFlashArmVExpressLib + FILE_GUID =3D c0f5dfa0-7599-11e0-9665-0002a5d5c51b + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NorFlashPlatformLib + +[Sources.common] + NorFlashArmVExpress.c + +[Packages] + MdePkg/MdePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpress.c b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/P= L111LcdArmVExpress.c new file mode 100644 index 000000000000..3f3ceb3d2fa8 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpress.c @@ -0,0 +1,370 @@ +/** @file + + Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +typedef struct { + UINT32 Mode; + UINT32 HorizontalResolution; + UINT32 VerticalResolution; + LCD_BPP Bpp; + UINT32 OscFreq; + + UINT32 HSync; + UINT32 HBackPorch; + UINT32 HFrontPorch; + UINT32 VSync; + UINT32 VBackPorch; + UINT32 VFrontPorch; +} LCD_RESOLUTION; + + +LCD_RESOLUTION mResolutions[] =3D { + { // Mode 0 : VGA : 640 x 480 x 24 bpp + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, VGA_= OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + }, + { // Mode 1 : SVGA : 800 x 600 x 24 bpp + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, S= VGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + }, + { // Mode 2 : XGA : 1024 x 768 x 24 bpp + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, XGA_= OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + }, + { // Mode 3 : SXGA : 1280 x 1024 x 24 bpp + SXGA, SXGA_H_RES_PIXELS, SXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= SXGA_OSC_FREQUENCY/2), + SXGA_H_SYNC, SXGA_H_BACK_PORCH, SXGA_H_FRONT_PORCH, + SXGA_V_SYNC, SXGA_V_BACK_PORCH, SXGA_V_FRONT_PORCH + }, + { // Mode 4 : UXGA : 1600 x 1200 x 24 bpp + UXGA, UXGA_H_RES_PIXELS, UXGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (= UXGA_OSC_FREQUENCY/2), + UXGA_H_SYNC, UXGA_H_BACK_PORCH, UXGA_H_FRONT_PORCH, + UXGA_V_SYNC, UXGA_V_BACK_PORCH, UXGA_V_FRONT_PORCH + }, + { // Mode 5 : HD : 1920 x 1080 x 24 bpp + HD, HD_H_RES_PIXELS, HD_V_RES_PIXELS, LCD_BITS_PER_PIXEL_24, (HD_OSC= _FREQUENCY/2), + HD_H_SYNC, HD_H_BACK_PORCH, HD_H_FRONT_PORCH, + HD_V_SYNC, HD_V_BACK_PORCH, HD_V_FRONT_PORCH + }, + { // Mode 6 : VGA : 640 x 480 x 16 bpp (565 Mode) + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + }, + { // Mode 7 : SVGA : 800 x 600 x 16 bpp (565 Mode) + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_56= 5, SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + }, + { // Mode 8 : XGA : 1024 x 768 x 16 bpp (565 Mode) + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_565, = XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + }, + { // Mode 9 : VGA : 640 x 480 x 15 bpp + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + }, + { // Mode 10 : SVGA : 800 x 600 x 15 bpp + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_55= 5, SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + }, + { // Mode 11 : XGA : 1024 x 768 x 15 bpp + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + }, + { // Mode 12 : XGA : 1024 x 768 x 15 bpp - All the timing info is derive= d from Linux Kernel Driver Settings + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_16_555, = 63500000, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + }, + { // Mode 13 : VGA : 640 x 480 x 12 bpp (444 Mode) + VGA, VGA_H_RES_PIXELS, VGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = VGA_OSC_FREQUENCY, + VGA_H_SYNC, VGA_H_BACK_PORCH, VGA_H_FRONT_PORCH, + VGA_V_SYNC, VGA_V_BACK_PORCH, VGA_V_FRONT_PORCH + }, + { // Mode 14 : SVGA : 800 x 600 x 12 bpp (444 Mode) + SVGA, SVGA_H_RES_PIXELS, SVGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_44= 4, SVGA_OSC_FREQUENCY, + SVGA_H_SYNC, SVGA_H_BACK_PORCH, SVGA_H_FRONT_PORCH, + SVGA_V_SYNC, SVGA_V_BACK_PORCH, SVGA_V_FRONT_PORCH + }, + { // Mode 15 : XGA : 1024 x 768 x 12 bpp (444 Mode) + XGA, XGA_H_RES_PIXELS, XGA_V_RES_PIXELS, LCD_BITS_PER_PIXEL_12_444, = XGA_OSC_FREQUENCY, + XGA_H_SYNC, XGA_H_BACK_PORCH, XGA_H_FRONT_PORCH, + XGA_V_SYNC, XGA_V_BACK_PORCH, XGA_V_FRONT_PORCH + } +}; + +EFI_EDID_DISCOVERED_PROTOCOL mEdidDiscovered =3D { + 0, + NULL +}; + +EFI_EDID_ACTIVE_PROTOCOL mEdidActive =3D { + 0, + NULL +}; + + +EFI_STATUS +LcdPlatformInitializeDisplay ( + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + + // Set the FPGA multiplexer to select the video output from the motherbo= ard or the daughterboard + Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, PL111_CLCD_SITE); + if (!EFI_ERROR(Status)) { + // Install the EDID Protocols + Status =3D gBS->InstallMultipleProtocolInterfaces( + &Handle, + &gEfiEdidDiscoveredProtocolGuid, &mEdidDiscovered, + &gEfiEdidActiveProtocolGuid, &mEdidActive, + NULL + ); + } + + return Status; +} + +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, + OUT UINTN* VramSize + ) +{ + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + // Is it on the motherboard or on the daughterboard? + switch(PL111_CLCD_SITE) { + + case ARM_VE_MOTHERBOARD_SITE: + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) PL111_CLCD_VRAM_MOTHERBOAR= D_BASE; + *VramSize =3D LCD_VRAM_SIZE; + break; + + case ARM_VE_DAUGHTERBOARD_1_SITE: + *VramBaseAddress =3D (EFI_PHYSICAL_ADDRESS) LCD_VRAM_CORE_TILE_BASE; + *VramSize =3D LCD_VRAM_SIZE; + + // Allocate the VRAM from the DRAM so that nobody else uses it. + Status =3D gBS->AllocatePages( AllocateAddress, EfiBootServicesData, E= FI_SIZE_TO_PAGES(((UINTN)LCD_VRAM_SIZE)), VramBaseAddress); + if (EFI_ERROR(Status)) { + return Status; + } + + // Mark the VRAM as write-combining. The VRAM is inside the DRAM, whic= h is cacheable. + Status =3D gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, + EFI_MEMORY_WC); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize)); + return Status; + } + break; + + default: + // Unsupported site + Status =3D EFI_UNSUPPORTED; + break; + } + + return Status; +} + +UINT32 +LcdPlatformGetMaxMode ( + VOID + ) +{ + // The following line will report correctly the total number of graphics= modes + // supported by the PL111CLCD. + //return (sizeof(mResolutions) / sizeof(CLCD_RESOLUTION)) - 1; + + // However, on some platforms it is desirable to ignore some graphics mo= des. + // This could be because the specific implementation of PL111 has certai= n limitations. + + // Set the maximum mode allowed + return (PcdGet32(PcdPL111LcdMaxMode)); +} + +EFI_STATUS +LcdPlatformSetMode ( + IN UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + UINT32 LcdSite; + UINT32 OscillatorId; + SYS_CONFIG_FUNCTION Function; + UINT32 SysId; + + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + LcdSite =3D PL111_CLCD_SITE; + + switch(LcdSite) { + case ARM_VE_MOTHERBOARD_SITE: + Function =3D SYS_CFG_OSC; + OscillatorId =3D PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID; + break; + case ARM_VE_DAUGHTERBOARD_1_SITE: + Function =3D SYS_CFG_OSC_SITE1; + OscillatorId =3D (UINT32)PcdGet32(PcdPL111LcdVideoModeOscId); + break; + default: + return EFI_UNSUPPORTED; + } + + // Set the video mode oscillator + Status =3D ArmPlatformSysConfigSetDevice (Function, OscillatorId, mResol= utions[ModeNumber].OscFreq); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // The FVP foundation model does not have an LCD. + // On the FVP models the GIC variant in encoded in bits [15:12]. + // Note: The DVI Mode is not modelled by RTSM or FVP models. + SysId =3D MmioRead32 (ARM_VE_SYS_ID_REG); + if (SysId !=3D ARM_RTSM_SYS_ID) { + // Take out the FVP GIC variant to reduce the permutations. + SysId &=3D ~ARM_FVP_SYS_ID_VARIANT_MASK; + if (SysId !=3D ARM_FVP_BASE_BOARD_SYS_ID) { + // Set the DVI into the new mode + Status =3D ArmPlatformSysConfigSet (SYS_CFG_DVIMODE, mResolutions[Mo= deNumber].Mode); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + } + } + + // Set the multiplexer + Status =3D ArmPlatformSysConfigSet (SYS_CFG_MUXFPGA, LcdSite); + if (EFI_ERROR(Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + return Status; +} + +EFI_STATUS +LcdPlatformQueryMode ( + IN UINT32 ModeNumber, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + Info->Version =3D 0; + Info->HorizontalResolution =3D mResolutions[ModeNumber].HorizontalResolu= tion; + Info->VerticalResolution =3D mResolutions[ModeNumber].VerticalResolution; + Info->PixelsPerScanLine =3D mResolutions[ModeNumber].HorizontalResolutio= n; + + switch (mResolutions[ModeNumber].Bpp) { + case LCD_BITS_PER_PIXEL_24: + Info->PixelFormat =3D PixelRedGreenBlueReserved8Bi= tPerColor; + Info->PixelInformation.RedMask =3D LCD_24BPP_RED_MASK; + Info->PixelInformation.GreenMask =3D LCD_24BPP_GREEN_MASK; + Info->PixelInformation.BlueMask =3D LCD_24BPP_BLUE_MASK; + Info->PixelInformation.ReservedMask =3D LCD_24BPP_RESERVED_MASK; + break; + + case LCD_BITS_PER_PIXEL_16_555: + case LCD_BITS_PER_PIXEL_16_565: + case LCD_BITS_PER_PIXEL_12_444: + case LCD_BITS_PER_PIXEL_8: + case LCD_BITS_PER_PIXEL_4: + case LCD_BITS_PER_PIXEL_2: + case LCD_BITS_PER_PIXEL_1: + default: + // These are not supported + ASSERT(FALSE); + break; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdPlatformGetTimings ( + IN UINT32 ModeNumber, + OUT UINT32* HRes, + OUT UINT32* HSync, + OUT UINT32* HBackPorch, + OUT UINT32* HFrontPorch, + OUT UINT32* VRes, + OUT UINT32* VSync, + OUT UINT32* VBackPorch, + OUT UINT32* VFrontPorch + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + *HRes =3D mResolutions[ModeNumber].HorizontalResolution; + *HSync =3D mResolutions[ModeNumber].HSync; + *HBackPorch =3D mResolutions[ModeNumber].HBackPorch; + *HFrontPorch =3D mResolutions[ModeNumber].HFrontPorch; + *VRes =3D mResolutions[ModeNumber].VerticalResolution; + *VSync =3D mResolutions[ModeNumber].VSync; + *VBackPorch =3D mResolutions[ModeNumber].VBackPorch; + *VFrontPorch =3D mResolutions[ModeNumber].VFrontPorch; + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdPlatformGetBpp ( + IN UINT32 ModeNumber, + OUT LCD_BPP * Bpp + ) +{ + if (ModeNumber >=3D LcdPlatformGetMaxMode ()) { + return EFI_INVALID_PARAMETER; + } + + *Bpp =3D mResolutions[ModeNumber].Bpp; + + return EFI_SUCCESS; +} diff --git a/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111L= cdArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpress= Lib/PL111LcdArmVExpressLib.inf new file mode 100644 index 000000000000..fd83d2412d4f --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVE= xpressLib.inf @@ -0,0 +1,44 @@ +#/** @file +# +# Component description file for ArmVeGraphicsDxe module +# +# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PL111LcdArmVExpressLib + FILE_GUID =3D b7f06f20-496f-11e0-a8e8-0002a5d5c51b + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D LcdPlatformLib + +[Sources.common] + PL111LcdArmVExpress.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + ArmPlatformSysConfigLib + BaseLib + DxeServicesTableLib + +[Protocols] + gEfiEdidDiscoveredProtocolGuid # Produced + gEfiEdidActiveProtocolGuid # Produced + +[Pcd] + gArmVExpressTokenSpaceGuid.PcdPL111LcdMaxMode + gArmVExpressTokenSpaceGuid.PcdPL111LcdVideoModeOscId diff --git a/Platform/ARM/VExpressPkg/Library/ResetSystemLib/ResetSystemLib= .c b/Platform/ARM/VExpressPkg/Library/ResetSystemLib/ResetSystemLib.c new file mode 100644 index 000000000000..d2bc4a88fa5a --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ResetSystemLib/ResetSystemLib.c @@ -0,0 +1,111 @@ +/** @file + Template library implementation to support ResetSystem Runtime call. + + Fill in the templates with what ever makes you system reset. + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2013, ARM Ltd. All rights reserved.
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include + +#include +#include +#include + +#include + +/** + This function causes a system-wide reset (cold reset), in which + all circuitry within the system returns to its initial state. This type = of + reset is asynchronous to system operation and operates without regard to + cycle boundaries. + + If this function returns, it means that the system does not support cold + reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + ArmPlatformSysConfigSet (SYS_CFG_REBOOT, 0); +} + +/** + This function causes a system-wide initialization (warm reset), in which= all + processors are set to their initial state. Pending cycles are not corrup= ted. + + If this function returns, it means that the system does not support warm + reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + ResetCold (); +} + +/** + This function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + If this function returns, it means that the system does not support shut= down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + ArmPlatformSysConfigSet (SYS_CFG_SHUTDOWN, 0); +} + +/** + This function causes the system to enter S3 and then wake up immediately. + + If this function returns, it means that the system does not support S3 + feature. +**/ +VOID +EFIAPI +EnterS3WithImmediateWake ( + VOID + ) +{ + // not implemented +} + +/** + This function causes a systemwide reset. The exact type of the reset is + defined by the EFI_GUID that follows the Null-terminated Unicode string = passed + into ResetData. If the platform does not recognize the EFI_GUID in Reset= Data + the platform must pick a supported reset type to perform.The platform may + optionally log the parameters from any non-normal reset that occurs. + + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData The data buffer starts with a Null-terminated str= ing, + followed by the EFI_GUID. +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData + ) +{ + ResetCold (); +} diff --git a/Platform/ARM/VExpressPkg/Library/ResetSystemLib/ResetSystemLib= .inf b/Platform/ARM/VExpressPkg/Library/ResetSystemLib/ResetSystemLib.inf new file mode 100644 index 000000000000..e7caf04f7f74 --- /dev/null +++ b/Platform/ARM/VExpressPkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,36 @@ +#/** @file +# Reset System lib to make it easy to port new platforms +# +# Copyright (c) 2008, Apple Inc. All rights reserved.
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D ArmVeResetSystemLib + FILE_GUID =3D 36885202-0854-4373-bfd2-95d229b44d44 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ResetSystemLib + +[Sources.common] + ResetSystemLib.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec + +[LibraryClasses] + DebugLib + ArmPlatformSysConfigLib --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel