From nobody Tue Jan 14 22:26:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513075120968338.0723511626172; Tue, 12 Dec 2017 02:38:40 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 42FCD220EE11F; Tue, 12 Dec 2017 02:33:58 -0800 (PST) Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BE227220EE115 for ; Tue, 12 Dec 2017 02:33:56 -0800 (PST) Received: by mail-wr0-x241.google.com with SMTP id l22so20578441wrc.11 for ; Tue, 12 Dec 2017 02:38:35 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:32 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vR7g5PrIl3rdXaOpQHxuIsdsB8ooiiqX+hzRXtSMeDI=; b=kXO/r7ma9aPEsVzUrwYbPm26O2bSwOtyULM1Qw5mLPwIzV72WXVqvmziC5TPjZ8RMI UPVypxyTg8ANr5QAPjrttdk6GZjLE7he6nlNvIn7DfhcmWaG3kKJ4Oqtrz98uD5HHqr8 SWQENbWVYDLP21hhFa2sWsBQnxnbMrmD7f2h4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vR7g5PrIl3rdXaOpQHxuIsdsB8ooiiqX+hzRXtSMeDI=; b=ObCnQtQ5znPe1Q1PyEGd3WWZDELl/z/A4gdm5zoDA7XQwq118Plg1pen2GZhSM1iJX yiOrwK7+H/vwvbrCrx/4rqXe/iEZ2w3FblhUG+JNst9BSkJJyOWYYNcfgCC0ANF5n/+w gmSu8FejzGHQH9EiyBMsQ+NgrRtYt3SbgOqcQp3ASUkNYNePIG+16RZAE/r9gF7JJ+Bc NuDHZxTtN3hTTuEfgRqQDyQ0QkI1E+Acu2IytuBTGJJtVZ14gggRno4mX4M2NNRRG61e XdUM8TZhJ9y1F/frgBbq/bH8wdhocBjJ0UFuYE9KzM8csgQdTGN/GZHb01p7IXSt6icP Y1fQ== X-Gm-Message-State: AKGB3mJV5BfSlAfTJIps6peTyydLGabbnhQ3zveYPY2BtTYO3608AJuv QIwCBYw2SMJErVPbsO3XnZXyv1IOCG8= X-Google-Smtp-Source: ACJfBouZGGTqPGPXs0s7dQ+LbCYRCC8ghGpE5+QjDQCFcjWVVqc9mdCYjpxltvSuIVaomJ5dIImqQw== X-Received: by 10.223.134.216 with SMTP id 24mr3511658wry.156.1513075113571; Tue, 12 Dec 2017 02:38:33 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:07 +0000 Message-Id: <20171212103807.18836-9-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 8/8] Silicon/SynQuacer/PlatformDxe: retrain PCIe switch links to Gen2 speed X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" For some reason, the Asmedia 118x PCIe switch needs a little help to make sure that the downstream links train at Gen2 speed. So add a PCI I/O protocol notifier that implements this for each PCIe downstream port that is present on the system. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c | 140 ++++= ++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 13 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++++= ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 3 + 4 files changed, 184 insertions(+), 9 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c b/Silic= on/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c new file mode 100644 index 000000000000..b069b42d0a42 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pcie.c @@ -0,0 +1,140 @@ + /** @file + SynQuacer DXE platform driver - PCIe support + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include "PlatformDxe.h" + +#define ASMEDIA_VID 0x1b21 +#define ASM1182E_PID 0x1182 +#define ASM1184E_PID 0x1184 + +#define ASM118x_PCIE_CAPABILITY_OFFSET 0x80 +#define ASM118x_PCIE_LINK_CONTROL_OFFSET (ASM118x_PCIE_CAPABILITY_OFFSE= T + \ + OFFSET_OF (PCI_CAPABILITY_PCI= EXP, \ + LinkControl)) + +STATIC VOID *mPciProtocolNotifyRegistration; +STATIC EFI_EVENT mPciProtocolNotifyEvent; + +#pragma pack(1) +typedef struct { + EFI_PCI_CAPABILITY_HDR CapHdr; + PCI_REG_PCIE_CAPABILITY Pcie; +} PCIE_CAP; +#pragma pack() + +STATIC +VOID +RetrainAsm1184eDownstreamPort ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + UINT16 PciVidPid[2]; + EFI_STATUS Status; + PCIE_CAP Cap; + PCI_REG_PCIE_LINK_CONTROL LinkControl; + + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OF= FSET, + ARRAY_SIZE (PciVidPid), &PciVidPid); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n", + __FUNCTION__, Status)); + return; + } + + if (PciVidPid[0] !=3D ASMEDIA_VID || + (PciVidPid[1] !=3D ASM1182E_PID && PciVidPid[1] !=3D ASM1184E_PID)) { + return; + } + + // + // The upstream and downstream ports share the same PID/VID, so check + // the port type. This assumes the PCIe Express capability block lives + // at offset 0x80 in the port's config space, which is known to be the + // case for these particular chips. + // + ASSERT (sizeof (Cap) =3D=3D sizeof (UINT32)); + ASSERT (sizeof (LinkControl) =3D=3D sizeof (UINT16)); + + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, + ASM118x_PCIE_CAPABILITY_OFFSET, 1, &Cap); + ASSERT_EFI_ERROR (Status); + ASSERT (Cap.CapHdr.CapabilityID =3D=3D EFI_PCI_CAPABILITY_ID_PCIEXP); + + if (Cap.Pcie.Bits.DevicePortType !=3D PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_P= ORT) { + return; + } + + DEBUG ((DEBUG_INFO, "%a: retraining ASM1184x downstream PCIe port\n", + __FUNCTION__)); + + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, + ASM118x_PCIE_LINK_CONTROL_OFFSET, 1, &LinkControl); + ASSERT_EFI_ERROR (Status); + + LinkControl.Bits.RetrainLink =3D 1; + + Status =3D PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, + ASM118x_PCIE_LINK_CONTROL_OFFSET, 1, &LinkControl); + ASSERT_EFI_ERROR (Status); +} + +STATIC +VOID +EFIAPI +OnPciIoProtocolNotify ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_PCI_IO_PROTOCOL *PciIo; + EFI_STATUS Status; + EFI_HANDLE HandleBuffer; + UINTN BufferSize; + + while (TRUE) { + BufferSize =3D sizeof (EFI_HANDLE); + Status =3D gBS->LocateHandle (ByRegisterNotify, NULL, + mPciProtocolNotifyRegistration, &BufferSize, &HandleBu= ffer); + if (EFI_ERROR (Status)) { + break; + } + + Status =3D gBS->HandleProtocol (HandleBuffer, &gEfiPciIoProtocolGuid, + (VOID **)&PciIo); + ASSERT_EFI_ERROR (Status); + + // + // The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its + // 2-port sibling of which samples were used in development) needs a + // little nudge to get it to train the downstream links at Gen2 speed. + // + RetrainAsm1184eDownstreamPort (PciIo); + } +} + +EFI_STATUS +EFIAPI +RegisterPcieNotifier ( + VOID + ) +{ + mPciProtocolNotifyEvent =3D EfiCreateProtocolNotifyEvent ( + &gEfiPciIoProtocolGuid, + TPL_CALLBACK, + OnPciIoProtocolNotify, + NULL, + &mPciProtocolNotifyRegistration); + + return EFI_SUCCESS; +} diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index e58a2093eb49..098a4dbd324e 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -12,15 +12,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. **/ =20 -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include "PlatformDxe.h" =20 STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mNetsecDesc[] =3D { { @@ -202,5 +194,8 @@ PlatformDxeEntryPoint ( =20 SmmuEnableCoherentDma (); =20 + Status =3D RegisterPcieNotifier (); + ASSERT_EFI_ERROR (Status); + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h new file mode 100644 index 000000000000..d1dad2a3eace --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h @@ -0,0 +1,37 @@ +/** @file + SynQuacer DXE platform driver. + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#ifndef __PLATFORM_DXE_H__ +#define __PLATFORM_DXE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +RegisterPcieNotifier ( + VOID + ); + +#endif diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 00c1130906c4..84498eaddcef 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -23,6 +23,7 @@ [Defines] ENTRY_POINT =3D PlatformDxeEntryPoint =20 [Sources] + Pcie.c PlatformDxe.c =20 [Packages] @@ -41,6 +42,7 @@ [LibraryClasses] MemoryAllocationLib UefiBootServicesTableLib UefiDriverEntryPoint + UefiLib =20 [Guids] gFdtTableGuid @@ -50,6 +52,7 @@ [Guids] =20 [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES + gEfiPciIoProtocolGuid ## CONSUMES gPcf8563RealTimeClockLibI2cMasterProtolGuid ## PRODUCES =20 [FixedPcd] --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel