From nobody Sun May 11 01:33:32 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1514164035947314.35353802558814; Sun, 24 Dec 2017 17:07:15 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D048D21CB87AE; Sun, 24 Dec 2017 17:02:15 -0800 (PST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2707D21CB87A8 for ; Sun, 24 Dec 2017 17:02:14 -0800 (PST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Dec 2017 17:07:06 -0800 Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.192.64]) by fmsmga006.fm.intel.com with ESMTP; 24 Dec 2017 17:07:05 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,452,1508828400"; d="scan'208";a="189773036" From: Jian J Wang To: edk2-devel@lists.01.org Date: Mon, 25 Dec 2017 09:06:59 +0800 Message-Id: <20171225010659.13428-5-jian.j.wang@intel.com> X-Mailer: git-send-email 2.15.1.windows.2 In-Reply-To: <20171225010659.13428-1-jian.j.wang@intel.com> References: <20171225010659.13428-1-jian.j.wang@intel.com> Subject: [edk2] [PATCH 4/4] UefiCpuPkg: Update code to use new structure field names X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dandan Bi , Laszlo Ersek , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Due to coding style fix of the structure definition in BaseLib.h, all code referencing those structure must be updated accordingly. Cc: Dandan Bi Cc: Eric Dong Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang Reviewed-by: Dandan Bi --- .../Ia32/ArchExceptionHandler.c | 24 +++++++++++-------= ---- .../X64/ArchExceptionHandler.c | 6 +++--- UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 +- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHa= ndler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandl= er.c index 6ac8549839..4e89b0470f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -216,7 +216,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow =3D (UINT16)TssBase; TssDesc->Bits.BaseMid =3D (UINT8)(TssBase >> 16); TssDesc->Bits.Type =3D IA32_GDT_TYPE_TSS; - TssDesc->Bits.P =3D 1; + TssDesc->Bits.Present =3D 1; TssDesc->Bits.LimitHigh =3D 0; TssDesc->Bits.BaseHigh =3D (UINT8)(TssBase >> 24); =20 @@ -240,7 +240,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow =3D (UINT16)TssBase; TssDesc->Bits.BaseMid =3D (UINT8)(TssBase >> 16); TssDesc->Bits.Type =3D IA32_GDT_TYPE_TSS; - TssDesc->Bits.P =3D 1; + TssDesc->Bits.Present =3D 1; TssDesc->Bits.LimitHigh =3D 0; TssDesc->Bits.BaseHigh =3D (UINT8)(TssBase >> 24); =20 @@ -253,17 +253,17 @@ ArchSetupExcpetionStack ( continue; } =20 - Tss->EIP =3D (UINT32)(TemplateMap.ExceptionStart + Tss->Eip =3D (UINT32)(TemplateMap.ExceptionStart + Vector * TemplateMap.ExceptionStubHeaderSize); - Tss->EFLAGS =3D 0x2; - Tss->ESP =3D StackTop; - Tss->CR3 =3D AsmReadCr3 (); - Tss->ES =3D AsmReadEs (); - Tss->CS =3D AsmReadCs (); - Tss->SS =3D AsmReadSs (); - Tss->DS =3D AsmReadDs (); - Tss->FS =3D AsmReadFs (); - Tss->GS =3D AsmReadGs (); + Tss->Eflags =3D 0x2; + Tss->Esp =3D StackTop; + Tss->Cr3 =3D AsmReadCr3 (); + Tss->Es =3D AsmReadEs (); + Tss->Cs =3D AsmReadCs (); + Tss->Ss =3D AsmReadSs (); + Tss->Ds =3D AsmReadDs (); + Tss->Fs =3D AsmReadFs (); + Tss->Gs =3D AsmReadGs (); =20 StackTop -=3D StackSwitchData->Ia32.KnownGoodStackSize; =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHan= dler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler= .c index 1dcf4277de..4d52b4eb0e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -186,7 +186,7 @@ ArchSetupExcpetionStack ( // TssDesc =3D StackSwitchData->X64.ExceptionTssDesc; Tss =3D StackSwitchData->X64.ExceptionTss; - if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->I= ST)) { + if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->I= st)) { return EFI_INVALID_PARAMETER; } =20 @@ -221,7 +221,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow =3D (UINT16)TssBase; TssDesc->Bits.BaseMidl =3D (UINT8)(TssBase >> 16); TssDesc->Bits.Type =3D IA32_GDT_TYPE_TSS; - TssDesc->Bits.P =3D 1; + TssDesc->Bits.Present =3D 1; TssDesc->Bits.LimitHigh =3D 0; TssDesc->Bits.BaseMidh =3D (UINT8)(TssBase >> 24); TssDesc->Bits.BaseHigh =3D (UINT32)(TssBase >> 32); @@ -236,7 +236,7 @@ ArchSetupExcpetionStack ( // // Fixup IST // - Tss->IST[Index] =3D StackTop; + Tss->Ist[Index] =3D StackTop; StackTop -=3D StackSwitchData->X64.KnownGoodStackSize; =20 // diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 0c2058a7b0..da1a43c430 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -243,7 +243,7 @@ RestoreVolatileRegisters ( VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) { Tss =3D (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base + VolatileRegisters->Tr); - if (Tss->Bits.P =3D=3D 1) { + if (Tss->Bits.Present =3D=3D 1) { Tss->Bits.Type &=3D 0xD; // 1101 - Clear busy bit just in case AsmWriteTr (VolatileRegisters->Tr); } --=20 2.15.1.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel