Align the UART DT nodes:
- use 'uart' not 'fuart' as node name for the second serial port
- create an alias 'serial1' for the second serial port
- use UART clock reference instead of hardcoded frequency
- split 'clocks' property into 1 cell per phandle

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
index 37a3981f0360..7c3518facb98 100644
--- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
+++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
@@ -32,6 +32,7 @@
 
     aliases {
         serial0 = &soc_uart0;
+        serial1 = &fuart;
     };
 
     chosen {
@@ -436,15 +437,16 @@
         compatible = "arm,pl011", "arm,primecell";
         reg = <0x0 0x2a400000 0x0 0x1000>;
         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-        clocks = <&clk_uart &clk_apb>;
+        clocks = <&clk_uart>, <&clk_apb>;
         clock-names = "uartclk", "apb_pclk";
     };
 
-    fuart: fuart@51040000 {
+    fuart: uart@51040000 {
         compatible = "snps,dw-apb-uart";
         reg = <0x0 0x51040000 0x0 0x1000>;
         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
-        clock-frequency = <62500000>;
+        clocks = <&clk_uart>, <&clk_apb>;
+        clock-names = "baudclk", "apb_pclk";
         reg-io-width = <4>;
         reg-shift = <2>;
     };
-- 
2.11.0

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