From nobody Mon Dec 23 13:49:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1515598000227864.954744274963; Wed, 10 Jan 2018 07:26:40 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4192A222CF1DA; Wed, 10 Jan 2018 07:21:25 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 16F48222CF1C8 for ; Wed, 10 Jan 2018 07:21:23 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jan 2018 07:26:35 -0800 Received: from lgao4-mobl1.ccr.corp.intel.com ([10.254.210.57]) by fmsmga002.fm.intel.com with ESMTP; 10 Jan 2018 07:26:34 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,340,1511856000"; d="scan'208";a="9032532" From: Liming Gao To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 23:24:26 +0800 Message-Id: <20180110152432.15964-2-liming.gao@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 In-Reply-To: <20180110152432.15964-1-liming.gao@intel.com> References: <20180110152432.15964-1-liming.gao@intel.com> Subject: [edk2] [Patch 1/7] BaseTools: Disable -Wno-unused-const-variable in XCODE5 RELEASE target X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Fish MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao Cc: Yonghong Zhu Cc: Andrew Fish Reviewed-by: Yonghong Zhu =20 --- BaseTools/Conf/tools_def.template | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index 12278302b3..a961048288 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -1,5 +1,5 @@ # -# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
# Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
# Copyright (c) 2015, Hewlett-Packard Development Company, L.P.
@@ -7551,7 +7551,7 @@ RELEASE_XCODE5_IA32_ASM_FLAGS =3D -arch i386 =20 =20 DEBUG_XCODE5_IA32_CC_FLAGS =3D -arch i386 -c -g -Os -Wall -Werro= r -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fsh= ort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields = -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-i= nitializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap= -function=3Dundefined_behavior_has_been_optimized_away_by_clang $(PLATFORM_= FLAGS) -RELEASE_XCODE5_IA32_CC_FLAGS =3D -arch i386 -c -Os -Wall -Werro= r -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fsh= ort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields = -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-i= nitializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap= -function=3Dundefined_behavior_has_been_optimized_away_by_clang $(PLATFORM_= FLAGS) +RELEASE_XCODE5_IA32_CC_FLAGS =3D -arch i386 -c -Os -Wall -Werro= r -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fsh= ort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields = -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-i= nitializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -Wno-u= nused-const-variable -ftrap-function=3Dundefined_behavior_has_been_optimize= d_away_by_clang $(PLATFORM_FLAGS) NOOPT_XCODE5_IA32_CC_FLAGS =3D -arch i386 -c -g -O0 -Wall -Werro= r -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fsh= ort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields = -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-i= nitializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap= -function=3Dundefined_behavior_has_been_optimized_away_by_clang $(PLATFORM_= FLAGS) =20 ################## @@ -7571,7 +7571,7 @@ RELEASE_XCODE5_X64_ASM_FLAGS =3D -arch x86_64 =20 DEBUG_XCODE5_X64_CC_FLAGS =3D -target x86_64-pc-win32-macho -c -g -Os = -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-exte= nsions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float = -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field= -initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftr= ap-function=3Dundefined_behavior_has_been_optimized_away_by_clang -D NO_MSA= BI_VA_FUNCS $(PLATFORM_FLAGS) NOOPT_XCODE5_X64_CC_FLAGS =3D -target x86_64-pc-win32-macho -c -g -O0 = -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-exte= nsions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float = -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field= -initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftr= ap-function=3Dundefined_behavior_has_been_optimized_away_by_clang -D NO_MSA= BI_VA_FUNCS $(PLATFORM_FLAGS) -RELEASE_XCODE5_X64_CC_FLAGS =3D -target x86_64-pc-win32-macho -c -Os = -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-exte= nsions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float = -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field= -initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftr= ap-function=3Dundefined_behavior_has_been_optimized_away_by_clang -D NO_MSA= BI_VA_FUNCS $(PLATFORM_FLAGS) +RELEASE_XCODE5_X64_CC_FLAGS =3D -target x86_64-pc-win32-macho -c -Os = -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-exte= nsions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float = -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field= -initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -Wno= -unused-const-variable -ftrap-function=3Dundefined_behavior_has_been_optimi= zed_away_by_clang -D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS) =20 ##########################################################################= ########## # --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Dec 23 13:49:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1515598003052944.2294988070903; Wed, 10 Jan 2018 07:26:43 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A5DA6222CF1DD; Wed, 10 Jan 2018 07:21:25 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 21AD2222CF1D2 for ; Wed, 10 Jan 2018 07:21:24 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jan 2018 07:26:36 -0800 Received: from lgao4-mobl1.ccr.corp.intel.com ([10.254.210.57]) by fmsmga002.fm.intel.com with ESMTP; 10 Jan 2018 07:26:35 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,340,1511856000"; d="scan'208";a="9032537" From: Liming Gao To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 23:24:27 +0800 Message-Id: <20180110152432.15964-3-liming.gao@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 In-Reply-To: <20180110152432.15964-1-liming.gao@intel.com> References: <20180110152432.15964-1-liming.gao@intel.com> Subject: [edk2] [Patch 2/7] BaseTools: Use nasm as the preferred assembly source files for XCODE5 tool X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Fish MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao Cc: Andrew Fish Cc: Yonghong Zhu Reviewed-by: Yonghong Zhu =20 --- BaseTools/Conf/tools_def.template | 1 - 1 file changed, 1 deletion(-) diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t= emplate index a961048288..d8fde02ea3 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -7500,7 +7500,6 @@ NOOPT_MYTOOLS_IPF_DLINK_FLAGS =3D /NOLOGO = /NODEFAULTLIB /LTCG /DLL /OPT =20 *_XCODE5_*_*_FAMILY =3D GCC *_XCODE5_*_*_BUILDRULEFAMILY =3D XCODE -*_XCODE5_*_*_BUILDRULEORDER =3D S s nasm =20 # # use xcode-select to change Xcode version of command line tools --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Dec 23 13:49:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1515598005720411.41692112117755; Wed, 10 Jan 2018 07:26:45 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0D4DD222CF1D2; Wed, 10 Jan 2018 07:21:29 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 21FA4222CF1D8 for ; Wed, 10 Jan 2018 07:21:25 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jan 2018 07:26:37 -0800 Received: from lgao4-mobl1.ccr.corp.intel.com ([10.254.210.57]) by fmsmga002.fm.intel.com with ESMTP; 10 Jan 2018 07:26:36 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,340,1511856000"; d="scan'208";a="9032543" From: Liming Gao To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 23:24:28 +0800 Message-Id: <20180110152432.15964-4-liming.gao@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 In-Reply-To: <20180110152432.15964-1-liming.gao@intel.com> References: <20180110152432.15964-1-liming.gao@intel.com> Subject: [edk2] [Patch 3/7] MdeModulePkg: Update DebugSupportDxe to pass XCODE5 build X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Fish , Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" XCODE5 doesn't support absolute addressing in the assembly code. This change uses lea instruction to get the address. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao Cc: Andrew Fish Cc: Star Zeng Reviewed-by: Star Zeng --- MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm b/Mde= ModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm index 134842a68a..31d8b0a717 100644 --- a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm +++ b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm @@ -1,7 +1,7 @@ ;/** @file ; Low level x64 routines used by the debug support driver. ; -; Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the B= SD License ; which accompanies this distribution. The full text of the license may = be found at @@ -226,7 +226,7 @@ ASM_PFX(CommonIdtEntry): pop rax add rsp, 8 ; pop vector numb= er mov [AppRsp], rsp ; save stack top - mov rsp, DebugStackBegin ; switch to debug= ger stack + lea rsp, [DebugStackBegin] ; switch to debug= ger stack sub rsp, 8 ; leave space for= vector number =20 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax; @@ -529,7 +529,7 @@ Chain: push rbx mov rax, cs push rax - mov rax, PhonyIretq + lea rax, [PhonyIretq] push rax iretq PhonyIretq: --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Dec 23 13:49:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151559801581740.88811176640536; Wed, 10 Jan 2018 07:26:55 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 70E3E222CF1C8; Wed, 10 Jan 2018 07:21:42 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3F22F222CF1B6 for ; Wed, 10 Jan 2018 07:21:41 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jan 2018 07:26:38 -0800 Received: from lgao4-mobl1.ccr.corp.intel.com ([10.254.210.57]) by fmsmga002.fm.intel.com with ESMTP; 10 Jan 2018 07:26:37 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,340,1511856000"; d="scan'208";a="9032554" From: Liming Gao To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 23:24:29 +0800 Message-Id: <20180110152432.15964-5-liming.gao@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 In-Reply-To: <20180110152432.15964-1-liming.gao@intel.com> References: <20180110152432.15964-1-liming.gao@intel.com> Subject: [edk2] [Patch 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Laszlo Ersek , Jiewen Yao , Andrew Fish , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Use the dummy address as jmp destination, and add the logic to fix up the address to the absolute address at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao Cc: Andrew Fish Cc: Jiewen Yao Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael Kinney --- .../X64/ExceptionHandlerAsm.nasm | 29 ++++++++++++++++--= ---- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandler= Asm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAs= m.nasm index ba8993d84b..a5fde0a875 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.
+; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -40,7 +40,8 @@ AsmIdtVectorBegin: db 0x6a ; push #VectorNum db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegi= n) / 32) ; VectorNum push rax - mov rax, ASM_PFX(CommonInterruptEntry) + db 0x48, 0xB8 + dq 0 ; mov rax, ASM_PFX(CommonInterruptEntry) jmp rax %endrep AsmIdtVectorEnd: @@ -50,7 +51,9 @@ HookAfterStubHeaderBegin: @VectorNum: db 0 ; 0 will be fixed push rax - mov rax, HookAfterStubHeaderEnd + db 0x48, 0xB8 +JmpAbsoluteAddress: + dq 0 ; mov rax, HookAfterStubHeaderEnd jmp rax HookAfterStubHeaderEnd: mov rax, rsp @@ -260,8 +263,7 @@ HasErrorCode: ; and make sure RSP is 16-byte aligned ; sub rsp, 4 * 8 + 8 - mov rax, ASM_PFX(CommonExceptionHandler) - call rax + call ASM_PFX(CommonExceptionHandler) add rsp, 4 * 8 + 8 =20 cli @@ -369,11 +371,24 @@ DoIret: ; comments here for definition of address map global ASM_PFX(AsmGetTemplateAddressMap) ASM_PFX(AsmGetTemplateAddressMap): - mov rax, AsmIdtVectorBegin + lea rax, [AsmIdtVectorBegin] mov qword [rcx], rax mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32 - mov rax, HookAfterStubHeaderBegin + lea rax, [HookAfterStubHeaderBegin] mov qword [rcx + 0x10], rax + +; Fix up CommonInterruptEntry address + lea rax, [ASM_PFX(CommonInterruptEntry)] + lea rcx, [AsmIdtVectorBegin] +%rep 32 + mov qword [rcx + (JmpAbsoluteAddress - HookAfterStubHeaderBegin)], = rax + add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32 +%endrep +; Fix up HookAfterStubHeaderEnd + lea rax, [HookAfterStubHeaderEnd] + lea rcx, [JmpAbsoluteAddress] + mov qword [rcx], rax + ret =20 ;-------------------------------------------------------------------------= ------------ --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Dec 23 13:49:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151559801821074.63937891257581; Wed, 10 Jan 2018 07:26:58 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CA4A521F833D0; Wed, 10 Jan 2018 07:21:44 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 64B8D222CF1B6 for ; Wed, 10 Jan 2018 07:21:43 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jan 2018 07:26:40 -0800 Received: from lgao4-mobl1.ccr.corp.intel.com ([10.254.210.57]) by fmsmga002.fm.intel.com with ESMTP; 10 Jan 2018 07:26:38 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,340,1511856000"; d="scan'208";a="9032559" From: Liming Gao To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 23:24:30 +0800 Message-Id: <20180110152432.15964-6-liming.gao@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 In-Reply-To: <20180110152432.15964-1-liming.gao@intel.com> References: <20180110152432.15964-1-liming.gao@intel.com> Subject: [edk2] [Patch 5/7] UefiCpuPkg: Update SmmCpuFeatureLib pass XCODE5 tool chain X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Laszlo Ersek , Jiewen Yao , Andrew Fish , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" 1. Use lea instruction to get the address instead of mov instruction. 2. Use the dummy address as jmp destination, and add the logic to fix up the address to the absolute address at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao Cc: Andrew Fish Cc: Jiewen Yao Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael Kinney --- .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 6 +++- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 8 +++-- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h | 11 +++++- .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 42 +++++++++++++++---= ---- .../SmmCpuFeaturesLib/X64/SmiException.nasm | 10 +++--- 5 files changed, 55 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm b/Uefi= CpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm index 00c0f0672c..057ec6d105 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -273,3 +273,7 @@ _StmSmiHandler: =20 ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPo= int + +global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress) +ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress): + ret diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.c index 45015b8da4..8dc2d70527 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -1,7 +1,7 @@ /** @file SMM STM support functions =20 - Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -116,7 +116,6 @@ UINTN mMsegSize =3D 0; =20 BOOLEAN mStmConfigurationTableInitialized =3D FALSE; =20 - /** The constructor function =20 @@ -139,6 +138,11 @@ SmmCpuFeaturesLibStmConstructor ( EFI_SMRAM_DESCRIPTOR *SmramDescriptor; =20 // + // Initialize address fixup + // + SmmCpuFeaturesLibStmSmiEntryFixupAddress (); + + // // Call the common constructor function // Status =3D SmmCpuFeaturesLibConstructor (ImageHandle, SystemTable); diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.h index 92a4dc00eb..c98b660ecb 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h @@ -1,7 +1,7 @@ /** @file SMM STM support =20 - Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -173,4 +173,13 @@ GetStmResource ( VOID ); =20 +/** + This function fixes up the address of the global variable or function + referred in SmiEntry assembly files to be the absoute address. +**/ +VOID +EFIAPI +SmmCpuFeaturesLibStmSmiEntryFixupAddress ( + ); + #endif diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm b/UefiC= puPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm index ea2d2970bd..e9c1306265 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -164,7 +164,9 @@ Base: mov cr0, rbx retf @LongMode: ; long mode (64-bit code) starts h= ere - mov rax, ASM_PFX(gStmSmiHandlerIdtr) + db 0x48, 0xB8 +StmSmiEntrySmiHandlerIdtrAbsAddr: + dq 0 ; mov rax, ASM_PFX(gStmSmiHan= dlerIdtr) lidt [rax] lea ebx, [rdi + DSC_OFFSET] mov ax, [rbx + DSC_DS] @@ -175,7 +177,10 @@ Base: mov gs, eax mov ax, [rbx + DSC_SS] mov ss, eax - + db 0x48, 0xB8 +StmSmiEntryCommonHandlerAbsAddr: + dq 0 ; mov rax, CommonHandler + jmp rax CommonHandler: mov rbx, [rsp + 0x08] ; rbx <- CpuIndex =20 @@ -188,16 +193,13 @@ CommonHandler: add rsp, -0x20 =20 mov rcx, rbx - mov rax, ASM_PFX(CpuSmmDebugEntry) - call rax + call ASM_PFX(CpuSmmDebugEntry) =20 mov rcx, rbx - mov rax, ASM_PFX(SmiRendezvous) ; rax <- absolute addr of= SmiRedezvous - call rax + call ASM_PFX(SmiRendezvous) =20 mov rcx, rbx - mov rax, ASM_PFX(CpuSmmDebugExit) - call rax + call ASM_PFX(CpuSmmDebugExit) =20 add rsp, 0x20 =20 @@ -208,7 +210,7 @@ CommonHandler: =20 add rsp, 0x200 =20 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz .1 @@ -228,7 +230,7 @@ _StmSmiHandler: ; Check XD disable bit ; xor r8, r8 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz @StmXdDone @@ -249,8 +251,9 @@ _StmSmiHandler: =20 ; below step is needed, because STM does not run above code. ; we have to run below code to set IDT/CR0/CR4 - - mov rax, ASM_PFX(gStmSmiHandlerIdtr) + db 0x48, 0xB8 +StmSmiHandlerIdtrAbsAddr: + dq 0 ; mov rax, ASM_PFX(gStmSmiHan= dlerIdtr) lidt [rax] =20 mov rax, cr0 @@ -264,3 +267,16 @@ _StmSmiHandler: =20 ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint + +global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress) +ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress): + lea rax, [ASM_PFX(gStmSmiHandlerIdtr)] + lea rcx, [StmSmiEntrySmiHandlerIdtrAbsAddr] + mov qword [rcx], rax + lea rcx, [StmSmiHandlerIdtrAbsAddr] + mov qword [rcx], rax + + lea rax, [CommonHandler] + lea rcx, [StmSmiEntryCommonHandlerAbsAddr] + mov qword [rcx], rax + ret diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm b/U= efiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm index ce9d7c2bb6..b0ab87b0d4 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -95,7 +95,7 @@ ASM_PFX(OnStmSetup): ; Check XD disable bit ; xor r8, r8 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz @StmXdDone1 @@ -118,7 +118,7 @@ ASM_PFX(OnStmSetup): call ASM_PFX(SmmStmSetup) add rsp, 0x20 =20 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz .11 @@ -139,7 +139,7 @@ ASM_PFX(OnStmTeardown): ; Check XD disable bit ; xor r8, r8 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz @StmXdDone2 @@ -162,7 +162,7 @@ ASM_PFX(OnStmTeardown): call ASM_PFX(SmmStmTeardown) add rsp, 0x20 =20 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz .12 --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Dec 23 13:49:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151559802130990.20484655508687; Wed, 10 Jan 2018 07:27:01 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3C7832220D1E0; Wed, 10 Jan 2018 07:21:45 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9729E2035D334 for ; Wed, 10 Jan 2018 07:21:43 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jan 2018 07:26:42 -0800 Received: from lgao4-mobl1.ccr.corp.intel.com ([10.254.210.57]) by fmsmga002.fm.intel.com with ESMTP; 10 Jan 2018 07:26:40 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,340,1511856000"; d="scan'208";a="9032566" From: Liming Gao To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 23:24:31 +0800 Message-Id: <20180110152432.15964-7-liming.gao@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 In-Reply-To: <20180110152432.15964-1-liming.gao@intel.com> References: <20180110152432.15964-1-liming.gao@intel.com> Subject: [edk2] [Patch 6/7] UefiCpuPkg: Update PiSmmCpuDxeSmm pass XCODE5 tool chain X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Laszlo Ersek , Jiewen Yao , Andrew Fish , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" 1. Use lea instruction to get the address instead of mov instruction. 2. Use the dummy address as jmp destination, and add the logic to fix up the address to the absolute address at boot time. 3. On MpFuncs.nasm, use ExchangeInfo to record InitializeFloatingPointUnits. This way is same to MpInitLib. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao Cc: Andrew Fish Cc: Jiewen Yao Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael Kinney --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 6 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 5 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 6 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 8 ++++++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 20 +++++++++++++++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm | 9 ++++--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 32 +++++++++++++++++----= ---- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm | 4 ++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm | 17 ++++++++++--- 9 files changed, 82 insertions(+), 25 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 94e5ab2c0e..554629536a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -1,7 +1,7 @@ /** @file Code for Processor S3 restoration =20 -Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -14,6 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. =20 #include "PiSmmCpuDxeSmm.h" =20 +#pragma pack(1) typedef struct { UINTN Lock; VOID *StackStart; @@ -23,7 +24,9 @@ typedef struct { IA32_DESCRIPTOR IdtrProfile; UINT32 BufferStart; UINT32 Cr3; + UINTN InitializeFloatingPointUnitsAddress; } MP_CPU_EXCHANGE_INFO; +#pragma pack() =20 typedef struct { UINT8 *RendezvousFunnelAddress; @@ -456,6 +459,7 @@ PrepareApStartupVector ( mExchangeInfo->StackSize =3D mAcpiCpuData.StackSize; mExchangeInfo->BufferStart =3D (UINT32) StartupVector; mExchangeInfo->Cr3 =3D (UINT32) (AsmReadCr3 ()); + mExchangeInfo->InitializeFloatingPointUnitsAddress =3D (UINTN)Initialize= FloatingPointUnits; } =20 /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index 4d2383ff97..a8324a7f4a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -207,3 +207,6 @@ ASM_PFX(SmiHandler): =20 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint =20 +global ASM_PFX(PiSmmCpuSmiEntryFixupAddress) +ASM_PFX(PiSmmCpuSmiEntryFixupAddress): + ret diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/Ia32/SmmInit.nasm index d9df3626c7..a5c62e77ce 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -85,3 +85,7 @@ ASM_PFX(SmmRelocationSemaphoreComplete): mov byte [eax], 1 pop eax jmp [ASM_PFX(mSmmRelocationOriginalAddress)] + +global ASM_PFX(PiSmmCpuSmmInitFixupAddress) +ASM_PFX(PiSmmCpuSmmInitFixupAddress): + ret diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 4b66a0dfd9..a27d1f4684 100755 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -1,7 +1,7 @@ /** @file Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 -Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials @@ -543,6 +543,12 @@ PiCpuSmmEntry ( UINT32 Cr3; =20 // + // Initialize address fixup + // + PiSmmCpuSmmInitFixupAddress (); + PiSmmCpuSmiEntryFixupAddress (); + + // // Initialize Debug Agent to support source level debug in SMM code // InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index ef32f17676..0323bfff92 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -1,7 +1,7 @@ /** @file Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 -Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials @@ -1166,4 +1166,22 @@ EdkiiSmmGetMemoryAttributes ( IN UINT64 *Attributes ); =20 +/** + This function fixes up the address of the global variable or function + referred in SmmInit assembly files to be the absoute address. +**/ +VOID +EFIAPI +PiSmmCpuSmmInitFixupAddress ( + ); + +/** + This function fixes up the address of the global variable or function + referred in SmiEntry assembly files to be the absoute address. +**/ +VOID +EFIAPI +PiSmmCpuSmiEntryFixupAddress ( + ); + #endif diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm b/UefiCpuPkg/PiSmmC= puDxeSmm/X64/MpFuncs.nasm index 702233d6e4..704942ec27 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -18,8 +18,6 @@ ; ;-------------------------------------------------------------------------= ------ =20 -extern ASM_PFX(InitializeFloatingPointUnits) - %define VacantFlag 0x0 %define NotVacantFlag 0xff =20 @@ -31,6 +29,7 @@ extern ASM_PFX(InitializeFloatingPointUnits) %define IdtrLocation LockLocation + 0x2A %define BufferStartLocation LockLocation + 0x34 %define Cr3OffsetLocation LockLocation + 0x38 +%define InitializeFloatingPointUnitsAddress LockLocation + 0x3C =20 ;-------------------------------------------------------------------------= ------------ ;RendezvousFunnelProc procedure follows. All APs execute their procedure.= This @@ -153,7 +152,7 @@ Releaselock: ; ; Call assembly function to initialize FPU. ; - mov rax, ASM_PFX(InitializeFloatingPointUnits) + mov rax, qword [esi + InitializeFloatingPointUnitsAddress] sub rsp, 0x20 call rax add rsp, 0x20 @@ -185,7 +184,7 @@ RendezvousFunnelProcEnd: ; comments here for definition of address map global ASM_PFX(AsmGetAddressMap) ASM_PFX(AsmGetAddressMap): - mov rax, RendezvousFunnelProcStart + lea rax, [RendezvousFunnelProcStart] mov qword [rcx], rax mov qword [rcx+0x8], PMODE_ENTRY - RendezvousFunnelProcSta= rt mov qword [rcx+0x10], FLAT32_JUMP - RendezvousFunnelProcSt= art diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index dc56dc7852..3944b3e68c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -158,7 +158,9 @@ Base: mov cr0, rbx retf @LongMode: ; long mode (64-bit code) starts h= ere - mov rax, ASM_PFX(gSmiHandlerIdtr) + db 0x48, 0xB8 +SmiHandlerIdtrAbsAddr: + dq 0 ; mov rax, ASM_PFX(gSmiHandle= rIdtr) lidt [rax] lea ebx, [rdi + DSC_OFFSET] mov ax, [rbx + DSC_DS] @@ -169,7 +171,10 @@ Base: mov gs, eax mov ax, [rbx + DSC_SS] mov ss, eax -; jmp _SmiHandler ; instruction is not needed + db 0x48, 0xB8 +_SmiHandlerAbsAddr: + dq 0 ; mov rax, _SmiHandler + jmp rax =20 _SmiHandler: mov rbx, [rsp + 0x8] ; rcx <- CpuIndex @@ -184,16 +189,13 @@ _SmiHandler: add rsp, -0x20 =20 mov rcx, rbx - mov rax, ASM_PFX(CpuSmmDebugEntry) - call rax + call ASM_PFX(CpuSmmDebugEntry) =20 mov rcx, rbx - mov rax, ASM_PFX(SmiRendezvous) ; rax <- absolute addr of SmiRede= zvous - call rax + call ASM_PFX(SmiRendezvous) =20 mov rcx, rbx - mov rax, ASM_PFX(CpuSmmDebugExit) - call rax + call ASM_PFX(CpuSmmDebugExit) =20 add rsp, 0x20 =20 @@ -205,7 +207,7 @@ _SmiHandler: =20 add rsp, 0x200 =20 - mov rax, ASM_PFX(mXdSupported) + lea rax, [ASM_PFX(mXdSupported)] mov al, [rax] cmp al, 0 jz .1 @@ -222,3 +224,13 @@ _SmiHandler: =20 ASM_PFX(gcSmiHandlerSize) DW $ - _SmiEntryPoint =20 +global ASM_PFX(PiSmmCpuSmiEntryFixupAddress) +ASM_PFX(PiSmmCpuSmiEntryFixupAddress): + lea rax, [ASM_PFX(gSmiHandlerIdtr)] + lea rcx, [SmiHandlerIdtrAbsAddr] + mov qword [rcx], rax + + lea rax, [_SmiHandler] + lea rcx, [_SmiHandlerAbsAddr] + mov qword [rcx], rax + ret diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm b/UefiCpuPkg/P= iSmmCpuDxeSmm/X64/SmiException.nasm index b2e2e6dee6..a8a9af3008 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -289,7 +289,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile): =20 ;; call into exception handler mov rcx, [rbp + 8] - mov rax, ASM_PFX(SmiPFHandler) + lea rax, [ASM_PFX(SmiPFHandler)] =20 ;; Prepare parameter and call mov rdx, rsp diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmC= puDxeSmm/X64/SmmInit.nasm index 9d05e2cb05..2701689c3d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -60,7 +60,7 @@ ASM_PFX(gSmmCr4): DD 0 ASM_PFX(gSmmCr0): DD 0 mov cr0, rax ; enable protected mode & paging DB 0x66, 0xea ; far jmp to long mode -ASM_PFX(gSmmJmpAddr): DQ @LongMode +ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode @LongMode: ; long-mode starts here DB 0x48, 0xbc ; mov rsp, imm64 ASM_PFX(gSmmInitStack): DQ 0 @@ -99,7 +99,7 @@ ASM_PFX(gcSmmInitTemplate): sub ebp, 0x30000 jmp ebp @L1: - DQ ASM_PFX(SmmStartup) + DQ 0; ASM_PFX(SmmStartup) =20 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate) =20 @@ -128,3 +128,14 @@ ASM_PFX(mRebasedFlagAddr32): dd 0 ; db 0xff, 0x25 ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0 + +global ASM_PFX(PiSmmCpuSmmInitFixupAddress) +ASM_PFX(PiSmmCpuSmmInitFixupAddress): + lea rax, [@LongMode] + lea rcx, [ASM_PFX(gSmmJmpAddr)] + mov qword [rcx], rax + + lea rax, [ASM_PFX(SmmStartup)] + lea rcx, [@L1] + mov qword [rcx], rax + ret --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Dec 23 13:49:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1515598026742840.3276971881462; Wed, 10 Jan 2018 07:27:06 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C069321F833BB; Wed, 10 Jan 2018 07:21:47 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B477A21F833B3 for ; Wed, 10 Jan 2018 07:21:43 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jan 2018 07:26:43 -0800 Received: from lgao4-mobl1.ccr.corp.intel.com ([10.254.210.57]) by fmsmga002.fm.intel.com with ESMTP; 10 Jan 2018 07:26:42 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,340,1511856000"; d="scan'208";a="9032568" From: Liming Gao To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 23:24:32 +0800 Message-Id: <20180110152432.15964-8-liming.gao@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 In-Reply-To: <20180110152432.15964-1-liming.gao@intel.com> References: <20180110152432.15964-1-liming.gao@intel.com> MIME-Version: 1.0 Subject: [edk2] [Patch 7/7] OvmfPkg: Don't add -mno-mmx -mno-sse option for XCODE5 tool chain X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laszlo Ersek , Andrew Fish Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Ovmf appended option -mno-mmx -mno-sse, but these two options were enabled in Openssl. The compiler option becomes -mmmx =E2=80=93msse -mno-mmx -mno-s= se. It trig mac clang compiler hang when compile one source file in openssl. This issue is found when SECURE_BOOT_ENABLE is TRUE. This may be the compil= er issue. To work around it, don't add these two options for XCODE5 tool chain. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao Cc: Andrew Fish Cc: Laszlo Ersek Reviewed-by: Laszlo Ersek --- OvmfPkg/OvmfPkgIa32.dsc | 4 +++- OvmfPkg/OvmfPkgIa32X64.dsc | 4 +++- OvmfPkg/OvmfPkgX64.dsc | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 9d23f8c162..d762955c5d 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# # This program and the accompanying materials @@ -64,7 +64,9 @@ GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG INTEL:RELEASE_*_*_CC_FLAGS =3D /D MDEPKG_NDEBUG MSFT:RELEASE_*_*_CC_FLAGS =3D /D MDEPKG_NDEBUG +!if $(TOOL_CHAIN_TAG) !=3D "XCODE5" GCC:*_*_*_CC_FLAGS =3D -mno-mmx -mno-sse +!endif =20 # # Disable deprecated APIs. diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index a9c667fed8..6bcbe70d64 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# # This program and the accompanying materials @@ -64,7 +64,9 @@ GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG INTEL:RELEASE_*_*_CC_FLAGS =3D /D MDEPKG_NDEBUG MSFT:RELEASE_*_*_CC_FLAGS =3D /D MDEPKG_NDEBUG +!if $(TOOL_CHAIN_TAG) !=3D "XCODE5" GCC:*_*_*_CC_FLAGS =3D -mno-mmx -mno-sse +!endif !ifdef $(SOURCE_DEBUG_ENABLE) MSFT:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable GCC:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index abf570512a..70fcdcba11 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -1,7 +1,7 @@ ## @file # EFI/Framework Open Virtual Machine Firmware (OVMF) platform # -# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP
# # This program and the accompanying materials @@ -64,7 +64,9 @@ GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG INTEL:RELEASE_*_*_CC_FLAGS =3D /D MDEPKG_NDEBUG MSFT:RELEASE_*_*_CC_FLAGS =3D /D MDEPKG_NDEBUG +!if $(TOOL_CHAIN_TAG) !=3D "XCODE5" GCC:*_*_*_CC_FLAGS =3D -mno-mmx -mno-sse +!endif !ifdef $(SOURCE_DEBUG_ENABLE) MSFT:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable GCC:*_*_X64_GENFW_FLAGS =3D --keepexceptiontable --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel