From nobody Mon Dec 23 18:06:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151559801821074.63937891257581; Wed, 10 Jan 2018 07:26:58 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CA4A521F833D0; Wed, 10 Jan 2018 07:21:44 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 64B8D222CF1B6 for ; Wed, 10 Jan 2018 07:21:43 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jan 2018 07:26:40 -0800 Received: from lgao4-mobl1.ccr.corp.intel.com ([10.254.210.57]) by fmsmga002.fm.intel.com with ESMTP; 10 Jan 2018 07:26:38 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,340,1511856000"; d="scan'208";a="9032559" From: Liming Gao To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 23:24:30 +0800 Message-Id: <20180110152432.15964-6-liming.gao@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 In-Reply-To: <20180110152432.15964-1-liming.gao@intel.com> References: <20180110152432.15964-1-liming.gao@intel.com> Subject: [edk2] [Patch 5/7] UefiCpuPkg: Update SmmCpuFeatureLib pass XCODE5 tool chain X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Laszlo Ersek , Jiewen Yao , Andrew Fish , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" 1. Use lea instruction to get the address instead of mov instruction. 2. Use the dummy address as jmp destination, and add the logic to fix up the address to the absolute address at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao Cc: Andrew Fish Cc: Jiewen Yao Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael Kinney --- .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 6 +++- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 8 +++-- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h | 11 +++++- .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 42 +++++++++++++++---= ---- .../SmmCpuFeaturesLib/X64/SmiException.nasm | 10 +++--- 5 files changed, 55 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm b/Uefi= CpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm index 00c0f0672c..057ec6d105 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -273,3 +273,7 @@ _StmSmiHandler: =20 ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPo= int + +global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress) +ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress): + ret diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.c index 45015b8da4..8dc2d70527 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -1,7 +1,7 @@ /** @file SMM STM support functions =20 - Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -116,7 +116,6 @@ UINTN mMsegSize =3D 0; =20 BOOLEAN mStmConfigurationTableInitialized =3D FALSE; =20 - /** The constructor function =20 @@ -139,6 +138,11 @@ SmmCpuFeaturesLibStmConstructor ( EFI_SMRAM_DESCRIPTOR *SmramDescriptor; =20 // + // Initialize address fixup + // + SmmCpuFeaturesLibStmSmiEntryFixupAddress (); + + // // Call the common constructor function // Status =3D SmmCpuFeaturesLibConstructor (ImageHandle, SystemTable); diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.h index 92a4dc00eb..c98b660ecb 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h @@ -1,7 +1,7 @@ /** @file SMM STM support =20 - Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -173,4 +173,13 @@ GetStmResource ( VOID ); =20 +/** + This function fixes up the address of the global variable or function + referred in SmiEntry assembly files to be the absoute address. +**/ +VOID +EFIAPI +SmmCpuFeaturesLibStmSmiEntryFixupAddress ( + ); + #endif diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm b/UefiC= puPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm index ea2d2970bd..e9c1306265 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -164,7 +164,9 @@ Base: mov cr0, rbx retf @LongMode: ; long mode (64-bit code) starts h= ere - mov rax, ASM_PFX(gStmSmiHandlerIdtr) + db 0x48, 0xB8 +StmSmiEntrySmiHandlerIdtrAbsAddr: + dq 0 ; mov rax, ASM_PFX(gStmSmiHan= dlerIdtr) lidt [rax] lea ebx, [rdi + DSC_OFFSET] mov ax, [rbx + DSC_DS] @@ -175,7 +177,10 @@ Base: mov gs, eax mov ax, [rbx + DSC_SS] mov ss, eax - + db 0x48, 0xB8 +StmSmiEntryCommonHandlerAbsAddr: + dq 0 ; mov rax, CommonHandler + jmp rax CommonHandler: mov rbx, [rsp + 0x08] ; rbx <- CpuIndex =20 @@ -188,16 +193,13 @@ CommonHandler: add rsp, -0x20 =20 mov rcx, rbx - mov rax, ASM_PFX(CpuSmmDebugEntry) - call rax + call ASM_PFX(CpuSmmDebugEntry) =20 mov rcx, rbx - mov rax, ASM_PFX(SmiRendezvous) ; rax <- absolute addr of= SmiRedezvous - call rax + call ASM_PFX(SmiRendezvous) =20 mov rcx, rbx - mov rax, ASM_PFX(CpuSmmDebugExit) - call rax + call ASM_PFX(CpuSmmDebugExit) =20 add rsp, 0x20 =20 @@ -208,7 +210,7 @@ CommonHandler: =20 add rsp, 0x200 =20 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz .1 @@ -228,7 +230,7 @@ _StmSmiHandler: ; Check XD disable bit ; xor r8, r8 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz @StmXdDone @@ -249,8 +251,9 @@ _StmSmiHandler: =20 ; below step is needed, because STM does not run above code. ; we have to run below code to set IDT/CR0/CR4 - - mov rax, ASM_PFX(gStmSmiHandlerIdtr) + db 0x48, 0xB8 +StmSmiHandlerIdtrAbsAddr: + dq 0 ; mov rax, ASM_PFX(gStmSmiHan= dlerIdtr) lidt [rax] =20 mov rax, cr0 @@ -264,3 +267,16 @@ _StmSmiHandler: =20 ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint + +global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress) +ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress): + lea rax, [ASM_PFX(gStmSmiHandlerIdtr)] + lea rcx, [StmSmiEntrySmiHandlerIdtrAbsAddr] + mov qword [rcx], rax + lea rcx, [StmSmiHandlerIdtrAbsAddr] + mov qword [rcx], rax + + lea rax, [CommonHandler] + lea rcx, [StmSmiEntryCommonHandlerAbsAddr] + mov qword [rcx], rax + ret diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm b/U= efiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm index ce9d7c2bb6..b0ab87b0d4 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -95,7 +95,7 @@ ASM_PFX(OnStmSetup): ; Check XD disable bit ; xor r8, r8 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz @StmXdDone1 @@ -118,7 +118,7 @@ ASM_PFX(OnStmSetup): call ASM_PFX(SmmStmSetup) add rsp, 0x20 =20 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz .11 @@ -139,7 +139,7 @@ ASM_PFX(OnStmTeardown): ; Check XD disable bit ; xor r8, r8 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz @StmXdDone2 @@ -162,7 +162,7 @@ ASM_PFX(OnStmTeardown): call ASM_PFX(SmmStmTeardown) add rsp, 0x20 =20 - mov rax, ASM_PFX(gStmXdSupported) + lea rax, [ASM_PFX(gStmXdSupported)] mov al, [rax] cmp al, 0 jz .12 --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel