From nobody Mon Dec 23 18:36:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151559802130990.20484655508687; Wed, 10 Jan 2018 07:27:01 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3C7832220D1E0; Wed, 10 Jan 2018 07:21:45 -0800 (PST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9729E2035D334 for ; Wed, 10 Jan 2018 07:21:43 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jan 2018 07:26:42 -0800 Received: from lgao4-mobl1.ccr.corp.intel.com ([10.254.210.57]) by fmsmga002.fm.intel.com with ESMTP; 10 Jan 2018 07:26:40 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,340,1511856000"; d="scan'208";a="9032566" From: Liming Gao To: edk2-devel@lists.01.org Date: Wed, 10 Jan 2018 23:24:31 +0800 Message-Id: <20180110152432.15964-7-liming.gao@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 In-Reply-To: <20180110152432.15964-1-liming.gao@intel.com> References: <20180110152432.15964-1-liming.gao@intel.com> Subject: [edk2] [Patch 6/7] UefiCpuPkg: Update PiSmmCpuDxeSmm pass XCODE5 tool chain X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Kinney , Laszlo Ersek , Jiewen Yao , Andrew Fish , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" 1. Use lea instruction to get the address instead of mov instruction. 2. Use the dummy address as jmp destination, and add the logic to fix up the address to the absolute address at boot time. 3. On MpFuncs.nasm, use ExchangeInfo to record InitializeFloatingPointUnits. This way is same to MpInitLib. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao Cc: Andrew Fish Cc: Jiewen Yao Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael Kinney --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 6 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 5 +++- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 6 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 8 ++++++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 20 +++++++++++++++- UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm | 9 ++++--- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 32 +++++++++++++++++----= ---- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm | 4 ++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm | 17 ++++++++++--- 9 files changed, 82 insertions(+), 25 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 94e5ab2c0e..554629536a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -1,7 +1,7 @@ /** @file Code for Processor S3 restoration =20 -Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD = License which accompanies this distribution. The full text of the license may be = found at @@ -14,6 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. =20 #include "PiSmmCpuDxeSmm.h" =20 +#pragma pack(1) typedef struct { UINTN Lock; VOID *StackStart; @@ -23,7 +24,9 @@ typedef struct { IA32_DESCRIPTOR IdtrProfile; UINT32 BufferStart; UINT32 Cr3; + UINTN InitializeFloatingPointUnitsAddress; } MP_CPU_EXCHANGE_INFO; +#pragma pack() =20 typedef struct { UINT8 *RendezvousFunnelAddress; @@ -456,6 +459,7 @@ PrepareApStartupVector ( mExchangeInfo->StackSize =3D mAcpiCpuData.StackSize; mExchangeInfo->BufferStart =3D (UINT32) StartupVector; mExchangeInfo->Cr3 =3D (UINT32) (AsmReadCr3 ()); + mExchangeInfo->InitializeFloatingPointUnitsAddress =3D (UINTN)Initialize= FloatingPointUnits; } =20 /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index 4d2383ff97..a8324a7f4a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -207,3 +207,6 @@ ASM_PFX(SmiHandler): =20 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint =20 +global ASM_PFX(PiSmmCpuSmiEntryFixupAddress) +ASM_PFX(PiSmmCpuSmiEntryFixupAddress): + ret diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/Ia32/SmmInit.nasm index d9df3626c7..a5c62e77ce 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -85,3 +85,7 @@ ASM_PFX(SmmRelocationSemaphoreComplete): mov byte [eax], 1 pop eax jmp [ASM_PFX(mSmmRelocationOriginalAddress)] + +global ASM_PFX(PiSmmCpuSmmInitFixupAddress) +ASM_PFX(PiSmmCpuSmmInitFixupAddress): + ret diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 4b66a0dfd9..a27d1f4684 100755 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -1,7 +1,7 @@ /** @file Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 -Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials @@ -543,6 +543,12 @@ PiCpuSmmEntry ( UINT32 Cr3; =20 // + // Initialize address fixup + // + PiSmmCpuSmmInitFixupAddress (); + PiSmmCpuSmiEntryFixupAddress (); + + // // Initialize Debug Agent to support source level debug in SMM code // InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index ef32f17676..0323bfff92 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -1,7 +1,7 @@ /** @file Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 -Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials @@ -1166,4 +1166,22 @@ EdkiiSmmGetMemoryAttributes ( IN UINT64 *Attributes ); =20 +/** + This function fixes up the address of the global variable or function + referred in SmmInit assembly files to be the absoute address. +**/ +VOID +EFIAPI +PiSmmCpuSmmInitFixupAddress ( + ); + +/** + This function fixes up the address of the global variable or function + referred in SmiEntry assembly files to be the absoute address. +**/ +VOID +EFIAPI +PiSmmCpuSmiEntryFixupAddress ( + ); + #endif diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm b/UefiCpuPkg/PiSmmC= puDxeSmm/X64/MpFuncs.nasm index 702233d6e4..704942ec27 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -18,8 +18,6 @@ ; ;-------------------------------------------------------------------------= ------ =20 -extern ASM_PFX(InitializeFloatingPointUnits) - %define VacantFlag 0x0 %define NotVacantFlag 0xff =20 @@ -31,6 +29,7 @@ extern ASM_PFX(InitializeFloatingPointUnits) %define IdtrLocation LockLocation + 0x2A %define BufferStartLocation LockLocation + 0x34 %define Cr3OffsetLocation LockLocation + 0x38 +%define InitializeFloatingPointUnitsAddress LockLocation + 0x3C =20 ;-------------------------------------------------------------------------= ------------ ;RendezvousFunnelProc procedure follows. All APs execute their procedure.= This @@ -153,7 +152,7 @@ Releaselock: ; ; Call assembly function to initialize FPU. ; - mov rax, ASM_PFX(InitializeFloatingPointUnits) + mov rax, qword [esi + InitializeFloatingPointUnitsAddress] sub rsp, 0x20 call rax add rsp, 0x20 @@ -185,7 +184,7 @@ RendezvousFunnelProcEnd: ; comments here for definition of address map global ASM_PFX(AsmGetAddressMap) ASM_PFX(AsmGetAddressMap): - mov rax, RendezvousFunnelProcStart + lea rax, [RendezvousFunnelProcStart] mov qword [rcx], rax mov qword [rcx+0x8], PMODE_ENTRY - RendezvousFunnelProcSta= rt mov qword [rcx+0x10], FLAT32_JUMP - RendezvousFunnelProcSt= art diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index dc56dc7852..3944b3e68c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -158,7 +158,9 @@ Base: mov cr0, rbx retf @LongMode: ; long mode (64-bit code) starts h= ere - mov rax, ASM_PFX(gSmiHandlerIdtr) + db 0x48, 0xB8 +SmiHandlerIdtrAbsAddr: + dq 0 ; mov rax, ASM_PFX(gSmiHandle= rIdtr) lidt [rax] lea ebx, [rdi + DSC_OFFSET] mov ax, [rbx + DSC_DS] @@ -169,7 +171,10 @@ Base: mov gs, eax mov ax, [rbx + DSC_SS] mov ss, eax -; jmp _SmiHandler ; instruction is not needed + db 0x48, 0xB8 +_SmiHandlerAbsAddr: + dq 0 ; mov rax, _SmiHandler + jmp rax =20 _SmiHandler: mov rbx, [rsp + 0x8] ; rcx <- CpuIndex @@ -184,16 +189,13 @@ _SmiHandler: add rsp, -0x20 =20 mov rcx, rbx - mov rax, ASM_PFX(CpuSmmDebugEntry) - call rax + call ASM_PFX(CpuSmmDebugEntry) =20 mov rcx, rbx - mov rax, ASM_PFX(SmiRendezvous) ; rax <- absolute addr of SmiRede= zvous - call rax + call ASM_PFX(SmiRendezvous) =20 mov rcx, rbx - mov rax, ASM_PFX(CpuSmmDebugExit) - call rax + call ASM_PFX(CpuSmmDebugExit) =20 add rsp, 0x20 =20 @@ -205,7 +207,7 @@ _SmiHandler: =20 add rsp, 0x200 =20 - mov rax, ASM_PFX(mXdSupported) + lea rax, [ASM_PFX(mXdSupported)] mov al, [rax] cmp al, 0 jz .1 @@ -222,3 +224,13 @@ _SmiHandler: =20 ASM_PFX(gcSmiHandlerSize) DW $ - _SmiEntryPoint =20 +global ASM_PFX(PiSmmCpuSmiEntryFixupAddress) +ASM_PFX(PiSmmCpuSmiEntryFixupAddress): + lea rax, [ASM_PFX(gSmiHandlerIdtr)] + lea rcx, [SmiHandlerIdtrAbsAddr] + mov qword [rcx], rax + + lea rax, [_SmiHandler] + lea rcx, [_SmiHandlerAbsAddr] + mov qword [rcx], rax + ret diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm b/UefiCpuPkg/P= iSmmCpuDxeSmm/X64/SmiException.nasm index b2e2e6dee6..a8a9af3008 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -289,7 +289,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile): =20 ;; call into exception handler mov rcx, [rbp + 8] - mov rax, ASM_PFX(SmiPFHandler) + lea rax, [ASM_PFX(SmiPFHandler)] =20 ;; Prepare parameter and call mov rdx, rsp diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmC= puDxeSmm/X64/SmmInit.nasm index 9d05e2cb05..2701689c3d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2016, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BS= D License ; which accompanies this distribution. The full text of the license may b= e found at @@ -60,7 +60,7 @@ ASM_PFX(gSmmCr4): DD 0 ASM_PFX(gSmmCr0): DD 0 mov cr0, rax ; enable protected mode & paging DB 0x66, 0xea ; far jmp to long mode -ASM_PFX(gSmmJmpAddr): DQ @LongMode +ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode @LongMode: ; long-mode starts here DB 0x48, 0xbc ; mov rsp, imm64 ASM_PFX(gSmmInitStack): DQ 0 @@ -99,7 +99,7 @@ ASM_PFX(gcSmmInitTemplate): sub ebp, 0x30000 jmp ebp @L1: - DQ ASM_PFX(SmmStartup) + DQ 0; ASM_PFX(SmmStartup) =20 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate) =20 @@ -128,3 +128,14 @@ ASM_PFX(mRebasedFlagAddr32): dd 0 ; db 0xff, 0x25 ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0 + +global ASM_PFX(PiSmmCpuSmmInitFixupAddress) +ASM_PFX(PiSmmCpuSmmInitFixupAddress): + lea rax, [@LongMode] + lea rcx, [ASM_PFX(gSmmJmpAddr)] + mov qword [rcx], rax + + lea rax, [ASM_PFX(SmmStartup)] + lea rcx, [@L1] + mov qword [rcx], rax + ret --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel