From nobody Mon Dec 23 09:57:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1517902043811295.4112427052321; Mon, 5 Feb 2018 23:27:23 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 496C62034A8A6; Mon, 5 Feb 2018 23:21:40 -0800 (PST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CDF9021F0DA4C for ; Mon, 5 Feb 2018 23:21:38 -0800 (PST) Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Feb 2018 23:27:21 -0800 Received: from ray-dev.ccr.corp.intel.com ([10.239.9.19]) by orsmga008.jf.intel.com with ESMTP; 05 Feb 2018 23:27:19 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,467,1511856000"; d="scan'208";a="15774695" From: Ruiyu Ni To: edk2-devel@lists.01.org Date: Tue, 6 Feb 2018 15:27:16 +0800 Message-Id: <20180206072716.359712-1-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.16.1.windows.1 Subject: [edk2] [PATCH] UefiCpuPkg/FeaturesLib: Fix Haswell CPU hang with 50% throttling X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Today's implementation only assumes SandyBridge CPU supports Extended On-Demand Clock Modulation Duty Cycle. Actually it is supported when CPUID.06h.EAX[5] =3D=3D 1. When platform requests 50% throttling, it causes value 1000b set to the low-4 bits of IA32_CLOCK_MODULATION. But the wrong code sets 1000b to bits[1-3] which causes assertion. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Jeff Fan Cc: Eric Dong Reviewed-by: Eric Dong --- .../Library/CpuCommonFeaturesLib/ClockModulation.c | 52 ++++++++++--------= ---- 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c b/Ue= fiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c index 56e53561e9..84d59de78f 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c @@ -1,7 +1,7 @@ /** @file Clock Modulation feature. =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -67,40 +67,34 @@ ClockModulationInitialize ( IN BOOLEAN State ) { - if (IS_SANDY_BRIDGE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayM= odel)) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, - MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER, - Bits.OnDemandClockModulationDutyCycle, - PcdGet8 (PcdCpuClockModulationDutyCycle) - ); - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, - MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER, - Bits.OnDemandClockModulationEnable, - (State) ? 1 : 0 - ); - } else { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_CLOCK_MODULATION, - MSR_IA32_CLOCK_MODULATION_REGISTER, - Bits.OnDemandClockModulationDutyCycle, - PcdGet8 (PcdCpuClockModulationDutyCycle) - ); + CPUID_THERMAL_POWER_MANAGEMENT_EAX ThermalPowerManagementEax; + AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &ThermalPowerManagementEax.Uin= t32, NULL, NULL, NULL); + + CPU_REGISTER_TABLE_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_CLOCK_MODULATION, + MSR_IA32_CLOCK_MODULATION_REGISTER, + Bits.OnDemandClockModulationDutyCycle, + PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1 + ); + if (ThermalPowerManagementEax.Bits.ECMD =3D=3D 1) { CPU_REGISTER_TABLE_WRITE_FIELD ( ProcessorNumber, Msr, MSR_IA32_CLOCK_MODULATION, MSR_IA32_CLOCK_MODULATION_REGISTER, - Bits.OnDemandClockModulationEnable, - (State) ? 1 : 0 + Bits.ExtendedOnDemandClockModulationDutyCycle, + PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0 ); } + CPU_REGISTER_TABLE_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_CLOCK_MODULATION, + MSR_IA32_CLOCK_MODULATION_REGISTER, + Bits.OnDemandClockModulationEnable, + (State) ? 1 : 0 + ); return RETURN_SUCCESS; } --=20 2.16.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel