From nobody Mon Dec 23 09:40:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518072238059146.10832178841406; Wed, 7 Feb 2018 22:43:58 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 01BB422361E4E; Wed, 7 Feb 2018 22:38:12 -0800 (PST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EA7B322361E46 for ; Wed, 7 Feb 2018 22:38:10 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Feb 2018 22:43:54 -0800 Received: from ray-dev.ccr.corp.intel.com ([10.239.9.19]) by orsmga001.jf.intel.com with ESMTP; 07 Feb 2018 22:43:53 -0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.136; helo=mga12.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,477,1511856000"; d="scan'208";a="29799603" From: Ruiyu Ni To: edk2-devel@lists.01.org Date: Thu, 8 Feb 2018 14:43:52 +0800 Message-Id: <20180208064352.156152-1-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.16.1.windows.1 Subject: [edk2] [PATCH] UefiCpuPkg/FeaturesLib: don't init MCi_CTL/STATUS when MCA's disabled X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Today's McaInitialize() doesn't check State value before initialize MCi_CTL and MCi_STATUS. The patch fixes this issue by only initializing the two kinds of MSRs when State is enabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Eric Dong Reviewed-by: Eric Dong --- .../Library/CpuCommonFeaturesLib/MachineCheck.c | 32 ++++++++++++------= ---- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiC= puPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index 58dc45aeda..cc64dbbf0a 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -1,7 +1,7 @@ /** @file Machine Check features. =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -140,25 +140,27 @@ McaInitialize ( MSR_IA32_MCG_CAP_REGISTER McgCap; UINT32 BankIndex; =20 - McgCap.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_CAP); - for (BankIndex =3D 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex+= +) { - CPU_REGISTER_TABLE_WRITE64 ( - ProcessorNumber, - Msr, - MSR_IA32_MC0_CTL + BankIndex * 4, - MAX_UINT64 - ); - } - - if (PcdGetBool (PcdIsPowerOnReset)) { - for (BankIndex =3D 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex= ++) { + if (State =3D=3D TRUE) { + McgCap.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_CAP); + for (BankIndex =3D 0; BankIndex < (UINT32) McgCap.Bits.Count; BankInde= x++) { CPU_REGISTER_TABLE_WRITE64 ( ProcessorNumber, Msr, - MSR_IA32_MC0_STATUS + BankIndex * 4, - 0 + MSR_IA32_MC0_CTL + BankIndex * 4, + MAX_UINT64 ); } + + if (PcdGetBool (PcdIsPowerOnReset)) { + for (BankIndex =3D 0; BankIndex < (UINTN) McgCap.Bits.Count; BankInd= ex++) { + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_MC0_STATUS + BankIndex * 4, + 0 + ); + } + } } =20 return RETURN_SUCCESS; --=20 2.16.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel