From nobody Mon Dec 23 09:26:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519149024930332.3596379786575; Tue, 20 Feb 2018 09:50:24 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2E5EC220F33F4; Tue, 20 Feb 2018 09:44:14 -0800 (PST) Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EBC8821FD73E6 for ; Tue, 20 Feb 2018 09:44:11 -0800 (PST) Received: by mail-wr0-x243.google.com with SMTP id u49so12177170wrc.10 for ; Tue, 20 Feb 2018 09:50:10 -0800 (PST) Received: from localhost.localdomain ([105.149.187.179]) by smtp.gmail.com with ESMTPSA id u63sm18282208wrc.26.2018.02.20.09.50.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Feb 2018 09:50:07 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B+NhtysjwTe0RVa7aV+wMjT840a+fwn2z7JdoF9U1VY=; b=HTRqp6dl9mb5xa6gXgM8vyH9mGNo+ESjy7Gp3f923zeMOdT6fwfwLju120BHyeNYeI 114InPM8kg+tNWV5Mgt0L3XWadbCrAaKPcg4z7+1jH3mMNbGt+LPA0+K36BuEGo3DNN5 NKrETJhr/dPRROpBhMbVkLGIe+hFhQFFzjrVg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=B+NhtysjwTe0RVa7aV+wMjT840a+fwn2z7JdoF9U1VY=; b=bTtCBJIHoR7v7Aa208bzA7D0F2NCVn5s+0970lxr0ZVc1wx1hJpf7B0q28aGPoyMIB oxlXaoyUPT8VfjS7OFZLQNuYhUYPGx+6+3k6KFH5iallgnyVNldIx49I311+LtU3Ef3K 3qvv1H93m2/Fm1weqilwpqHwsK4h/+XGqlMm8Ai1yhd1DzTjAoWZgMiTD6U0nAgdkbzs k7O4FC+nlwA+wuh6X7k9WkH8PZSDyIheF33fvWz43MXUe+vtencUKn/frSig5vop5uCV dR1xl6p01LiFqdfJACsTmKKCQqSqboCl5RuU+D/FWHzmWDjW3EcFJl7VN1/Qdm/Bh/OY nYAA== X-Gm-Message-State: APf1xPDz1F0t//iLbJsV/XK124antowcBX+21PXI8Quu+4DnIZ2/hZSg fD1XlLT5rt+fUW8HX7H9HANEZFg9c3o= X-Google-Smtp-Source: AH8x224tQnXPeZaV8XAZ8BhRyYl50zu4c4bpCvT0MWQAjvlhBmn6Wz70K8IcPPl0K2Ynt3rAmRX0Ww== X-Received: by 10.28.51.6 with SMTP id z6mr891831wmz.26.1519149008903; Tue, 20 Feb 2018 09:50:08 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 20 Feb 2018 17:49:44 +0000 Message-Id: <20180220174944.525-8-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180220174944.525-1-ard.biesheuvel@linaro.org> References: <20180220174944.525-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 7/7] Platform/Socionext/DeveloperBox: add 96boards mezzanine support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Wire up the various drivers for the 96boards LS connector and the optional Secure96 mezzanine board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 34 +++++= +++++++++++++++ Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 10 ++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 9 ++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 2 ++ 4 files changed, 55 insertions(+) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/So= cionext/DeveloperBox/DeveloperBox.dsc index 9c95618a20fe..39f40534bb39 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -33,6 +33,9 @@ [Defines] [BuildOptions] RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_S= OURCE=3D0 =20 + # add ample padding to the DTC so we can apply 96boards mezzanine overla= ys + *_*_*_DTC_FLAGS =3D -p 1024 + [BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,B= uildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICA= TION] GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 =20 @@ -398,6 +401,28 @@ [PcdsFixedAtBuild.common] !endif gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(BUILD_NUMBER) =20 + # + # 96boards mezzanine support + # + gNinetySixBoardsTokenSpaceGuid.PcdI2c0Parent|"/i2c@51210000" + gNinetySixBoardsTokenSpaceGuid.PcdI2c0BusFrequencyHz|100000 + gNinetySixBoardsTokenSpaceGuid.PcdSpiParent|"/spi@54810000" + gNinetySixBoardsTokenSpaceGuid.PcdGpioParent|"/gpio@51000000" + gNinetySixBoardsTokenSpaceGuid.PcdGpioPolarity|0 + + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinA|10 + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinB|11 + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinC|12 + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinD|13 + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinE|18 + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinF|19 + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinG|20 + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinH|21 + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinI|22 + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinJ|23 + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinK|24 + gNinetySixBoardsTokenSpaceGuid.PcdGpioPinL|25 + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 @@ -644,8 +669,17 @@ [Components.common] SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.= inf =20 # + # 96board mezzanine support + # + Platform/NinetySixBoards/Secure96Dxe/Secure96Dxe.inf + Silicon/Atmel/AtSha204a/AtSha204aDxe.inf + Platform/NinetySixBoards/NinetySixBoardsI2cDxe/NinetySixBoardsI2cDxe.inf + Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsDxe.inf + + # # I2C # Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf + MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf =20 Platform/Socionext/DeveloperBox/OsInstallerMenuDxe/OsInstallerMenuDxe.inf diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/So= cionext/DeveloperBox/DeveloperBox.fdf index c2bc5aa85739..636bfaa3dd29 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -237,9 +237,18 @@ [FV.FvMain] } =20 # + # 96board mezzanine support + # + INF Platform/NinetySixBoards/Secure96Dxe/Secure96Dxe.inf + INF Platform/NinetySixBoards/NinetySixBoardsI2cDxe/NinetySixBoardsI2cDxe= .inf + INF Silicon/Atmel/AtSha204a/AtSha204aDxe.inf + INF Platform/NinetySixBoards/NinetySixBoardsDxe/NinetySixBoardsDxe.inf + + # # I2C # INF Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.= inf + INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf =20 INF Platform/Socionext/DeveloperBox/OsInstallerMenuDxe/OsInstallerMenuDx= e.inf =20 @@ -430,6 +439,7 @@ [Rule.Common.DXE_DRIVER] DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi UI STRING=3D"$(MODULE_NAME)" Optional + RAW BIN Optional |.dtb } =20 [Rule.Common.DXE_RUNTIME_DRIVER] diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index aab830dc3a5a..11c0648c2ca0 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -313,6 +313,15 @@ PlatformDxeEntryPoint ( &Handle); ASSERT_EFI_ERROR (Status); =20 + // + // Install the gNinetySixBoardsI2c0MasterGuid GUID onto the same handle, + // identifying I2C #1 on our SoC as I2C #0 on the 96boards low speed con= nector + // + Status =3D gBS->InstallProtocolInterface (&Handle, + &gNinetySixBoardsI2c0MasterGuid, + EFI_NATIVE_INTERFACE, NULL); + ASSERT_EFI_ERROR (Status); + SmmuEnableCoherentDma (); SetMmioTimerFrequency (); =20 diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 49d9deee57ea..4ba8bf4f761e 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -34,6 +34,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Platform/NinetySixBoards/NinetySixBoards.dec Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -56,6 +57,7 @@ [LibraryClasses] UefiRuntimeServicesTableLib =20 [Guids] + gNinetySixBoardsI2c0MasterGuid gEfiHiiPlatformSetupFormsetGuid gFdtTableGuid gNetsecNonDiscoverableDeviceGuid --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel