From nobody Mon Dec 23 05:21:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519765605068345.3787496200481; Tue, 27 Feb 2018 13:06:45 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6CB9D20954CB5; Tue, 27 Feb 2018 13:00:37 -0800 (PST) Received: from atlmailgw2.ami.com (atlmailgw2.ami.com [63.147.10.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DCB6222352291 for ; Tue, 27 Feb 2018 13:00:35 -0800 (PST) Received: from atlms1.us.megatrends.com (atlms1.us.megatrends.com [172.16.96.144]) (using TLS with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by atlmailgw2.ami.com (Symantec Messaging Gateway) with SMTP id 14.A8.01718.068C59A5; Tue, 27 Feb 2018 16:06:40 -0500 (EST) Received: from Felix7.us.megatrends.com (172.16.99.93) by atlms1.us.megatrends.com (172.16.96.144) with Microsoft SMTP Server id 14.3.123.3; Tue, 27 Feb 2018 16:06:40 -0500 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=63.147.10.42; helo=atlmailgw2.ami.com; envelope-from=felixp@ami.com; receiver=edk2-devel@lists.01.org X-AuditID: ac10606f-88bff700000006b6-85-5a95c860898f From: Felix Polyudov To: Date: Tue, 27 Feb 2018 16:06:40 -0500 Message-ID: <20180227210640.7536-1-felixp@ami.com> X-Mailer: git-send-email 2.10.0.windows.1 MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKIsWRmVeSWpSXmKPExsWyRiBhgm7CialRBku+WVjsOXSU2WLFvQ3s Fh0d/5gcmD0W73nJ5NE9+x9LAFNUA6NNYl5efkliSapCSmpxsq1SQFFmWWJypZJCZoqtkqGS QkFOYnJqbmpeia1SYkFBal6Kkh2XAgawASrLzFNIzUvOT8nMS7dV8gz217WwMLXUNVSyC8lI VcjMS8svyk0syczPU0jOzysBqk5NAYoqJHRxZnz/Hl7wRLli0/KjjA2M66W7GDk5JARMJA6t ucTaxcjFISSwnUmi/dVhNghnA6NE763H7CBVbAKqElsmrmIBsUUEZCX+dH4Cs5kFQiVunFwC ViMsECIx4eVpVhCbBah+x6b5zCA2r4CRxI4HDawQ2zQlps96DRUXlDg58wnUHAmJgy9egMWF BKQlzj78zTiBkXcWkrJZSMoWMDKtYhRKLMnJTczMSS830kvMzdRLzs/dxAiJlfwdjB8/mh9i FOBgVOLhtdg1NUqINbGsuDL3EKMEB7OSCO/KxZOjhHhTEiurUovy44tKc1KLDzE6AZ09kVmK GxRswHiINzYwkBKFcQxNzEzMjcwNLU3MjY2VxHkDTp6OFBJIB8ZndmpqQWoRzBAmDk6pBsY9 sxZ8y561WM3caEvE5EeT0z//Co9cLvZSZX+or3L9nS7xu9yvmK4nCQo8OyHH+8xn7xTh+WWr Ahax7DzRd+TPBPEm5ud3z2h8uJLTV/F7Q0bFo6jFhh9i9//yOPbcpCNx0W85+yBPG8UNFmFV Fxf7ThNd+XT7y8+bn2rHnN/sYDlLxOHr684rSizFGYmGWsxFxYkA9lpCy7gCAAA= Subject: [edk2] [Patch v2] MdePkg/Include/IndustryStandard: Add PCI Express 4.0 header file X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: michael.d.kinney@intel.com, manickavasakamk@ami.com, liming.gao@intel.com Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" v2: The structure is updated to include all the fields defined=20 in the PCI-E specification. The header includes Physical Layer PCI Express Extended Capability definiti= ons described in section 7.7.5 of PCI Express Base Specification rev. 4.0. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Felix Polyudov --- MdePkg/Include/IndustryStandard/PciExpress40.h | 89 ++++++++++++++++++++++= ++++ 1 file changed, 89 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/PciExpress40.h diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Includ= e/IndustryStandard/PciExpress40.h new file mode 100644 index 0000000..a832259 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h @@ -0,0 +1,89 @@ +/** @file +Support for the PCI Express 4.0 standard. + +This header file may not define all structures. Please extend as required. + +Copyright (c) 2018, American Megatrends, Inc. All rights reserved.
+This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD = License +which accompanies this distribution. The full text of the license may be = found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLI= ED. + +**/ + +#ifndef _PCIEXPRESS40_H_ +#define _PCIEXPRESS40_H_ + +#include + +#pragma pack(1) + +/// The Physical Layer PCI Express Extended Capability definitions. +/// +/// Based on section 7.7.5 of PCI Express Base Specification 4.0. +///@{ +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID 0x0026 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1 + +// Register offsets from Physical Layer PCI-E Ext Cap Header +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET = 0x04=20 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET = 0x08 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET = 0x0C +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSE= T 0x10 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STAT= US_OFFSET 0x14 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STA= TUS_OFFSET 0x18 +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFS= ET 0x20 + +typedef union { + struct { + UINT32 Reserved : 32; // Reserved bit 0:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES; + +typedef union { + struct { + UINT32 Reserved : 32; // Reserved bit 0:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL; + +typedef union { + struct { + UINT32 EqualizationComplete : 1; // bit 0 + UINT32 EqualizationPhase1Success : 1; // bit 1 + UINT32 EqualizationPhase2Success : 1; // bit 2 + UINT32 EqualizationPhase3Success : 1; // bit 3 + UINT32 LinkEqualizationRequest : 1; // bit 4 + UINT32 Reserved : 27; // Reserved bit 5:31 + } Bits; + UINT32 Uint32; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS; + +typedef union { + struct { + UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3 + UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7 + } Bits; + UINT8 Uint8; +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablitie= s; + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control; + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status; + UINT32 LocalDataP= arityMismatchStatus; + UINT32 FirstRetim= erDataParityMismatchStatus; + UINT32 SecondReti= merDataParityMismatchStatus; + UINT32 Reserved; + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEquali= zationControl; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0; +///@} + +#pragma pack() + +#endif --=20 2.10.0.windows.1 Please consider the environment before printing this email. The information contained in this message may be confidential and proprieta= ry to American Megatrends, Inc. This communication is intended to be read = only by the individual or entity to whom it is addressed or by their design= ee. If the reader of this message is not the intended recipient, you are on= notice that any distribution of this message, in any form, is strictly pro= hibited. Please promptly notify the sender by reply e-mail or by telephone= at 770-246-8600, and then delete or destroy all copies of the transmission. _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel