From nobody Mon Dec 23 10:16:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519845901245383.75277485081926; Wed, 28 Feb 2018 11:25:01 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 38D9E223522B5; Wed, 28 Feb 2018 11:18:47 -0800 (PST) Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2FDE9223522B5 for ; Wed, 28 Feb 2018 11:18:46 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id i3so5792164wmi.4 for ; Wed, 28 Feb 2018 11:24:53 -0800 (PST) Received: from localhost.localdomain ([160.163.57.8]) by smtp.gmail.com with ESMTPSA id 47sm2152312wrb.48.2018.02.28.11.24.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Feb 2018 11:24:51 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IpnR5CHMAnD9xNOsB3ZabaF/4F7z5Far0onb4lR0uCo=; b=eJfx7J2WuF4ANw+NBKlhyWdONmX6H76ULCEmhNlFDbcubW7QI4z/o92Fx5G3diP3yP kVF5C00Fh9RXH1K+/XjulAQD2zYK8eXV2IA3dklwlS+64Isw4JpYtc6Jc1Q8skJmnWzN cTyZpfj7lqkISQ9RH62aonzfs13gH46QYE3dg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IpnR5CHMAnD9xNOsB3ZabaF/4F7z5Far0onb4lR0uCo=; b=OrWJaAJW06FFgK4cQpvmuy9PhdCW6AuEbLqM2ZQrJwiHX1xwCPaxAMQVgIlUj4xVF+ SIg3oUGaemc2+MPAXnIzPAYTV6aysJTNhxYo9Jp9ILX2MsvEWBqkl9acTYdGHGBsG5Jw OoxneBhqy1neqf0Wk55xFibELZZHdqSoEz3yy0WyadtJJmRAcPA+IKjuOwz8fflMZOV0 Kxh4RtF4nFSMKWiFaVVetH87N8ozL7iQUa5vhvrpXFeTgE43EiZTeazeHJs3KVA0cLKL LeWbEZ8ehgwjcRBL1fKdS6GCPf9OrBKjcQbDp36TV874MmLC4ShgbL0BGW+vUe8IcPXS GgRA== X-Gm-Message-State: APf1xPD/r5EkCtqYFjkqbCk7VGG/Kpr7J3QVwI9kfRonzHwhxcVhxn1S lqD2KVLXiurIE66faLvFt6jWKwqPXVY= X-Google-Smtp-Source: AH8x2269/VZ7illHkyIRSzmhVeMteuZxooo1SZNMwFaIJXtf+u5aQzJd+e8TydJDgnyHFTonvLAaMw== X-Received: by 10.28.229.85 with SMTP id c82mr15885517wmh.76.1519845891910; Wed, 28 Feb 2018 11:24:51 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 28 Feb 2018 19:24:21 +0000 Message-Id: <20180228192421.17684-8-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180228192421.17684-1-ard.biesheuvel@linaro.org> References: <20180228192421.17684-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 7/7] Silicon/SynQuacer/AcpiTables: take presence detect of PCI0 into account X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On the SynQuacer Evalution Board, PCIe RC #0 is not clocked if no card is inserted into the PCIe slot, and so any attempt to access the device registers will lock up the system. So let's check the presence detect pin directly in the _STA implementation of PCI0. This needs to be done before the config space check, because that access itself will lock the system if no card is inserted. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 15 ++++++++++= +++++ Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf | 1 + 2 files changed, 16 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b/S= ilicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl index 5ffed663e17d..db529aa95220 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl @@ -14,6 +14,7 @@ =20 **/ =20 +#include #include =20 #include "AcpiTables.h" @@ -37,7 +38,21 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQU= ACR", VPID, 16, } =20 + OperationRegion (GPIO, SystemMemory, SYNQUACER_GPIO_BASE, 8) + Field (GPIO, DWordAcc, NoLock, Preserve) { + , 39, + PRDT, 1, + , 24, + } + Method (_STA, 0x0, Serialized) { + If (!LEqual (FixedPcdGet8 (PcdPcie0PresenceDetectGpioPin), 0xf= f)) { + Store (PRDT, local0) + If (!LEqual (local0, 0x0)) { + Return (0x0) + } + } + // // Check whether the VID/PID of device #1 on bus #0 equals 0xf= fff. // If this is not the case, we are dealing with a ghost device, diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf b/Silico= n/Socionext/SynQuacer/AcpiTables/AcpiTables.inf index b1b6bbaa481d..bca8354d1184 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiTables.inf @@ -62,3 +62,4 @@ [FixedPcd] =20 gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress + gSynQuacerTokenSpaceGuid.PcdPcie0PresenceDetectGpioPin --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel