From nobody Mon Dec 23 09:58:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1519949087650752.194340478978; Thu, 1 Mar 2018 16:04:47 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BE5542255D6CE; Thu, 1 Mar 2018 15:58:20 -0800 (PST) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2AABF2255D6C0 for ; Thu, 1 Mar 2018 15:58:19 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 6EC4F8D746; Fri, 2 Mar 2018 00:04:27 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-4.rdu2.redhat.com [10.10.120.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id 842EE10B0F24; Fri, 2 Mar 2018 00:04:26 +0000 (UTC) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=66.187.233.73; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org From: Laszlo Ersek To: edk2-devel-01 Date: Fri, 2 Mar 2018 01:03:59 +0100 Message-Id: <20180302000408.14201-12-lersek@redhat.com> In-Reply-To: <20180302000408.14201-1-lersek@redhat.com> References: <20180302000408.14201-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:27 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.2]); Fri, 02 Mar 2018 00:04:27 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'lersek@redhat.com' RCPT:'' Subject: [edk2] [PATCH 11/20] OvmfPkg/SmmCpuFeaturesLib: upper-case the "static" keyword X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Brijesh Singh , Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In edk2, the "static" keyword is spelled "STATIC". Also let "STATIC" stand alone on a line in function definitions. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek --- OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/OvmfPk= g/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index a876a6e34751..6b9924e49426 100644 --- a/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -427,61 +427,61 @@ typedef struct { /// /// Structure used to build a lookup table to retrieve the widths and offs= ets /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value /// =20 #define SMM_SAVE_STATE_REGISTER_FIRST_INDEX 1 =20 typedef struct { UINT8 Width32; UINT8 Width64; UINT16 Offset32; UINT16 Offset64Lo; UINT16 Offset64Hi; BOOLEAN Writeable; } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY; =20 /// /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGI= STER /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY /// -static CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] =3D= { +STATIC CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] =3D= { SMM_REGISTER_RANGE ( EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO ), SMM_REGISTER_RANGE ( EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP ), SMM_REGISTER_RANGE ( EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4 ), { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 } }; =20 /// /// Lookup table used to retrieve the widths and offsets associated with e= ach /// supported EFI_SMM_SAVE_STATE_REGISTER value /// -static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] =3D { +STATIC CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] =3D { { 0, // Width32 0, // Width64 0, // Offset32 0, // Offset64Lo 0, // Offset64Hi FALSE // Writeable }, // Reserved =20 // // CPU Save State registers defined in PI SMM CPU Protocol. // { 0, // Width32 8, // Width64 0, // Offset32 SMM_CPU_OFFSET (x64._GDTRBase), // Offset64Lo SMM_CPU_OFFSET (x64._GDTRBase) + 4, // Offset64Hi FALSE // Writeable }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE =3D 4 @@ -816,41 +816,42 @@ static CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuW= idthOffset[] =3D { 0, // Offset32 SMM_CPU_OFFSET (x64._CR4), // Offset64Lo SMM_CPU_OFFSET (x64._CR4) + 4, // Offset64Hi FALSE // Writeable }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 =3D 54 }; =20 // // No support for I/O restart // =20 /** Read information from the CPU save state. =20 @param Register Specifies the CPU register to read form the save state. =20 @retval 0 Register is not valid @retval >0 Index into mSmmCpuWidthOffset[] associated with Register =20 **/ -static UINTN +STATIC +UINTN GetRegisterIndex ( IN EFI_SMM_SAVE_STATE_REGISTER Register ) { UINTN Index; UINTN Offset; =20 for (Index =3D 0, Offset =3D SMM_SAVE_STATE_REGISTER_FIRST_INDEX; mSmmCpuRegisterRanges[Index].Length !=3D 0; Index++) { if (Register >=3D mSmmCpuRegisterRanges[Index].Start && Register <=3D mSmmCpuRegisterRanges[Index].End) { return Register - mSmmCpuRegisterRanges[Index].Start + Offset; } Offset +=3D mSmmCpuRegisterRanges[Index].Length; } return 0; } =20 /** @@ -859,41 +860,42 @@ GetRegisterIndex ( This function abstracts the differences that whether the CPU Save State register is in the IA32 CPU Save State Map or X64 CPU Save State Map. =20 This function supports reading a CPU Save State register in SMBase reloc= ation handler. =20 @param[in] CpuIndex Specifies the zero-based index of the CPU save state. @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table. @param[in] Width The number of bytes to read from the CPU save state. @param[out] Buffer Upon return, this holds the CPU register value read from the save state. =20 @retval EFI_SUCCESS The register was read from Save State. @retval EFI_NOT_FOUND The register is not defined for the Save S= tate of Processor. @retval EFI_INVALID_PARAMTER This or Buffer is NULL. =20 **/ -static EFI_STATUS +STATIC +EFI_STATUS ReadSaveStateRegisterByIndex ( IN UINTN CpuIndex, IN UINTN RegisterIndex, IN UINTN Width, OUT VOID *Buffer ) { QEMU_SMRAM_SAVE_STATE_MAP *CpuSaveState; =20 CpuSaveState =3D (QEMU_SMRAM_SAVE_STATE_MAP *)gSmst->CpuSaveState[CpuInd= ex]; =20 if ((CpuSaveState->x86.SMMRevId & 0xFFFF) =3D=3D 0) { // // If 32-bit mode width is zero, then the specified register can not be // accessed // if (mSmmCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { return EFI_NOT_FOUND; } =20 --=20 2.14.1.3.gb7cf6e02401b _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel