From nobody Mon Dec 23 04:48:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1520076580321457.36800069682556; Sat, 3 Mar 2018 03:29:40 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0485621E08295; Sat, 3 Mar 2018 03:23:28 -0800 (PST) Received: from mail-wr0-x235.google.com (mail-wr0-x235.google.com [IPv6:2a00:1450:400c:c0c::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8373921E0828E for ; Sat, 3 Mar 2018 03:23:25 -0800 (PST) Received: by mail-wr0-x235.google.com with SMTP id v65so12563039wrc.11 for ; Sat, 03 Mar 2018 03:29:36 -0800 (PST) Received: from localhost.localdomain ([196.71.216.221]) by smtp.gmail.com with ESMTPSA id y111sm9257950wrc.0.2018.03.03.03.29.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 03 Mar 2018 03:29:33 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::235; helo=mail-wr0-x235.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=vvRVL+FnAPXfCZQoIJSSJs0bdCuCUcfMUZSLNP1mxxo=; b=GTxU6svNQvVTf/w2ud/4stb7WxZsXk6eYRbVF8NtnjbY5i9ldT7CKTAd76n6hNWZib FlFv+ZdJQ16Ab7scmZXxk+0WVSKgJLyj2ndWzCd+5UPJy9kL2fFlCPrtGw/keq74gr8B 7kTPam2h6oBIqYenTMPVFcj5JPqwf/5FHVIWE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=vvRVL+FnAPXfCZQoIJSSJs0bdCuCUcfMUZSLNP1mxxo=; b=Vn4+T9wSSXR+VWfb17ZSIAEeV3qo5e7jgrZpXt4A4E4bHqTLAA4NnGBciNPH7NN5k3 5k7TjwANwk7tzkJk50UTTvPd/IL5qjWvsvv0Ddvaj0ImzPdwgHo69X71c1Fhb4+neF6D nlyiJU2n4n4ygP76GAb9cJKuKY0oXGzQsippXXcYDeiooV6FYVjzLJ5QHGAtjBxaYm9V ljPO/BBt5euArtomhwsmVHb6dFWPnQFvhdRYV/4NKpa8ZxTJKxgHY7lhrNGhbaQ+wlt7 CdmRCgHzpsD4+0TUhwN0TWo76ahRNKkIF0qDg5EGmslWP3oiRm9Q9q+eAsA5rHXTR6sV 1c2w== X-Gm-Message-State: APf1xPA/1Kc1Ei1cAeVEg1l5HhqMK8vpioezPzeR7vI7QDuaVXN6dupD +/QAhF8JcX506XRCjf9DQPRdXWRHuM8= X-Google-Smtp-Source: AG47ELs/3kUG8Pf0g3w99HdqVhFpIUZV2p8ePvV7zL0Jj5PcXRMn63LhVbHiELqtrxEuTOBJd7N6Zw== X-Received: by 10.223.164.153 with SMTP id g25mr7946479wrb.79.1520076574410; Sat, 03 Mar 2018 03:29:34 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Sat, 3 Mar 2018 11:29:23 +0000 Message-Id: <20180303112923.13521-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms] Platform/Socionext/DeveloperBox: add SMBIOS tables X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This adds SMBIOS tables to the DeveloperBox platform describing the BIOS, system, enclosure, CPUs, caches, PCIe slots and system memory, which almost amounts to the mandatory minimum as given by the SMBIOS spec. Only the type 17 structures currently lack detailed information about the DIMMs: the SPDs are on a I2C bus that is only accessible by the SCP, and it currently does not share this information. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | = 9 + Platform/Socionext/DeveloperBox/DeveloperBox.fdf | = 6 + Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformDxe.c | = 641 ++++++++++++++++++++ Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | = 47 ++ 4 files changed, 703 insertions(+) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/So= cionext/DeveloperBox/DeveloperBox.dsc index d170266087af..c971f76233b0 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -688,4 +688,13 @@ [Components.common] =20 !include Silicon/Socionext/SynQuacer/Acpi.dsc.inc =20 + # + # SMBIOS/DMI support + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformDxe.inf { + + *_*_*_CC_FLAGS =3D -DFIRMWARE_VENDOR=3D\"$(FIRMWARE_VENDOR)\" -DBUIL= D_NUMBER=3D\"$(BUILD_NUMBER)\" + } + Platform/Socionext/DeveloperBox/OsInstallerMenuDxe/OsInstallerMenuDxe.inf diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/So= cionext/DeveloperBox/DeveloperBox.fdf index 851082808564..0dfefe428fb2 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -260,6 +260,12 @@ [FV.FvMain] INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf INF RuleOverride =3D ACPITABLE Silicon/Socionext/SynQuacer/AcpiTables/Ac= piTables.inf =20 + # + # SMBIOS/DMI support + # + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformDxe.= inf + INF Platform/Socionext/DeveloperBox/OsInstallerMenuDxe/OsInstallerMenuDx= e.inf =20 !if $(DO_X86EMU) =3D=3D TRUE diff --git a/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatfo= rmDxe.c b/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformD= xe.c new file mode 100644 index 000000000000..f1aec6ebdac0 --- /dev/null +++ b/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -0,0 +1,641 @@ +/** @file + This driver installs SMBIOS information for Socionext SynQuacer platforms + + Copyright (c) 2015, ARM Limited. All rights reserved. + Copyright (c) 2018, Linaro, Ltd. All rights reserved. + + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +STATIC EFI_SMBIOS_PROTOCOL *mSmbios; + +// +// Type definition and contents of the default SMBIOS table. +// This table covers only the minimum structures required by +// the SMBIOS specification (section 6.2, version 3.0) +// +#pragma pack(1) +typedef struct { + SMBIOS_TABLE_TYPE0 Base; + INT8 Strings[]; +} ARM_TYPE0; + +typedef struct { + SMBIOS_TABLE_TYPE1 Base; + UINT8 Strings[]; +} ARM_TYPE1; + +typedef struct { + SMBIOS_TABLE_TYPE2 Base; + UINT8 Strings[]; +} ARM_TYPE2; + +typedef struct { + SMBIOS_TABLE_TYPE3 Base; + UINT8 Strings[]; +} ARM_TYPE3; + +typedef struct { + SMBIOS_TABLE_TYPE4 Base; + UINT8 Strings[]; +} ARM_TYPE4; + +typedef struct { + SMBIOS_TABLE_TYPE7 Base; + UINT8 Strings[]; +} ARM_TYPE7; + +typedef struct { + SMBIOS_TABLE_TYPE9 Base; + UINT8 Strings[]; +} ARM_TYPE9; + +typedef struct { + SMBIOS_TABLE_TYPE16 Base; + UINT8 Strings[]; +} ARM_TYPE16; + +typedef struct { + SMBIOS_TABLE_TYPE17 Base; + UINT8 Strings[]; +} ARM_TYPE17; + +typedef struct { + SMBIOS_TABLE_TYPE19 Base; + UINT8 Strings[]; +} ARM_TYPE19; + +typedef struct { + SMBIOS_TABLE_TYPE32 Base; + UINT8 Strings[]; +} ARM_TYPE32; +#pragma pack() + +enum { + SMBIOS_HANDLE_A53_L1I =3D 0x1000, + SMBIOS_HANDLE_A53_L1D, + SMBIOS_HANDLE_A53_L2, + SMBIOS_HANDLE_A53_L3, + SMBIOS_HANDLE_MOTHERBOARD, + SMBIOS_HANDLE_CHASSIS, + SMBIOS_HANDLE_A53_CLUSTER, + SMBIOS_HANDLE_MEMORY, +}; + +// BIOS information (section 7.1) +STATIC CONST ARM_TYPE0 mArmDefaultType0 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_BIOS_INFORMATION, + sizeof (SMBIOS_TABLE_TYPE0), + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, // Vendor + 2, // BiosVersion + 0xE800, // BiosSegment + 3, // BiosReleaseDa= te + (FixedPcdGet32 (PcdFdSize) - SIZE_64KB) / SIZE_64KB, // BiosSize + { + 0, 0, 0, 0, 0, 0, + 1, // PCI supported + 0, + 1, // PNP supported + 0, + 1, // BIOS upgradab= le + 0, 0, 0, + 1, // Boot from CD + 1, // Selectable bo= ot + }, + { 0x3, 0xC, }, // BIOSCharacter= isticsExtensionBytes[2] + + FixedPcdGet32 (PcdFirmwareRevision) >> 16, // SystemBiosMaj= orRelease + FixedPcdGet32 (PcdFirmwareRevision) & 0xff, // SystemBiosMin= orRelease + 0xFF, // EmbeddedContr= ollerFirmwareMajorRelease + 0xFF // EmbeddedContr= ollerFirmwareMinorRelease + }, + FIRMWARE_VENDOR "\0" + BUILD_NUMBER "\0" + __DATE__ +}; + +// System information (section 7.2) +STATIC CONST ARM_TYPE1 mArmDefaultType1 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, + sizeof(SMBIOS_TABLE_TYPE1), + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, // Manufacturer + 2, // Product Name + 0, // Version + 0, // Serial + { 0xbf4ec78a, 0x431d, 0x4eb6, { 0xbb, 0xc9, 0x0c, 0x06, 0x19, 0x05, 0x= ca, 0x13 }}, + 6, // Wakeup type + 0, // SKU + 0, // Family + }, + "Socionext\0" + "SynQuacer E-series DeveloperBox" +}; + +// Enclosure +STATIC CONST ARM_TYPE3 mArmDefaultType3 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, + sizeof (SMBIOS_TABLE_TYPE3), + SMBIOS_HANDLE_CHASSIS, + }, + 1, // Manufacturer + 4, // Enclosure type (low profile desktop) + 2, // Version + 0, // Serial + 0, // Asset tag + ChassisStateUnknown, // boot chassis state + ChassisStateSafe, // power supply state + ChassisStateSafe, // thermal state + ChassisSecurityStatusNone, // security state + { 0, 0, 0, 0 }, // OEM defined + 1, // 1U height + 1, // number of power cords + 0, // no contained elements + }, { + "InWin\0" + "BK623" + } +}; + +STATIC CONST ARM_TYPE4 mArmDefaultType4 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, + sizeof (SMBIOS_TABLE_TYPE4), + SMBIOS_HANDLE_A53_CLUSTER, + }, + 0, // socket type + 3, // processor type CPU + ProcessorFamilyIndicatorFamily2, // processor family, acquire from fi= eld2 + 1, // manufacturer + {}, // processor id + 2, // version + { 0, 0, 0, 0, 0, 1 }, // voltage + 0, // external clock + 1000, // max speed + 1000, // current speed + 0x41, // status + ProcessorUpgradeNone, + SMBIOS_HANDLE_A53_L1I, // l1 cache handle + SMBIOS_HANDLE_A53_L2, // l2 cache handle + SMBIOS_HANDLE_A53_L3, // l3 cache handle + 0, // serial not set + 0, // asset not set + 3, // part number + 24, // core count in socket + 24, // enabled core count in socket + 1, // threads per socket + 0xEC, // processor characteristics + ProcessorFamilyARM, // ARM core + }, + "ARM Ltd.\0" + "Cortex-A53\0" + "0xd03" +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_l1i =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, + sizeof (SMBIOS_TABLE_TYPE7), + SMBIOS_HANDLE_A53_L1I, + }, + 1, + 0x380, // L1 enabled + 32, // 32k i cache max + 32, // 32k installed + { 0, 1 }, // SRAM type + { 0, 1 }, // SRAM type + 0, // unknown speed + CacheErrorParity, + CacheTypeInstruction, + CacheAssociativity2Way, + }, + "L1 Instruction" +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_l1d =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, + sizeof (SMBIOS_TABLE_TYPE7), + SMBIOS_HANDLE_A53_L1D, + }, + 1, + 0x180, // L1 enabled, WB + 32, // 32k d cache max + 32, // 32k installed + { 0, 1 }, // SRAM type + { 0, 1 }, // SRAM type + 0, // unknown speed + CacheErrorSingleBit, + CacheTypeData, + CacheAssociativity4Way, + }, + "L1 Data" +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_l2 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, + sizeof (SMBIOS_TABLE_TYPE7), + SMBIOS_HANDLE_A53_L2, + }, + 1, + 0x181, // L2 enabled, WB + 256, // 256 KB cache max + 256, // 256 KB installed + { 0, 1 }, // SRAM type + { 0, 1 }, // SRAM type + 0, // unknown speed + CacheErrorSingleBit, + CacheTypeUnified, + CacheAssociativity16Way, + }, + "L2" +}; + +STATIC CONST ARM_TYPE7 mArmDefaultType7_l3 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_CACHE_INFORMATION, + sizeof (SMBIOS_TABLE_TYPE7), + SMBIOS_HANDLE_A53_L3, + }, + 1, + 0x182, // L3 enabled, WB + 4096, // 4M cache max + 4096, // 4M installed + { 0, 1 }, // SRAM type + { 0, 1 }, // SRAM type + 0, // unknown speed + CacheErrorSingleBit, + CacheTypeUnified, + CacheAssociativityUnknown, + }, + "L3" +}; + +// Slots +STATIC CONST ARM_TYPE9 mArmDefaultType9_0 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, + sizeof (SMBIOS_TABLE_TYPE9), + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, + SlotTypePciExpressGen2X16, + SlotDataBusWidth4X, + SlotUsageUnknown, + SlotLengthLong, + 0, + { 1 }, + {}, + 1, + 0, + 0, + }, + "J-PCIEX16" +}; + +STATIC CONST ARM_TYPE9 mArmDefaultType9_1 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, + sizeof (SMBIOS_TABLE_TYPE9), + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, + SlotTypePciExpressGen2X1, + SlotDataBusWidth1X, + SlotUsageUnknown, + SlotLengthShort, + 0, + { 1 }, + {}, + 0, + 1, + 3, + }, + "J-PCIE1" +}; + +STATIC CONST ARM_TYPE9 mArmDefaultType9_2 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, + sizeof (SMBIOS_TABLE_TYPE9), + SMBIOS_HANDLE_PI_RESERVED, + }, + 1, + SlotTypePciExpressGen2X1, + SlotDataBusWidth1X, + SlotUsageUnknown, + SlotLengthShort, + 0, + { 1 }, + {}, + 0, + 1, + 7, + }, + "J-PCIE2" +}; + +// Memory array +STATIC CONST ARM_TYPE16 mArmDefaultType16 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, + sizeof (SMBIOS_TABLE_TYPE16), + SMBIOS_HANDLE_MEMORY, + }, + MemoryArrayLocationSystemBoard, // on motherboard + MemoryArrayUseSystemMemory, // system RAM + MemoryErrorCorrectionNone, + 0x4000000, // max 64 GB + 0xFFFE, // No error information structure + 0x1, // soldered memory + }, { + } +}; + +// Memory device +STATIC CONST ARM_TYPE17 mArmDefaultType17_1 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, + sizeof (SMBIOS_TABLE_TYPE17), + SMBIOS_HANDLE_PI_RESERVED, + }, + SMBIOS_HANDLE_MEMORY, // array to which this module belongs + 0xFFFE, // no errors + 72, // single DIMM with ECC + 64, // data width of this device (64-bits) + 0xFFFF, // size unknown + 0x09, // DIMM + 1, // part of a set + 1, // device locator + 0, // bank locator + MemoryTypeDdr4, // DDR4 + {}, // type detail + 0, // ? MHz + 0, // manufacturer + 0, // serial + 0, // asset tag + 0, // part number + 0, // rank + }, { + "DIMM1" + } +}; + +STATIC CONST ARM_TYPE17 mArmDefaultType17_2 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, + sizeof (SMBIOS_TABLE_TYPE17), + SMBIOS_HANDLE_PI_RESERVED, + }, + SMBIOS_HANDLE_MEMORY, // array to which this module belongs + 0xFFFE, // no errors + 72, // single DIMM with ECC + 64, // data width of this device (64-bits) + 0xFFFF, // size unknown + 0x09, // DIMM + 1, // part of a set + 1, // device locator + 0, // bank locator + MemoryTypeDdr4, // DDR4 + {}, // type detail + 0, // ? MHz + 0, // manufacturer + 0, // serial + 0, // asset tag + 0, // part number + 0, // rank + }, { + "DIMM2" + } +}; + +STATIC CONST ARM_TYPE17 mArmDefaultType17_3 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, + sizeof (SMBIOS_TABLE_TYPE17), + SMBIOS_HANDLE_PI_RESERVED, + }, + SMBIOS_HANDLE_MEMORY, // array to which this module belongs + 0xFFFE, // no errors + 72, // single DIMM with ECC + 64, // data width of this device (64-bits) + 0xFFFF, // size unknown + 0x09, // DIMM + 1, // part of a set + 1, // device locator + 0, // bank locator + MemoryTypeDdr4, // DDR4 + {}, // type detail + 0, // ? MHz + 0, // manufacturer + 0, // serial + 0, // asset tag + 0, // part number + 0, // rank + }, { + "DIMM3" + } +}; + +STATIC CONST ARM_TYPE17 mArmDefaultType17_4 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_DEVICE, + sizeof (SMBIOS_TABLE_TYPE17), + SMBIOS_HANDLE_PI_RESERVED, + }, + SMBIOS_HANDLE_MEMORY, // array to which this module belongs + 0xFFFE, // no errors + 72, // single DIMM with ECC + 64, // data width of this device (64-bits) + 0xFFFF, // size unknown + 0x09, // DIMM + 1, // part of a set + 1, // device locator + 0, // bank locator + MemoryTypeDdr4, // DDR4 + {}, // type detail + 0, // ? MHz + 0, // manufacturer + 0, // serial + 0, // asset tag + 0, // part number + 0, // rank + }, { + "DIMM4" + } +}; + +// Memory array mapped address, this structure +// is overridden by InstallMemoryStructure +STATIC CONST ARM_TYPE19 mArmDefaultType19 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, + sizeof (SMBIOS_TABLE_TYPE19), + SMBIOS_HANDLE_PI_RESERVED, + }, + 0xFFFFFFFF, // invalid, look at extended addr field + 0xFFFFFFFF, + SMBIOS_HANDLE_MEMORY, // handle + 1, + 0x0, + 0x0, + }, { + } +}; + +// System boot info +STATIC CONST ARM_TYPE32 mArmDefaultType32 =3D { + { + { // SMBIOS_STRUCTURE Hdr + EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, + sizeof (SMBIOS_TABLE_TYPE32), + SMBIOS_HANDLE_PI_RESERVED, + }, + {}, + BootInformationStatusNoError, + }, { + } +}; + +STATIC CONST VOID * CONST FixedTables[] =3D { + &mArmDefaultType0, + &mArmDefaultType1, + &mArmDefaultType3, + &mArmDefaultType7_l1i, + &mArmDefaultType7_l1d, + &mArmDefaultType7_l2, + &mArmDefaultType7_l3, + &mArmDefaultType4, + &mArmDefaultType9_0, + &mArmDefaultType9_1, + &mArmDefaultType9_2, + &mArmDefaultType16, + &mArmDefaultType17_1, + &mArmDefaultType17_2, + &mArmDefaultType17_3, + &mArmDefaultType17_4, + &mArmDefaultType32, +}; + +STATIC +EFI_STATUS +InstallMemoryStructure ( + IN UINT64 StartingAddress, + IN UINT64 RegionLength + ) +{ + EFI_SMBIOS_HANDLE SmbiosHandle; + ARM_TYPE19 MemoryDescriptor; + + CopyMem (&MemoryDescriptor, &mArmDefaultType19, sizeof (mArmDefaultType1= 9)); + + MemoryDescriptor.Base.ExtendedStartingAddress =3D StartingAddress; + MemoryDescriptor.Base.ExtendedEndingAddress =3D StartingAddress + Region= Length; + SmbiosHandle =3D MemoryDescriptor.Base.Hdr.Handle; + + return mSmbios->Add (mSmbios, NULL, &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER*) &MemoryDescriptor); +} + +STATIC +VOID +InstallAllStructures ( + VOID + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_HANDLE SmbiosHandle; + UINTN Idx; + EFI_PEI_HOB_POINTERS Hob; + + for (Idx =3D 0; Idx < ARRAY_SIZE (FixedTables); Idx++) { + SmbiosHandle =3D ((EFI_SMBIOS_TABLE_HEADER *)FixedTables[Idx])->Handle; + Status =3D mSmbios->Add (mSmbios, NULL, &SmbiosHandle, + (EFI_SMBIOS_TABLE_HEADER*) FixedTables[Idx]); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to add SMBIOS table - %r\n", + __FUNCTION__, Status)); + break; + } + } + + for (Hob.Raw =3D GetHobList (); + !END_OF_HOB_LIST (Hob); + Hob.Raw =3D GET_NEXT_HOB (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR && + Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM_ME= MORY) { + Status =3D InstallMemoryStructure (Hob.ResourceDescriptor->PhysicalS= tart, + Hob.ResourceDescriptor->ResourceLen= gth); + ASSERT_EFI_ERROR (Status); + } + } +} + +/** + Installs SMBIOS information for SynQuacer platform + + @param ImageHandle Module's image handle + @param SystemTable Pointer of EFI_SYSTEM_TABLE + + @retval EFI_SUCCESS Smbios data successfully installed + @retval Other Smbios data was not installed + +**/ +EFI_STATUS +EFIAPI +SmbiosPlatformDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status =3D gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, + (VOID **)&mSmbios); + ASSERT_EFI_ERROR (Status); + + InstallAllStructures (); + + return EFI_SUCCESS; +} diff --git a/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatfo= rmDxe.inf b/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatfor= mDxe.inf new file mode 100644 index 000000000000..4bb5acdfa386 --- /dev/null +++ b/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformDxe.i= nf @@ -0,0 +1,47 @@ +## @file +# +# Copyright (c) 2018, Linaro, Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SmbiosPlatformDxe + FILE_GUID =3D 449c91b9-0907-49b5-aa76-04af3097401c + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmbiosPlatformDxeEntryPoint + +[Sources] + SmbiosPlatformDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseMemoryLib + BaseLib + DebugLib + HobLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED + +[Depex] + gEfiSmbiosProtocolGuid --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel