From nobody Thu Apr 18 15:36:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1527237951107123.64155344145433; Fri, 25 May 2018 01:45:51 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D2F67207E5401; Fri, 25 May 2018 01:45:49 -0700 (PDT) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A74D5207E4E10 for ; Fri, 25 May 2018 01:45:48 -0700 (PDT) Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 May 2018 01:45:48 -0700 Received: from ray-dev.ccr.corp.intel.com ([10.239.9.4]) by orsmga006.jf.intel.com with ESMTP; 25 May 2018 01:45:47 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.136; helo=mga12.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,439,1520924400"; d="scan'208";a="44656276" From: Ruiyu Ni To: edk2-devel@lists.01.org Date: Fri, 25 May 2018 16:45:56 +0800 Message-Id: <20180525084556.305832-1-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.16.1.windows.1 Subject: [edk2] [PATCH] PcAtChipsetPkg/PcRtc: Add two new PCD for RTC Index/Target registers X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In certain HW implementation, the BIT7 of RTC Index register(0x70) is for NMI sources enable/disable but the BIT7 of 0x70 cannot be read before writing. Software which doesn't want to change the NMI sources enable/disable setting can write to the alias register 0x74, through which only BIT0 ~ BIT6 of 0x70 is modified. So two new PCDs are added so that platform can have the flexibility to change the default RTC register addresses from 0x70/0x71 to 0x74/0x75. With the new PCDs added, it can also support special HW that provides RTC storage in a different register pairs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Star Zeng --- PcAtChipsetPkg/PcAtChipsetPkg.dec | 10 ++++++= +++- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c | 10 +++++-= ---- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h | 5 +---- .../PcatRealTimeClockRuntimeDxe.inf | 4 +++- 4 files changed, 18 insertions(+), 11 deletions(-) diff --git a/PcAtChipsetPkg/PcAtChipsetPkg.dec b/PcAtChipsetPkg/PcAtChipset= Pkg.dec index f11d2045a4..ace7fb7e88 100644 --- a/PcAtChipsetPkg/PcAtChipsetPkg.dec +++ b/PcAtChipsetPkg/PcAtChipsetPkg.dec @@ -4,7 +4,7 @@ # This package is designed to public interfaces and implementation which f= ollows # PcAt defacto standard. # -# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Inc. All rights reserved.
# # This program and the accompanying materials @@ -194,5 +194,13 @@ [PcdsFixedAtBuild, PcdsPatchableInModule] # @Prompt Initial value for Register_D in RTC. gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x00|UINT8|0x0= 000001D =20 + ## Specifies RTC Index Register address in I/O space. + # @Prompt RTC Index Register address + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x70|UINT8|0x0000001E + + ## Specifies RTC Target Register address in I/O space. + # @Prompt RTC Target Register address + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x71|UINT8|0x0000001F + [UserExtensions.TianoCore."ExtraFiles"] PcAtChipsetPkgExtra.uni diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c b/PcAtChips= etPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c index c032e16217..caecd0ac1e 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c @@ -1,7 +1,7 @@ /** @file RTC Architectural Protocol GUID as defined in DxeCis 0.96. =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Inc. All rights reserved.
=20 This program and the accompanying materials @@ -72,8 +72,8 @@ RtcRead ( IN UINT8 Address ) { - IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8) (Address | (UINT8) (IoRead8= (PCAT_RTC_ADDRESS_REGISTER) & 0x80))); - return IoRead8 (PCAT_RTC_DATA_REGISTER); + IoWrite8 (PcdGet8 (PcdRtcIndexRegister), (UINT8) (Address | (UINT8) (IoR= ead8 (PcdGet8 (PcdRtcIndexRegister)) & 0x80))); + return IoRead8 (PcdGet8 (PcdRtcTargetRegister)); } =20 /** @@ -90,8 +90,8 @@ RtcWrite ( IN UINT8 Data ) { - IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8) (Address | (UINT8) (IoRead8= (PCAT_RTC_ADDRESS_REGISTER) & 0x80))); - IoWrite8 (PCAT_RTC_DATA_REGISTER, Data); + IoWrite8 (PcdGet8 (PcdRtcIndexRegister), (UINT8) (Address | (UINT8) (IoR= ead8 (PcdGet8 (PcdRtcIndexRegister)) & 0x80))); + IoWrite8 (PcdGet8 (PcdRtcTargetRegister), Data); } =20 /** diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h b/PcAtChips= etPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h index 8aeb12c88a..3b68f8cc9e 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h @@ -1,7 +1,7 @@ /** @file Header file for real time clock driver. =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Inc. All rights reserved.
=20 This program and the accompanying materials @@ -47,9 +47,6 @@ typedef struct { =20 extern PC_RTC_MODULE_GLOBALS mModuleGlobal; =20 -#define PCAT_RTC_ADDRESS_REGISTER 0x70 -#define PCAT_RTC_DATA_REGISTER 0x71 - // // Dallas DS12C887 Real Time Clock // diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRu= ntimeDxe.inf b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClock= RuntimeDxe.inf index 1b2b063623..4d1360744d 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDx= e.inf +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDx= e.inf @@ -4,7 +4,7 @@ # This driver provides GetTime, SetTime, GetWakeupTime, SetWakeupTime serv= ices to Runtime Service Table. # It will install a tagging protocol with gEfiRealTimeClockArchProtocolGui= d. # -# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Inc. All rights reserved.
# # This program and the accompanying materials @@ -77,6 +77,8 @@ [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout ## CONSUMES gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear ## CONSUMES gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear ## CONSUMES + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister ## CONSUMES + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister ## CONSUMES =20 [Depex] gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid --=20 2.16.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel