From nobody Sun May 5 23:09:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1527704380209584.6743463764134; Wed, 30 May 2018 11:19:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A2981210C998E; Wed, 30 May 2018 11:19:38 -0700 (PDT) Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1AEBE210C997A for ; Wed, 30 May 2018 11:19:37 -0700 (PDT) Received: by mail-wr0-x243.google.com with SMTP id i12-v6so30496480wrc.4 for ; Wed, 30 May 2018 11:19:36 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id b105-v6sm48315705wrd.64.2018.05.30.11.19.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 May 2018 11:19:34 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::243; helo=mail-wr0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RNOHp2TbxVLH+DSFojfAFSFGNlt0bp2vpVXkOF7Ryzc=; b=dvsDysyT6UTseVQ853f0Oo+JTyKhNRbxXAqdBa/NmbszfeH7uaJdazTvmL0pOWVoOL nHuoXdv0BYLiIDkqliPQ7V/ecbuvNzGTSDF9mTXFmxjeMTjXAlCwDLbJQzzZCjed5jN5 2dEixtjNZGp/nUMGfGDBJVlJ/MYo13IajO0Bc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RNOHp2TbxVLH+DSFojfAFSFGNlt0bp2vpVXkOF7Ryzc=; b=ns1jsUWL4ZVHzE0GQ7uJseCJvlVIXkJVXY6Irf82TnUE9nMqSzKWbTC3JG3mpFMsYq Es+StDfiI1UXV5YU/r/x/pZeorAD2k2xEt8LyKCXKTFGO5gYWbwd7/r22LB4QIVC66FK kS3WsgNOPG6UkG3awup1VzDZkTUMmn1tNGxk/EkUoI6nTWJ3QxLpYTFbZVniL66Lucyo oPjt7K6/MC4r6PPCMU2QU+jRU0QOlZPwd61I+4h7cX2d2Ar60LfNviAHySUSHKOxXP8k BUZdseAPAeivR3LVvAt+U4Qh41cN6Jgy7IXWDg9ESPeNKqDhQ7oy7IWYwztke8q0BYBE Vygg== X-Gm-Message-State: ALKqPwdYpwHxR+E32WxGSdmYSw+pS9Y2NTGYzsdf1zzyWr4NcEGTkcqb wQ8xtWD2ccvkB+opt9XeYjW9ptl225s= X-Google-Smtp-Source: ADUXVKIqx9kRM/56Hf3xI2er+UOcJySKFZCoEJ5yjL+2RB1/LG6BE5ll7rRhamJCTBBl6RHvPblR8Q== X-Received: by 2002:adf:9f4a:: with SMTP id f10-v6mr2895278wrg.216.1527704375304; Wed, 30 May 2018 11:19:35 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 30 May 2018 20:19:27 +0200 Message-Id: <20180530181929.5066-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530181929.5066-1-ard.biesheuvel@linaro.org> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/3] Silicon/SynQuacerPciHostBridgeLib: add workaround for PCIe MMIO64 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Masahisa KOJIMA The current revision of SC2A11 contains PCIe bus issue. In MRd transaction, 1st/Last DW BE fields are not correctly set by hardware. As a workaround, set TH bit and specify MSG_CODE in iATU. With this setup, the value specified as MSG_CODE is set to the 1st/Last DW BE fields and PCIe controller can emit the correct MRd TLP header. Same workaround was already included for MMIO32 region, MMIO64 region also requires this workaround. Some deivices, such as Samsong SSD 970 EVO, do not work without this modification. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Masahisa KOJIMA Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPci= HostBridgeLibConstructor.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/= SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Librar= y/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index e4679543cc66..227f9a725ce8 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuac= erPciHostBridgeLibConstructor.c @@ -359,8 +359,9 @@ PciInitControllerPost ( RootBridge->MemAbove4G.Base, RootBridge->MemAbove4G.Base, RootBridge->MemAbove4G.Limit - RootBridge->MemAbove4G.Base + 1, - IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, - 0); + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TH, + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_MSG_CODE_32BIT); } =20 // enable link --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 23:09:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1527704383958929.4383821516805; Wed, 30 May 2018 11:19:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CE5D5210C9994; Wed, 30 May 2018 11:19:39 -0700 (PDT) Received: from mail-wm0-x233.google.com (mail-wm0-x233.google.com [IPv6:2a00:1450:400c:c09::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8ED9F210C9985 for ; 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Wed, 30 May 2018 11:19:36 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 30 May 2018 20:19:28 +0200 Message-Id: <20180530181929.5066-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530181929.5066-1-ard.biesheuvel@linaro.org> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/3] Silicon/Socionext/SynQuacer/Stage2Tables: add north SMMU level 3 table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Extend the static stage 2 page tables with a set of level 3 tables that describe the ECAM space in a manner that allows the north SMMU to be used to make the ECAM space appear sane to the CPUs. It is up to the secure firmware to manipulate the north SMMU page tables so that the level 2 block entries corresponding with busses #0 .. #1 in the respective config spaces of PCI0 and PCI1 are replaced with table entries pointing to the level 3 tables added by this patch. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S | 35 +++++++++++++= ++----- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S b/Sili= con/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S index 313ef3c56abc..af55f27bca47 100644 --- a/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S +++ b/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables.S @@ -20,15 +20,17 @@ * the SoC. */ =20 -#define TT_S2_CONT_SHIFT 52 -#define TT_S2_AF (0x1 << 10) -#define TT_S2_SH_NON_SHAREABLE (0x0 << 8) -#define TT_S2_AP_RW (0x3 << 6) -#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2) -#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2) -#define TT_S2_TABLE (0x3 << 0) -#define TT_S2_L3_PAGE (0x1 << 1) -#define TT_S2_VALID (0x1 << 0) +#define TT_S2_CONT_SHIFT 52 +#define TT_S2_AF (0x1 << 10) +#define TT_S2_SH_NON_SHAREABLE (0x0 << 8) +#define TT_S2_AP_RO (0x1 << 6) +#define TT_S2_AP_RW (0x3 << 6) +#define TT_S2_MEMATTR_DEVICE_nGRE (0x2 << 2) +#define TT_S2_MEMATTR_DEVICE_nGnRE (0x1 << 2) +#define TT_S2_MEMATTR_MEMORY_WB (0xf << 2) +#define TT_S2_TABLE (0x3 << 0) +#define TT_S2_L3_PAGE (0x1 << 1) +#define TT_S2_VALID (0x1 << 0) =20 .altmacro .macro for, start, count, do, arg2, arg3, arg4 @@ -58,6 +60,12 @@ TT_S2_L3_PAGE | TT_S2_VALID | (\cont << TT_S2_CONT_SHIFT) .endm =20 + .macro smmu_l3_entry, base, offset=3D0, ignore=3D0 + .quad ((\base << 12) + \offset) | TT_S2_AF | TT_S2_AP_RO | \ + TT_S2_SH_NON_SHAREABLE | TT_S2_MEMATTR_DEVICE_nGnRE | \ + TT_S2_L3_PAGE | TT_S2_VALID + .endm + .section ".rodata", "a", %progbits /* level 1 */ s2_mem_entry 0 /* 0x0000_0000 - 0x3fff_ffff */ @@ -86,3 +94,12 @@ 3:for 0, 8, s2_l3_entry, 0x70000000 for 0, 8, s2_l3_entry, 0x70010000 /* hide device #1 */ for 0, 496, s2_l3_entry, 0x70010000, 1 + + /* level 3 for north SMMU */ + .org 0x6000 + for 0, 8, smmu_l3_entry, 0xc00060000000 + for 0, 8, smmu_l3_entry, 0xc00060010000 /* hide device #1 */ + for 0, 496, smmu_l3_entry, 0xc00060010000 + for 0, 8, smmu_l3_entry, 0x800070000000 + for 0, 8, smmu_l3_entry, 0x800070010000 /* hide device #1 */ + for 0, 496, smmu_l3_entry, 0x800070010000 --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 23:09:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=fgYoYKWoshTorOCl2oPSlXJYjjZylJuB8SbfjrHR4GQ=; b=DgFltTx6ICWNoHgF8AoCHWc+RgpIvFmXY29OxKkbzfQT0zJnD3Meh4OjVbuLRm3Shu xCVZiluaifTUA6D1GyUvWAb5LiVnXIjmBbDQE/1bPFRGy+2f+3fddgIDaBMwodXRUz1Q cw62fXUyEqaqWXvQNcTX8aLGlCNZWnb0gxokNTvhV83tlcwh5X3+UwKmTASWMYWw/Vpr piG05yG1d5SLPse7T3ucq4N9+IJrsl83SUWJ7P/HUL3PNu9bKZG21cwCs5KeqyTH+3a6 tLxakq8rN3K5zLrehAA3A6eh+OqOcZKHfokmf+ESAkf4kzeIVgIui3Gy/wccl9/CXwac 8QHQ== X-Gm-Message-State: ALKqPwe3taOoj2WUkH0DRR7/nis4HCMXrrBmRGsqyldYOIbR8YXVKtBH lce2ffo754s35RbCDVxaHpwWDbo8zSs= X-Google-Smtp-Source: ADUXVKKPxLlsaFSLEizXahqgI9SsnkpFNoPCne5SWLoDAeBbBkvnJzoD4BhI2n2c88rnbOxOlTe8ZA== X-Received: by 2002:a1c:17c9:: with SMTP id 192-v6mr2103620wmx.95.1527704378347; Wed, 30 May 2018 11:19:38 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 30 May 2018 20:19:29 +0200 Message-Id: <20180530181929.5066-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180530181929.5066-1-ard.biesheuvel@linaro.org> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 3/3] Silicon/SynQuacer/AcpiTables: add NETSEC/eMMC SMMU to the IORT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a description of the SMMU that sits in front of the NETSEC and eMMC controllers to the IORT table so that ACPI based OSes can utilize it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 109 +++++++++++++++++++- 1 file changed, 107 insertions(+), 2 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc b/Silicon/Soc= ionext/SynQuacer/AcpiTables/Iort.aslc index 92c485f8006f..3f2aaa3d8858 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc @@ -13,6 +13,7 @@ **/ =20 #include +#include =20 #include "AcpiTables.h" =20 @@ -29,10 +30,23 @@ typedef struct { EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; } SYNQUACER_RC_NODE; =20 +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node; + EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[8]; +} SYNQUACER_SMMU_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node; + CONST CHAR8 Name[11]; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; +} SYNQUACER_NC_NODE; + typedef struct { EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; SYNQUACER_ITS_NODE ItsNode; SYNQUACER_RC_NODE RcNode[2]; + SYNQUACER_SMMU_NODE SmmuNode; + SYNQUACER_NC_NODE NamedCompNode[2]; } SYNQUACER_IO_REMAPPING_STRUCTURE; =20 #define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags) \ @@ -49,7 +63,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort =3D { __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, SYNQUACER_IO_REMAPPING_STRUCTURE, EFI_ACPI_IO_REMAPPING_TABLE_REVISION), - 3, // NumNodes + 6, // NumNodes sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset 0 // Reserved }, { @@ -94,7 +108,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort =3D { // __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE), - }, { + }, { // PciRcNode { { @@ -121,6 +135,97 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort =3D { __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE), } + }, { + // NETSEC/eMMC SMMU node + { + { + EFI_ACPI_IORT_TYPE_SMMUv1v2, + sizeof(SYNQUACER_SMMU_NODE), + 0x0, + 0x0, + 0x0, + 0x0, + }, + SYNQUACER_SCB_SMMU_BASE, + SYNQUACER_SCB_SMMU_SIZE, + EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500, + EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, + FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, + SMMU_NSgIrpt), + 0x8, + sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), + 0x0, + 0x0, + 228, + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, + 0x0, + 0x0, + }, { + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, + }, + }, { + { + // NETSEC named component node + { + { + EFI_ACPI_IORT_TYPE_NAMED_COMP, + sizeof(SYNQUACER_NC_NODE), + 0x0, + 0x0, + 0x1, + FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping), + }, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + 0x0, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, + 40, + }, { + "\\_SB_.NET0" + }, { + 0x0, + 0x0, + 0x0, + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode), + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE + } + }, { + // eMMC named component node + { + { + EFI_ACPI_IORT_TYPE_NAMED_COMP, + sizeof(SYNQUACER_NC_NODE), + 0x0, + 0x0, + 0x1, + FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping), + }, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + 0x0, + 0x0, + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, + 40, + }, { + "\\_SB_.MMC0" + }, { + 0x0, + 0x0, + 0x0, + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode), + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE + } + } } }; =20 --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel