From nobody Sat Apr 27 09:44:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529568803802953.7916366844448; Thu, 21 Jun 2018 01:13:23 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CA6BA211DB43F; Thu, 21 Jun 2018 01:13:22 -0700 (PDT) Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D3EF8211C8302 for ; Thu, 21 Jun 2018 01:13:21 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id f16-v6so2162696wrm.3 for ; Thu, 21 Jun 2018 01:13:21 -0700 (PDT) Received: from dogfood.home ([2a01:cb1d:112:6f00:104b:ef1a:8c01:a5bb]) by smtp.gmail.com with ESMTPSA id q17-v6sm4803152wro.30.2018.06.21.01.13.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Jun 2018 01:13:18 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=R+Lo6Atv3Y/KMTl59+QeCsQFql15WuO17UHq1O9S9gw=; b=kwCvtReEylkLl5OyguPSlUeLkPTT7iJDDXiJhlHBSOfWsPX9dHY+m1KEbrYLh2CM2O jRUb5tae374DdHAElchMJaEOGllJFYSQfS6VEs5qGC90hH+A+LJUjYUdGVy/4cSeGlQJ 6t6PX0yp5JoFXwNxri6/GP2PznPDWmPLzPZIc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=R+Lo6Atv3Y/KMTl59+QeCsQFql15WuO17UHq1O9S9gw=; b=Wzwv7TC/9SRzjPYQ1ugrFPq6iuf4yBtk4Moo365cSViUjq3MsOiCuGGLjHN1QVPlKY 9kuDQpwE9nmbJ8MmHy4TXAZzSH2rO7PhpdQqDYLhNYPxWoyEB+EPz78Ld05ciOMl1f9G KT2eCJYau+rgFVoq6ykehyB6kXdO7v1tYkO54YrAQ5vy5nqO8C49AZBCuVPlvVYIGMgX upjPeF0yzPrnTV6Doxi6bY2llp+r85XnF2kGHZFG83XeIsa3jrccDlF5pzuGfjTlWkbR d/+vETOt65y8iFyO7xcr9C+M0SrfqCODlpXwXwrM+M0t7Die1FLiC1z5h36qfxVc3tSy ws6Q== X-Gm-Message-State: APt69E0luzOCoVMG6iPsWOLyFgYEXB6ePvrxczgIlvk0ZECU82sb5but OPCdHalEt1i42xEMBugF4EmOpK6UXWI= X-Google-Smtp-Source: ADUXVKLxLQBSVNGUxHBw+yVjnVro/OHOeG2s2EV6Up4OOh0YQLeoCNkTS6qArSNAI1lkXj+WOjVohw== X-Received: by 2002:a5d:4306:: with SMTP id h6-v6mr21206260wrq.58.1529568800166; Thu, 21 Jun 2018 01:13:20 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 21 Jun 2018 10:13:14 +0200 Message-Id: <20180621081315.16228-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180621081315.16228-1-ard.biesheuvel@linaro.org> References: <20180621081315.16228-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 1/2] ArmPkg/ArmMmuLib ARM: remove cache maintenance of block mapping contents X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Peculiarly enough, the current page table manipulation code takes it upon itself to write back and invalidate the memory contents covered by section mappings when their memory attributes change. It is not generally the case that data must be written back when such a change occurs, even when switching from cacheable to non-cacheable attributes, and in some cases, it is actually causing problems. (The cache maintenance is also performed on the PCIe MMIO regions as they get mapped by the PCI bus driver, and under virtualization, each cache maintenance operation on an emulated MMIO region triggers a round trip to the host and back) So let's just drop this code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/= ArmMmuLib/Arm/ArmMmuLibCore.c index 9bf4ba03fd5b..9c2578979e44 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -597,12 +597,6 @@ UpdatePageEntries ( if (CurrentPageTableEntry !=3D PageTableEntry) { Mva =3D (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SEC= TION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT)); =20 - // Clean/invalidate the cache for this page, but only - // if we are modifying the memory type attributes - if (((CurrentPageTableEntry ^ PageTableEntry) & TT_DESCRIPTOR_PAGE_C= ACHE_POLICY_MASK) !=3D 0) { - WriteBackInvalidateDataCacheRange (Mva, TT_DESCRIPTOR_PAGE_SIZE); - } - // Only need to update if we are changing the entry PageTable[PageTableIndex] =3D PageTableEntry; ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], = Mva); @@ -718,12 +712,6 @@ UpdateSectionEntries ( if (CurrentDescriptor !=3D Descriptor) { Mva =3D (VOID *)(UINTN)(((UINTN)FirstLevelIdx + i) << TT_DESCRIPTO= R_SECTION_BASE_SHIFT); =20 - // Clean/invalidate the cache for this section, but only - // if we are modifying the memory type attributes - if (((CurrentDescriptor ^ Descriptor) & TT_DESCRIPTOR_SECTION_CACH= E_POLICY_MASK) !=3D 0) { - WriteBackInvalidateDataCacheRange (Mva, SIZE_1MB); - } - // Only need to update if we are changing the descriptor FirstLevelTable[FirstLevelIdx + i] =3D Descriptor; ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLeve= lIdx + i], Mva); --=20 2.17.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat Apr 27 09:44:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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Thu, 21 Jun 2018 01:13:21 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 21 Jun 2018 10:13:15 +0200 Message-Id: <20180621081315.16228-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180621081315.16228-1-ard.biesheuvel@linaro.org> References: <20180621081315.16228-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 2/2] ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memory X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Given that these days, our ARM port only supports ARMv7 and later, we can assume that the page table walker's memory accesses are cache coherent, and so there is no need to perform cache maintenance. It does require the page tables themselves to reside in memory mapped as writeback cacheable so ASSERT() that this is the case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 2 -- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 14 +++----------- 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/Arm= Lib/Arm/ArmLibSupport.S index 149b57e059ee..f2a517671f0a 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S @@ -100,8 +100,6 @@ ASM_FUNC(ArmGetTTBR0BaseAddress) // IN VOID *MVA // R1 // ); ASM_FUNC(ArmUpdateTranslationTableEntry) - mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA - dsb mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array= . R9 =3D=3D NoOp dsb diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/= ArmMmuLib/Arm/ArmMmuLibCore.c index 9c2578979e44..3037b642d40c 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -343,17 +343,12 @@ ArmConfigureMmu ( } =20 // Translate the Memory Attributes into Translation Table Register Attri= butes - if ((TranslationTableAttribute =3D=3D ARM_MEMORY_REGION_ATTRIBUTE_UNCACH= ED_UNBUFFERED) || - (TranslationTableAttribute =3D=3D ARM_MEMORY_REGION_ATTRIBUTE_NONSEC= URE_UNCACHED_UNBUFFERED)) { - TTBRAttributes =3D ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE : TTB= R_NON_CACHEABLE; - } else if ((TranslationTableAttribute =3D=3D ARM_MEMORY_REGION_ATTRIBUTE= _WRITE_BACK) || + if ((TranslationTableAttribute =3D=3D ARM_MEMORY_REGION_ATTRIBUTE_WRITE_= BACK) || (TranslationTableAttribute =3D=3D ARM_MEMORY_REGION_ATTRIBUTE_NONSEC= URE_WRITE_BACK)) { TTBRAttributes =3D ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : = TTBR_WRITE_BACK_ALLOC; - } else if ((TranslationTableAttribute =3D=3D ARM_MEMORY_REGION_ATTRIBUTE= _WRITE_THROUGH) || - (TranslationTableAttribute =3D=3D ARM_MEMORY_REGION_ATTRIBUTE_NONSEC= URE_WRITE_THROUGH)) { - TTBRAttributes =3D ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH : TTB= R_WRITE_THROUGH; } else { - ASSERT (0); // No support has been found for the attributes of the mem= ory region that the translation table belongs to. + // Page tables must reside in memory mapped as writeback cacheable + ASSERT (0); return RETURN_UNSUPPORTED; } =20 @@ -461,9 +456,6 @@ ConvertSectionToPages ( PageTable[Index] =3D TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (In= dex << 12)) | PageDescriptor; } =20 - // Flush d-cache so descriptors make it back to uncached memory for subs= equent table walks - WriteBackInvalidateDataCacheRange ((VOID *)PageTable, TT_DESCRIPTOR_PAGE= _SIZE); - // Formulate page table entry, Domain=3D0, NS=3D0 PageTableDescriptor =3D (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGE= TABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; =20 --=20 2.17.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel