From nobody Tue Feb 10 18:38:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1531469762655929.2924877609024; Fri, 13 Jul 2018 01:16:02 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 543C820986AC7; Fri, 13 Jul 2018 01:16:02 -0700 (PDT) Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7F24420986ABC for ; Fri, 13 Jul 2018 01:16:00 -0700 (PDT) Received: by mail-pg1-x542.google.com with SMTP id m19-v6so4759810pgv.3 for ; Fri, 13 Jul 2018 01:16:00 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id e7-v6sm24400196pgc.55.2018.07.13.01.15.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Jul 2018 01:15:59 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0sRNz9lxXBn4Ds0xXco2Q9Ksha2Xik1Bw4rce6YWnMg=; b=XG6e6KbQyYAY1dYt2neo1CCSF7IFNiw1f3GKhlxmVKBfi5YV26uZZs9xzQ1HWSGhpG ytJUgOLRyEnA8ILmyHvLQaBGXbv9EW1bK1xh5qs+sVGGj3Tpns2h+3s4rnRM8cRS+AcE cuLhLRCIYSyP0wLoPcoYNQJKrNtfw2srS2Ojg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0sRNz9lxXBn4Ds0xXco2Q9Ksha2Xik1Bw4rce6YWnMg=; b=H47nr22d1AN/SG+YHJGJ4Q/frSmMyUEIb7laUy5hEyI4rKlGjea2EnPdZnn8FU4oDJ 793aWCCdV6mUkVHFwi9KWVDs2sN0lNY241hL+MXUkcym7fBJW+hVr4szjgNzCNekdocu widwLX2pXRdiAuIJVn7VtSFexlaOLpiikJXtUNWA+3mTKiwnUsdN1NKhEWx66W3aguUC 87lNtAPcIDDSZaURTKOBonFYf0ffyjwMWWBnCkW7nH207gJk7f7uz304SljNe6X2pSuv O42565OgyyXezZG3FSnEmwn08VQbTJBhchBUVRXGGpwcfB5JvtbUKsXo8rHcSvafka7n f9FA== X-Gm-Message-State: AOUpUlEifr9Z4E1wlgqwK8HLUcl1wQwyLbjBuji3g87lcP2iuvSyE3J7 RUutfx8NfstwJ3SvK3f0YKkmIw== X-Google-Smtp-Source: AAOMgpepZ2KVa4Lh1rI+eXYdUryJXeLPJpBWGA4KjlYzPytYERfDmm/a7egg2U40j7bH1lRfeQkNbA== X-Received: by 2002:a65:4888:: with SMTP id n8-v6mr5224895pgs.149.1531469760178; Fri, 13 Jul 2018 01:16:00 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 13 Jul 2018 16:15:38 +0800 Message-Id: <20180713081540.8414-5-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180713081540.8414-1-ming.huang@linaro.org> References: <20180713081540.8414-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v3 4/6] Hisilicon/D05: Add PlatformMiscDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Fix the issue of onboard Nic not work kerenl with AMD GPU and NVME SSD in board. The GPU don't support 64 MSI, so need to allocate INTx, but the default interrupt number 255 is invalid, so Change all the PCI Device interrupt number to 0. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99 ++= ++++++++++++++++++ Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47 ++= ++++++++ 4 files changed, 148 insertions(+) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index b6e1a9d98a..0e6d5912a0 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -629,6 +629,7 @@ =20 =20 Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassD= xe.inf + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf =20 # # Memory test diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 4503776d63..61e8d907f9 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -354,6 +354,7 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf =20 INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf =20 diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe= .c b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c new file mode 100644 index 0000000000..8519b7139d --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c @@ -0,0 +1,99 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include + +VOID +SetIntLine ( + ) +{ + EFI_STATUS Status; + UINTN HandleIndex; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT8 INTLine; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Fun; + + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n")); + gBS->FreePool ((VOID *)HandleBuffer); + return; + } + + for (HandleIndex =3D 0; HandleIndex < HandleCount; HandleIndex++) { + Status =3D gBS->HandleProtocol ( + HandleBuffer[HandleIndex], + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (EFI_ERROR (Status)) { + continue; + } + + INTLine =3D 0; + (VOID)PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint8, + PCI_INT_LINE_OFFSET, + 1, + &INTLine); + (VOID)PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Fun); + DEBUG ((DEBUG_INFO, "Set BDF(%x-%x-%x) IntLine to 0\n", Bus, Device,= Fun)); + } + + gBS->FreePool ((VOID *)HandleBuffer); + return; +} + +EFI_STATUS +EFIAPI +PlatformMiscDxeEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + SetIntLine, + NULL, + &gEfiEventReadyToBootGuid, + &Event + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Create event for SetIntLine, %r!\n", Status)); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe= .inf b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf new file mode 100644 index 0000000000..0b365e7a53 --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf @@ -0,0 +1,47 @@ +#/** @file +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the= BSD License +# which accompanies this distribution. The full text of the license may= be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformMiscDxe + FILE_GUID =3D a48f7a09-253f-468b-87c6-caf78baf47bb + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformMiscDxeEntry + +[Sources.common] + PlatformMiscDxe.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[Guids] + gEfiEventReadyToBootGuid + +[Protocols] + gEfiPciIoProtocolGuid + +[LibraryClasses] + BaseLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + +[Depex] + TRUE --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel