From nobody Tue Feb 10 12:43:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1532413967647362.50153440018516; Mon, 23 Jul 2018 23:32:47 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A79F6210C1232; Mon, 23 Jul 2018 23:32:46 -0700 (PDT) Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5F1E1210C122A for ; Mon, 23 Jul 2018 23:32:45 -0700 (PDT) Received: by mail-pf1-x441.google.com with SMTP id x17-v6so608173pfh.5 for ; Mon, 23 Jul 2018 23:32:45 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id e2-v6sm12086575pgo.92.2018.07.23.23.32.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 23:32:44 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::441; helo=mail-pf1-x441.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WZEtX8WRGKr3zyBinVR1fKHteo57mGdaJtx1Esed71M=; b=Csw1vQddgEVyCuO81O5F5SIDMkOpKST+wFapY6rIPEsS0/0nTfLezBa/+M6kKY2EW7 lMclBj3FYByhMgiegds3IMKdV+iEE0Sqp44MnGpHgLu+IBwjKW7W1CJ48R/S+CEhG3lR Wkr13fN4quhjxgJNH95inZ/bcjhBWLHY562s0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WZEtX8WRGKr3zyBinVR1fKHteo57mGdaJtx1Esed71M=; b=iXtmhgWcY1i7g85TlgfUcgOxwd8Dmn9vvFGiuw9jQeY4RbEnEAZgl1jnhsUxrXgPrX iBnIWIJiFecNNR+9NM0e5z6oexaQ1sSC9ZwhwH5sJ5qlgJ03hZcWK5SdCCGeFYR5mW5I erdJIFdjHyELhbJj1LBgRyZroOOCYunAMrLfW1pPdZi3x8o9l+/QP+SW5Dx+U3rgbJnH 9s4fhByWoSNwn5kEJ9LVe3+rroXn+u0mfBOBFzWvNSRNC2935gSny6HVrtVonD3ki+HX Eh7kMzfLlFfuefBm0Xlq7d7XQOPCrDmPN9qDZ9OJMfqqE+KTniRjGlgqyCHjOQgp3yVD 6lcw== X-Gm-Message-State: AOUpUlGT+GCAXH2Lk2LW0WZAhVDlUDzrTUalrUZwyeispZI4gpw/rSGe mwjb2nS23E36PgnkMIBUW0CaZQ== X-Google-Smtp-Source: AAOMgpe8Llen0Jfik3c7xgRbgvAPODOUj7kJJhUszo2Q/izzWpYhS0s/Tu7x6iZEXm76jFNeIXvmiw== X-Received: by 2002:a63:81c3:: with SMTP id t186-v6mr15392106pgd.413.1532413964991; Mon, 23 Jul 2018 23:32:44 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Tue, 24 Jul 2018 14:32:13 +0800 Message-Id: <20180724063220.61679-6-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180724063220.61679-1-ming.huang@linaro.org> References: <20180724063220.61679-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 05/12] Hisilicon/Pci: move ATU configuration to PciPlatformLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Michael D Kinney , huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" we move all platform specific code to platform specific module, not in PciHostBridge driver. This is to prepare for switching to generic PciHostBridge driver, so This patch add Hi161xPciPlatformLib and moves ATU initialization to Hi161xPciPlatformLib and add api PciInitPlatform for PciPlatform driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Signed-off-by: Ming Huang Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c = | 107 ----------- Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib= .c | 185 ++++++++++++++++++++ Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib= .inf | 42 +++++ 3 files changed, 227 insertions(+), 107 deletions(-) diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b= /Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 3f894e8eec..273a322ee4 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -633,112 +633,6 @@ UINT64 GetPcieCfgAddress ( } =20 =20 -void SetAtuConfig0RW ( - PCI_ROOT_BRIDGE_INSTANCE *Private, - UINT32 Index - ) -{ - UINTN RbPciBase =3D Private->RbPciBar; - UINT64 MemLimit =3D GetPcieCfgAddress (Private->Ecam, Private->BusBase= + 1, 1, 0, 0) - 1; - UINT64 Cfg0Base =3D GetPcieCfgAddress (Private->Ecam, Private->BusBase= , 0, 0, 0); - - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(= Cfg0Base)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)= (Cfg0Base >> 32)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32= ) MemLimit); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_T= YPE_CONFIG0); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_M= ODE); - - { - UINTN i; - for (i=3D0; i<0x20; i+=3D4) { - DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=3D%p value=3D%x\n", __FUNCTIO= N__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); - } - } -} - -void SetAtuConfig1RW ( - PCI_ROOT_BRIDGE_INSTANCE *Private, - UINT32 Index - ) -{ - UINTN RbPciBase =3D Private->RbPciBar; - UINT64 MemLimit =3D GetPcieCfgAddress (Private->Ecam, Private->BusLimi= t, 0x1F, 0x07, 0xFFF); - UINT64 Cfg1Base =3D GetPcieCfgAddress (Private->Ecam, Private->BusBase= + 2, 0, 0, 0); - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_T= YPE_CONFIG1); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(= Cfg1Base)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)= (Cfg1Base >> 32)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32= ) MemLimit); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_M= ODE); - - { - UINTN i; - for (i=3D0; i<0x20; i+=3D4) { - DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=3D%p value=3D%x\n", __FUNCTIO= N__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); - } - } -} - -void SetAtuIoRW(UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UI= NT64 CpuIoRegionBase, UINT32 Index) -{ - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_T= YPE_IO); - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(= CpuIoRegionBase)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)= ((UINT64)CpuIoRegionBase >> 32)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32= )(CpuIoRegionLimit)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32= )(IoBase)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT3= 2)((UINT64)(IoBase) >> 32)); - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_= MODE); - - { - UINTN i; - for (i=3D0; i<0x20; i+=3D4) { - DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=3D%p value=3D%x\n", __FUNCTIO= N__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); - } - } -} - -void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit,= UINT64 CpuMemRegionBase, UINT32 Index) -{ - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_T= YPE_MEM); - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(= CpuMemRegionBase)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)= ((UINT64)(CpuMemRegionBase) >> 32)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32= )(CpuMemRegionLimit)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32= )(MemBase)); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT3= 2)((UINT64)(MemBase) >> 32)); - - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_= MODE); - - { - UINTN i; - for (i=3D0; i<0x20; i+=3D4) { - DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=3D%p value=3D%x\n", __FUNCTIO= N__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); - } - } -} - -VOID InitAtu (PCI_ROOT_BRIDGE_INSTANCE *Private) -{ - SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegi= onLimit, Private->CpuMemRegionBase, 0); - SetAtuConfig0RW (Private, 1); - SetAtuConfig1RW (Private, 2); - SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Privat= e->CpuIoRegionBase, 3); -} - - BOOLEAN PcieIsLinkUp (UINT32 SocType, UINTN RbPciBar, UINTN Port) { UINT32 Value =3D 0; @@ -861,7 +755,6 @@ RootBridgeConstructor ( =20 Protocol->SegmentNumber =3D Seg; =20 - InitAtu (PrivateData); =20 Status =3D gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (V= OID **)&mMetronome); if (EFI_ERROR(Status)) diff --git a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPc= iPlatformLib.c b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi16= 1xPciPlatformLib.c new file mode 100644 index 0000000000..de26259778 --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatfo= rmLib.c @@ -0,0 +1,185 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +STATIC +UINT64 +GetPcieCfgAddress ( + UINT64 Ecam, + UINTN Bus, + UINTN Device, + UINTN Function, + UINTN Reg + ) +{ + return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg); +} + +STATIC +VOID +SetAtuConfig0RW ( + PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private, + UINT32 Index + ) +{ + UINTN RbPciBase =3D Private->RbPciBar; + UINT64 MemLimit =3D GetPcieCfgAddress (Private->Ecam, Private->BusBase += 1, 1, 0, 0) - 1; + UINT64 MemBase =3D GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0= , 0, 0); + + + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)Mem= Base); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(M= emBase >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) = MemLimit); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYP= E_CONFIG0); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MOD= E); + + { + UINTN i; + for (i=3D0; i<0x20; i+=3D4) { + DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=3D%p value=3D%x\n", __FUNCTION_= _, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); + } + } +} + +STATIC +VOID +SetAtuConfig1RW ( + PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private, + UINT32 Index + ) +{ + UINTN RbPciBase =3D Private->RbPciBar; + UINT64 MemLimit =3D GetPcieCfgAddress (Private->Ecam, Private->BusLimit = + 1, 0, 0, 0) - 1; + UINT64 MemBase =3D GetPcieCfgAddress (Private->Ecam, Private->BusBase + = 2, 0, 0, 0); + + + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYP= E_CONFIG1); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)Mem= Base); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(M= emBase >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) = MemLimit); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MOD= E); + + { + UINTN i; + for (i=3D0; i<0x20; i+=3D4) { + DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=3D%p value=3D%x\n", __FUNCTION_= _, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); + } + } +} + +STATIC +VOID +SetAtuIoRW (UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64= CpuIoRegionBase, UINT32 Index) +{ + + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_T= YPE_IO); + + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(= CpuIoRegionBase)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)= ((UINT64)CpuIoRegionBase >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32= )(CpuIoRegionLimit)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32= )(IoBase)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT3= 2)((UINT64)(IoBase) >> 32)); + + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_= MODE); + + { + UINTN i; + for (i=3D0; i<0x20; i+=3D4) { + DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=3D%p value=3D%x\n", __FUNCTIO= N__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); + } + } +} + +STATIC +VOID +SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT= 64 CpuMemRegionBase, UINT32 Index) +{ + + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_T= YPE_MEM); + + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(= CpuMemRegionBase)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)= ((UINT64)(CpuMemRegionBase) >> 32)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32= )(CpuMemRegionLimit)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32= )(MemBase)); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT3= 2)((UINT64)(MemBase) >> 32)); + + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_= MODE); + + { + UINTN i; + for (i=3D0; i<0x20; i+=3D4) { + DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=3D%p value=3D%x\n", __FUNCTIO= N__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); + } + } +} + +VOID +InitAtu (PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private) +{ + SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegi= onLimit, Private->CpuMemRegionBase, 0); + SetAtuConfig0RW (Private, 1); + SetAtuConfig1RW (Private, 2); + SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Privat= e->CpuIoRegionBase, 3); +} + +/*++ + +Routine Description: + + Perform Platform initialization first in PciPlatform. + +Arguments: + +Returns: + + VOID. + +--*/ +VOID +EFIAPI +PciInitPlatform ( + VOID + ) +{ + UINT32 Port; + UINT32 HostBridgeNum =3D 0; + + for (HostBridgeNum =3D 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridg= eNum++) { + for (Port =3D 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) { + InitAtu (&mResAppeture[HostBridgeNum][Port]); + } + } + + return; +} + diff --git a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPc= iPlatformLib.inf b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi= 161xPciPlatformLib.inf new file mode 100644 index 0000000000..274cad0abf --- /dev/null +++ b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatfo= rmLib.inf @@ -0,0 +1,42 @@ +## @file +# PCI Segment Library for Hisilicon Hi1610/Hi1616 SoC with multiple RCs +# +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.
+# Copyright (c) 2018, Hisilicon Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php. +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Hi161xPciPlatformLib + FILE_GUID =3D 22447df4-0baa-11e8-b6de-286ed489ee9b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciPlatformLib + +[Sources] + Hi161xPciPlatformLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + PlatformPciLib + +[Protocols] + gEfiPciHostBridgeResourceAllocationProtocolGuid + gEfiPciIoProtocolGuid + gEfiPciRootBridgeIoProtocolGuid --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel