From nobody Tue Feb 10 13:56:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1532416340699266.46270802216793; Tue, 24 Jul 2018 00:12:20 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6C393210C1235; Tue, 24 Jul 2018 00:12:20 -0700 (PDT) Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CFAFF210C1226 for ; Tue, 24 Jul 2018 00:12:18 -0700 (PDT) Received: by mail-pg1-x542.google.com with SMTP id y5-v6so2226261pgv.1 for ; Tue, 24 Jul 2018 00:12:18 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id t14-v6sm11449788pgu.0.2018.07.24.00.11.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Jul 2018 00:12:17 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pfmMOGPCxuzdEUVW71luh49qzTO9GtLUx4IHTfiWTa8=; b=RDolvQ6Cjc+9Mvy8cQhNDLrsQY2vhQGObTHrcl4wTAIy6uv/warXG1kB4AFe5W93Nk yWcdCSiMUvtpRX2Lzxadd0AnRjV4lZvFn2erraze/JBg93DqZ5yEkW9FvFUjuD7aImVi He/Ubl6mLcdW1nnGUO/Qx8NgMy8JwJkecfvy8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pfmMOGPCxuzdEUVW71luh49qzTO9GtLUx4IHTfiWTa8=; b=RYj/Y9HzSOeK/+MjRXOkHUg47BRK0cIDIOSn/8kTU0O+DLP2DXpeZvmLBddOPwHesI SUtYnPiAIp0WmWAVU7w6c7uo7Diwoj7Hvik5167IcLTWTHqdnIH01QZLXdeFQgdm6GhE GSKjCRavSDbe12wSf09xq/BB9Air3bhZ61lkjbotUC3dPf1xU+Hdl0LY8Yqyo+kRwcnh FNHRB4QnpD0m1V0BU/A+HbCv2GkzHI5ddr1tDKSN708ATEtrtOjFZYGqJ5pZ94wXJS+w hyxSc2UAfp5wGJwvcIwYQiriPsRS/XZF+e3nYXdK6N+bunKjnf1Ldc1oqU+iWJpQoeag amzg== X-Gm-Message-State: AOUpUlHTXxFgcl3N81sGSzTfjuiQArHzDniPIsyOFaAitGhYcATs4vSg LM3BpHbuXwZ1PnpqEYaJdRVhAQ== X-Google-Smtp-Source: AAOMgpfeLGW9GvlmIpvNpaF1GjfkNzTOByrxNGmzorkSGJlxe23MI/QM4sU3q3C6sJGH8YO4X8RtIw== X-Received: by 2002:a63:342:: with SMTP id 63-v6mr14766771pgd.290.1532416338316; Tue, 24 Jul 2018 00:12:18 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Tue, 24 Jul 2018 15:08:50 +0800 Message-Id: <20180724070922.63362-7-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180724070922.63362-1-ming.huang@linaro.org> References: <20180724070922.63362-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v1 06/38] Hisilicon/D06: Add OemMiscLibD06 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This library include BoardFeatureD06.c and OemMiscLibD06.c c file, use for several modules like PciHostBridgeLib and Smbios. Enlarge macro PCIEDEVICE_REPORT_MAX for D06. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D06/D06.dsc | = 1 + Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c | = 432 ++++++++++++++++++++ Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni | = Bin 0 -> 5204 bytes Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | = 157 +++++++ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | = 47 +++ Silicon/Hisilicon/Include/Library/OemMiscLib.h | = 2 +- 6 files changed, 638 insertions(+), 1 deletion(-) diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc index 88869ba26e..f4dfef1087 100644 --- a/Platform/Hisilicon/D06/D06.dsc +++ b/Platform/Hisilicon/D06/D06.dsc @@ -71,6 +71,7 @@ =20 TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf RealTimeClockLib|Platform/Hisilicon/D06/Library/M41T83RealTimeClockLib/M= 41T83RealTimeClockLib.inf + OemMiscLib|Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf OemAddressMapLib|Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddr= essMapD06.inf PlatformSysCtrlLib|Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi= 1620/PlatformSysCtrlLibHi1620.inf =20 diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c= b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c new file mode 100644 index 0000000000..c8f6cd0e29 --- /dev/null +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c @@ -0,0 +1,432 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +I2C_DEVICE gDS3231RtcDevice =3D { + .Socket =3D 0, + .Port =3D 5, + .DeviceType =3D DEVICE_TYPE_SPD, + .SlaveDeviceAddress =3D 0x68 +}; + +SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =3D +{ + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =3D +{ + {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM} +}; + +SERDES_PARAM gSerdesParamNA =3D { + .Hilink0Mode =3D EmHilink0Hccs1X8Width16, + .Hilink1Mode =3D EmHilink1Hccs0X8Width16, + .Hilink2Mode =3D EmHilink2Pcie2X8, + .Hilink3Mode =3D 0x0, + .Hilink4Mode =3D 0xF, + .Hilink5Mode =3D EmHilink5Sas1X4, + .Hilink6Mode =3D 0x0, + .UseSsc =3D 0, +}; + +SERDES_PARAM gSerdesParamNB =3D { + .Hilink0Mode =3D EmHilink0Pcie1X8, + .Hilink1Mode =3D EmHilink1Pcie0X8, + .Hilink2Mode =3D EmHilink2Sas0X8, + .Hilink3Mode =3D 0x0, + .Hilink4Mode =3D 0xF, + .Hilink5Mode =3D EmHilink5Pcie2X2Pcie3X2, + .Hilink6Mode =3D 0xF, + .UseSsc =3D 0, +}; + +SERDES_PARAM gSerdesParamS1NA =3D { + .Hilink0Mode =3D EmHilink0Hccs1X8Width16, + .Hilink1Mode =3D EmHilink1Hccs0X8Width16, + .Hilink2Mode =3D EmHilink2Pcie2X8, + .Hilink3Mode =3D 0x0, + .Hilink4Mode =3D 0xF, + .Hilink5Mode =3D EmHilink5Sas1X4, + .Hilink6Mode =3D 0x0, + .UseSsc =3D 0, +}; + +SERDES_PARAM gSerdesParamS1NB =3D { + .Hilink0Mode =3D EmHilink0Pcie1X8, + .Hilink1Mode =3D EmHilink1Pcie0X8, + .Hilink2Mode =3D EmHilink2Sas0X8, + .Hilink3Mode =3D 0x0, + .Hilink4Mode =3D 0xF, + .Hilink5Mode =3D EmHilink5Pcie2X2Pcie3X2, + .Hilink6Mode =3D 0xF, + .UseSsc =3D 0, +}; + + +EFI_STATUS +OemGetSerdesParam ( + OUT SERDES_PARAM *ParamA, + OUT SERDES_PARAM *ParamB, + IN UINT32 SocketId + ) +{ + if (NULL =3D=3D ParamA) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param =3D=3D NULL!\n", __FUNCTION__, = __LINE__)); + return EFI_INVALID_PARAMETER; + } if (NULL =3D=3D ParamB) { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param =3D=3D NULL!\n", __FUNCTION__, = __LINE__)); + return EFI_INVALID_PARAMETER; + } + + if (0 =3D=3D SocketId) { + (VOID) CopyMem (ParamA, &gSerdesParamNA, sizeof (*ParamA)); + (VOID) CopyMem (ParamB, &gSerdesParamNB, sizeof (*ParamB)); + } else { + (VOID) CopyMem (ParamA, &gSerdesParamS1NA, sizeof (*ParamA)); + (VOID) CopyMem (ParamB, &gSerdesParamS1NB, sizeof (*ParamB)); + } + + return EFI_SUCCESS; +} + +VOID +OemPcieResetAndOffReset ( + VOID + ) +{ + return; +} + +SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] =3D { + // PCIe0 Slot 1 + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX16, // SlotType + SlotDataBusWidth16X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0001, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 0, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0 // ModemRingResumeSupported:1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 0, // SmbusSignalSupported :1; + 0 // Reserved :5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0002, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown := 1; + 0, // Provides50Volts := 1; + 0, // Provides33Volts := 1; + 0, // SharedSlot := 1; + 0, // PcCard16Supported := 1; + 0, // CardBusSupported := 1; + 0, // ZoomVideoSupported := 1; + 0 // ModemRingResumeSupported:= 1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported := 1; + 0, // HotPlugDevicesSupported = :1; + 0, // SmbusSignalSupported := 1; + 0 // Reserved := 5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0003, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown := 1; + 0, // Provides50Volts := 1; + 0, // Provides33Volts := 1; + 0, // SharedSlot := 1; + 0, // PcCard16Supported := 1; + 0, // CardBusSupported := 1; + 0, // ZoomVideoSupported := 1; + 0 // ModemRingResumeSupported:= 1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported := 1; + 0, // HotPlugDevicesSupported = :1; + 0, // SmbusSignalSupported := 1; + 0 // Reserved := 5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + + + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0004, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown := 1; + 0, // Provides50Volts := 1; + 0, // Provides33Volts := 1; + 0, // SharedSlot := 1; + 0, // PcCard16Supported := 1; + 0, // CardBusSupported := 1; + 0, // ZoomVideoSupported := 1; + 0 // ModemRingResumeSupported:= 1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported := 1; + 0, // HotPlugDevicesSupported = :1; + 0, // SmbusSignalSupported := 1; + 0 // Reserved := 5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX16, // SlotType + SlotDataBusWidth16X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0005, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown := 1; + 0, // Provides50Volts := 1; + 0, // Provides33Volts := 1; + 0, // SharedSlot := 1; + 0, // PcCard16Supported := 1; + 0, // CardBusSupported := 1; + 0, // ZoomVideoSupported := 1; + 0 // ModemRingResumeSupported:= 1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported := 1; + 0, // HotPlugDevicesSupported = :1; + 0, // SmbusSignalSupported := 1; + 0 // Reserved := 5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0006, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown := 1; + 0, // Provides50Volts := 1; + 0, // Provides33Volts := 1; + 0, // SharedSlot := 1; + 0, // PcCard16Supported := 1; + 0, // CardBusSupported := 1; + 0, // ZoomVideoSupported := 1; + 0 // ModemRingResumeSupported:= 1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported := 1; + 0, // HotPlugDevicesSupported = :1; + 0, // SmbusSignalSupported := 1; + 0 // Reserved := 5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0007, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown := 1; + 0, // Provides50Volts := 1; + 0, // Provides33Volts := 1; + 0, // SharedSlot := 1; + 0, // PcCard16Supported := 1; + 0, // CardBusSupported := 1; + 0, // ZoomVideoSupported := 1; + 0 // ModemRingResumeSupported:= 1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported := 1; + 0, // HotPlugDevicesSupported = :1; + 0, // SmbusSignalSupported := 1; + 0 // Reserved := 5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + { + { // Hdr + EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type, + 0, // Length, + 0 // Handle + }, + 1, // SlotDesignation + SlotTypePciExpressX8, // SlotType + SlotDataBusWidth8X, // SlotDataBusWidth + SlotUsageAvailable, // SlotUsage + SlotLengthOther, // SlotLength + 0x0008, // SlotId + { // SlotCharacteristics1 + 0, // CharacteristicsUnknown := 1; + 0, // Provides50Volts := 1; + 0, // Provides33Volts := 1; + 0, // SharedSlot := 1; + 0, // PcCard16Supported := 1; + 0, // CardBusSupported := 1; + 0, // ZoomVideoSupported := 1; + 0 // ModemRingResumeSupported:= 1; + }, + { // SlotCharacteristics2 + 0, // PmeSignalSupported := 1; + 0, // HotPlugDevicesSupported = :1; + 0, // SmbusSignalSupported := 1; + 0 // Reserved := 5; + }, + 0x00, // SegmentGroupNum + 0x00, // BusNum + 0 // DevFuncNum + }, + + }; + +UINT8 +OemGetPcieSlotNumber ( + VOID + ) +{ + return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9); +} + +EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] =3D { + {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_= 001)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_= 011)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_= 021)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_= 031)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_040), STRING_TOKEN(STR_LEMON_C10_DIMM_= 041)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_050), STRING_TOKEN(STR_LEMON_C10_DIMM_= 051)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_060), STRING_TOKEN(STR_LEMON_C10_DIMM_= 061)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_070), STRING_TOKEN(STR_LEMON_C10_DIMM_= 071)}}, + + {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_= 101)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_= 111)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_= 121)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_= 131)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_140), STRING_TOKEN(STR_LEMON_C10_DIMM_= 141)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_150), STRING_TOKEN(STR_LEMON_C10_DIMM_= 151)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_160), STRING_TOKEN(STR_LEMON_C10_DIMM_= 161)}, + {STRING_TOKEN(STR_LEMON_C10_DIMM_170), STRING_TOKEN(STR_LEMON_C10_DIMM_= 171)}} +}; + +EFI_HII_HANDLE +EFIAPI +OemGetPackages ( + VOID + ) +{ + return HiiAddPackages ( + &gEfiCallerIdGuid, + NULL, + OemMiscLibStrings, + NULL, + NULL + ); +} + + diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06St= rings.uni b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Str= ings.uni new file mode 100644 index 0000000000..f3994d9d4d Binary files /dev/null and b/Platform/Hisilicon/D06/Library/OemMiscLibD06/B= oardFeatureD06Strings.uni differ diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b= /Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c new file mode 100644 index 0000000000..009a53b2c8 --- /dev/null +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c @@ -0,0 +1,157 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] =3D { + {67,0,0,0}, + {225,0,0,3}, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF}, + {0xFFFF,0xFFFF,0xFFFF,0xFFFF} +}; + +// Right now we only support 1P +BOOLEAN +OemIsSocketPresent ( + UINTN Socket + ) +{ + UINT32 SocketMask =3D PcdGet32 (PcdSocketMask); + return (BOOLEAN)((SocketMask & (1 << Socket)) ? TRUE : FALSE); +} + + +UINTN +OemGetSocketNumber ( + VOID + ) +{ + if(!OemIsMpBoot ()) { + return 1; + } + + return 2; +} + + +UINTN +OemGetDdrChannel ( + VOID + ) +{ + return 8; +} + + +UINTN +OemGetDimmSlot ( + UINTN Socket, + UINTN Channel + ) +{ + return 2; +} + + +// Nothing to do for EVB +VOID +OemPostEndIndicator ( + VOID + ) +{ + DEBUG ((DEBUG_ERROR,"M3 release reset CONFIG.........")); + + MmioWrite32 (0xd0002180, 0x3); + MmioWrite32 (0xd0002194, 0xa4); + MmioWrite32 (0xd0000a54, 0x1); + + MicroSecondDelay (10000); + + MmioWrite32 (0xd0002108, 0x1); + MmioWrite32 (0xd0002114, 0x1); + MmioWrite32 (0xd0002120, 0x1); + MmioWrite32 (0xd0003108, 0x1); + + MicroSecondDelay (500000); + DEBUG ((DEBUG_ERROR, "Done\n")); +} + + + +VOID +CoreSelectBoot ( + VOID + ) +{ + if (!PcdGet64 (PcdTrustedFirmwareEnable)) + { + StartupAp (); + } + + return; +} + +BOOLEAN +OemIsMpBoot ( + VOID + ) +{ + return PcdGet32 (PcdIsMPBoot); +} + +VOID +OemLpcInit ( + VOID + ) +{ + LpcInit (); + return; +} + +UINT32 +OemIsWarmBoot ( + VOID + ) +{ + return 0; +} + +VOID +OemBiosSwitch ( + UINT32 Master + ) +{ + (VOID)Master; + return; +} + +BOOLEAN +OemIsNeedDisableExpanderBuffer ( + VOID + ) +{ + return TRUE; +} diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf= b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf new file mode 100644 index 0000000000..acb7366078 --- /dev/null +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf @@ -0,0 +1,47 @@ +#/** @file +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the= BSD License +# which accompanies this distribution. The full text of the license may= be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D OemMiscLib + FILE_GUID =3D 3002911C-C160-4C46-93BB-782846673EEA + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D OemMiscLib + +[Sources.common] + BoardFeatureD06.c + OemMiscLibD06.c + BoardFeatureD06Strings.uni + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + PcdLib + TimerLib + SerdesLib + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES + +[Pcd] + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable + gHisiTokenSpaceGuid.PcdSocketMask + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz + gHisiTokenSpaceGuid.PcdIsMPBoot diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisil= icon/Include/Library/OemMiscLib.h index 6f18c0fa72..53e7a37a68 100644 --- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h +++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h @@ -22,7 +22,7 @@ #include #include =20 -#define PCIEDEVICE_REPORT_MAX 4 +#define PCIEDEVICE_REPORT_MAX 8 typedef struct _REPORT_PCIEDIDVID2BMC{ UINTN Bus; UINTN Device; --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel