From nobody Thu Mar 28 11:06:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1533890290887184.41676310018852; Fri, 10 Aug 2018 01:38:10 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3BEB2210EB11F; Fri, 10 Aug 2018 01:38:09 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B243221BADAB2 for ; Fri, 10 Aug 2018 01:38:07 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Aug 2018 01:38:08 -0700 Received: from zwei4-mobl1.ccr.corp.intel.com ([10.239.193.212]) by orsmga004.jf.intel.com with ESMTP; 10 Aug 2018 01:37:43 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=david.wei@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,218,1531810800"; d="scan'208";a="223530801" From: zwei4 To: edk2-devel@lists.01.org Date: Fri, 10 Aug 2018 16:37:18 +0800 Message-Id: <20180810083718.11176-1-david.wei@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 Subject: [edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] UP2 Board Enabling. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Wei MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RDMRC_1 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add board specific code for AAEON UP2 board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: David Wei CC: Mike Wu CC: Mang Guo --- .../Board/UP2/BoardInitDxe/BoardInitDxe.c | 68 +++ .../Board/UP2/BoardInitDxe/BoardInitDxe.h | 37 ++ .../Board/UP2/BoardInitDxe/BoardInitDxe.inf | 53 +++ .../Board/UP2/BoardInitPostMem/BoardGpios.c | 280 ++++++++++++ .../Board/UP2/BoardInitPostMem/BoardGpios.h | 470 +++++++++++++++++= ++++ .../Board/UP2/BoardInitPostMem/BoardInit.c | 190 +++++++++ .../Board/UP2/BoardInitPostMem/BoardInit.h | 30 ++ .../Board/UP2/BoardInitPostMem/BoardInitMiscs.c | 179 ++++++++ .../Board/UP2/BoardInitPostMem/BoardInitMiscs.h | 132 ++++++ .../UP2/BoardInitPostMem/BoardInitPostMem.inf | 93 ++++ .../Board/UP2/BoardInitPostMem/HdaVerbTables.c | 145 +++++++ .../Board/UP2/BoardInitPostMem/HdaVerbTables.h | 38 ++ .../Board/UP2/BoardInitPostMem/PlatformInfoHob.c | 59 +++ .../Board/UP2/BoardInitPreMem/BoardInit.c | 180 ++++++++ .../Board/UP2/BoardInitPreMem/BoardInit.h | 29 ++ .../Board/UP2/BoardInitPreMem/BoardInitMiscs.c | 342 +++++++++++++++ .../Board/UP2/BoardInitPreMem/BoardInitMiscs.h | 46 ++ .../Board/UP2/BoardInitPreMem/BoardInitPreMem.inf | 57 +++ .../Board/UP2/BoardInitPreMem/PlatformId.c | 57 +++ .../Board/UP2/BoardInitPreMem/PlatformId.h | 74 ++++ Platform/BroxtonPlatformPkg/Board/UP2/Vbt/Vbt.bin | Bin 0 -> 5632 bytes 21 files changed, 2559 insertions(+) create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/Boar= dInitDxe.c create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/Boar= dInitDxe.h create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/Boar= dInitDxe.inf create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/= BoardGpios.c create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/= BoardGpios.h create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/= BoardInit.c create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/= BoardInit.h create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/= BoardInitMiscs.c create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/= BoardInitMiscs.h create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/= BoardInitPostMem.inf create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/= HdaVerbTables.c create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/= HdaVerbTables.h create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/= PlatformInfoHob.c create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/B= oardInit.c create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/B= oardInit.h create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/B= oardInitMiscs.c create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/B= oardInitMiscs.h create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/B= oardInitPreMem.inf create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/P= latformId.c create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/P= latformId.h create mode 100644 Platform/BroxtonPlatformPkg/Board/UP2/Vbt/Vbt.bin diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDx= e.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.c new file mode 100644 index 0000000000..3b5c5ac566 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.c @@ -0,0 +1,68 @@ +/** @file + Board specific functions in DXE phase to be set as dynamic PCD and consu= med by + commmon platform code. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "BoardInitDxe.h" + +GET_BOARD_NAME mUp2GetBoardNamePtr =3D Up2GetBoardName; + +CHAR16* +EFIAPI +Up2GetBoardName ( + IN UINT8 BoardId + ) +{ + STATIC CHAR16 BoardName[40]; + + DEBUG ((EFI_D_INFO, "BoardInitDxe: GetBoardName\n")); + UnicodeSPrint (BoardName, sizeof (BoardName), L"UP2 "); //MyBoardPorting + + if (BoardId !=3D (UINT8) BOARD_ID_UP2) { + return NULL; + } else { + DEBUG ((EFI_D_INFO, "It is UP2.\n")); + return BoardName; + } +} + + +/** + Set PCDs for board specific functions + + @param[in] ImageHandle ImageHandle of the loaded driver. + @param[in] SystemTable Pointer to the EFI System Table. + + @retval EFI_SUCCESS The handlers were registered successfully. + +**/ +EFI_STATUS +EFIAPI +Up2BoardInitDxeConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT8 BoardId; + + BoardId =3D PcdGet8 (PcdBoardId); + if (BoardId !=3D (UINT8) BOARD_ID_UP2) {//MyBoardPorting + return EFI_SUCCESS; + } + + PcdSet64 (PcdGetBoardNameFunc, (UINT64) mUp2GetBoardNamePtr); + + return EFI_SUCCESS; +} + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDx= e.h b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.h new file mode 100644 index 0000000000..61e66978ac --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.h @@ -0,0 +1,37 @@ +/** @file + The internal header file includes the common header files, defines + internal structure and functions used by ImageVerificationLib. + + Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __MYBOARD_BOARD_INIT_DXE_H__ +#define __MYBOARD_BOARD_INIT_DXE_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +CHAR16* +EFIAPI +Up2GetBoardName ( + IN UINT8 BoardId + ); + +#endif diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDx= e.inf b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.inf new file mode 100644 index 0000000000..5abd6e27a2 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitDxe/BoardInitDxe.inf @@ -0,0 +1,53 @@ +## @file +# Board specific functions in DXE phase to be set as dynamic PCD and cons= umed by +# commmon platform code. +# +# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D Up2BoardInitDxe + FILE_GUID =3D D406820E-9CD3-45b3-8D83-74C6CFFB7C80 + + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL|DXE_DRIVER DXE_RUNTIME_DRIVER DX= E_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER + CONSTRUCTOR =3D Up2BoardInitDxeConstructor + +[Sources] + BoardInitDxe.c + BoardInitDxe.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + BroxtonPlatformPkg/PlatformPkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + +[LibraryClasses] + BaseLib + UefiLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + DebugLib + PcdLib + PrintLib + +[Protocols] + +[Guids] + +[Pcd] + gPlatformModuleTokenSpaceGuid.PcdGetBoardNameFunc + gPlatformModuleTokenSpaceGuid.PcdBoardId + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardGp= ios.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardGpios.c new file mode 100644 index 0000000000..81d642d9ff --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardGpios.c @@ -0,0 +1,280 @@ +/** @file + Gpio setting for multiplatform. + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "BoardGpios.h" +#include +#include + +/** + Returns the Correct GPIO table for Mobile/Desktop respectively. + Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get= correctly. + + @param[in] PeiServices General purpose services available to eve= ry PEIM. + @param[in] PlatformInfoHob PlatformInfoHob pointer with PlatformFlav= or specified. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_DEVICE_ERROR KSC fails to respond. + +**/ +EFI_STATUS +Up2MultiPlatformGpioTableInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ) +{ + DEBUG ((DEBUG_INFO, "Up2MultiPlatformGpioTableInit()...\n")); + DEBUG ((DEBUG_INFO, "PlatformInfoHob->BoardId: 0x%02X\n", PlatformInfoHo= b->BoardId)); + + // + // Select/modify the GPIO initialization data based on the Board ID. + // + switch (PlatformInfoHob->BoardId) { + case BOARD_ID_UP2: + PlatformInfoHob->PlatformGpioSetting_SW =3D &mUp2_GpioInitData_SW[0]; + PlatformInfoHob->PlatformGpioSetting_W =3D &mUp2_GpioInitData_W[0]; + PlatformInfoHob->PlatformGpioSetting_NW =3D &mUp2_GpioInitData_NW[0]; + PlatformInfoHob->PlatformGpioSetting_N =3D &mUp2_GpioInitData_N[0]; + break; + + default: + PlatformInfoHob->PlatformGpioSetting_SW =3D &mUp2_GpioInitData_SW[0]; + PlatformInfoHob->PlatformGpioSetting_W =3D &mUp2_GpioInitData_W[0]; + PlatformInfoHob->PlatformGpioSetting_NW =3D &mUp2_GpioInitData_NW[0]; + PlatformInfoHob->PlatformGpioSetting_N =3D &mUp2_GpioInitData_N[0]; + break; + } + + return EFI_SUCCESS; +} + + +/** + Set GPIO Lock for security. + +**/ +VOID +Up2SetGpioPadCfgLock ( + VOID + ) +{ + UINT32 Data32; + + Data32 =3D 0; + + // + // JTAG + // + GpioLockPadCfg (N_TCK); + GpioLockPadCfg (N_TRST_B); + GpioLockPadCfg (N_TMS); + GpioLockPadCfg (N_TDI); + GpioLockPadCfg (N_TDO); + + // + // Power + // + GpioLockPadCfg (NW_PMIC_THERMTRIP_B); + GpioLockPadCfg (NW_PROCHOT_B); + + // + // Touch + // + GpioLockPadCfg (NW_GPIO_118); + GpioLockPadCfg (NW_GPIO_119); + GpioLockPadCfg (NW_GPIO_120); + GpioLockPadCfg (NW_GPIO_121); + GpioLockPadCfg (NW_GPIO_122); + GpioLockPadCfg (NW_GPIO_123); + + // + // SPI + // + GpioLockPadCfg (NW_GPIO_97); + GpioLockPadCfg (NW_GPIO_98); + GpioLockPadCfg (NW_GPIO_99); + GpioLockPadCfg (NW_GPIO_100); + GpioLockPadCfg (NW_GPIO_101); + GpioLockPadCfg (NW_GPIO_102); + GpioLockPadCfg (NW_GPIO_103); + GpioLockPadCfg (NW_FST_SPI_CLK_FB); + + // + // SMBus + // Set SMBus GPIO PAD_CFG.PADRSTCFG to Powergood + // + Data32 =3D GpioPadRead (SW_SMB_ALERTB); + Data32 &=3D ~(BIT31 | BIT30); + GpioPadWrite (SW_SMB_ALERTB, Data32); + + Data32 =3D GpioPadRead (SW_SMB_CLK); + Data32 &=3D ~(BIT31 | BIT30); + GpioPadWrite (SW_SMB_CLK, Data32); + + Data32 =3D GpioPadRead (SW_SMB_DATA); + Data32 &=3D ~(BIT31 | BIT30); + GpioPadWrite (SW_SMB_DATA, Data32); + + GpioLockPadCfg (SW_SMB_ALERTB); + GpioLockPadCfg (SW_SMB_CLK); + GpioLockPadCfg (SW_SMB_DATA); +} + + +/** + Returns the Correct GPIO table for Mobile/Desktop respectively. + Before call it, make sure PlatformInfoHob->BoardId&PlatformFlavor is get= correctly. + + @param[in] PeiServices General purpose services available to ev= ery PEIM. + @param[in] PlatformInfoHob PlatformInfoHob pointer with PlatformFla= vor specified. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_DEVICE_ERROR KSC fails to respond. + +**/ +EFI_STATUS +Up2MultiPlatformGpioProgram ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ) +{ + UINTN VariableSize; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + SYSTEM_CONFIGURATION SystemConfiguration; + + VariableSize =3D sizeof (SYSTEM_CONFIGURATION); + ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION)); + + (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **) &VariableServices + ); + + VariableServices->GetVariable ( + VariableServices, + PLATFORM_SETUP_VARIABLE_NAME, + &gEfiSetupVariableGuid, + NULL, + &VariableSize, + &SystemConfiguration + ); + + DEBUG ((DEBUG_INFO, "Up2MultiPlatformGpioProgram()...\n")); + + switch (PlatformInfoHob->BoardId) { + case BOARD_ID_UP2: + // + // PAD programming + // + DEBUG ((DEBUG_INFO, "PAD programming, Board ID: 0x%X\n", PlatformInf= oHob->BoardId)); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_N) / sizeof (mUp2_Gpio= InitData_N[0]), PlatformInfoHob->PlatformGpioSetting_N); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_NW) / sizeof (mUp2_Gpi= oInitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_W) / sizeof (mUp2_Gpio= InitData_W[0]), PlatformInfoHob->PlatformGpioSetting_W); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_SW) / sizeof (mUp2_Gpi= oInitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_N_LH) / sizeof (mUp2_G= pioInitData_N_LH[0]), mUp2_GpioInitData_N_LH); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_SW_LH) / sizeof (mUp2_= GpioInitData_SW_LH[0]), mUp2_GpioInitData_SW_LH); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_W_LH) / sizeof (mUp2_G= pioInitData_W_LH[0]), mUp2_GpioInitData_W_LH); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_NW_LH) / sizeof (mUp2_= GpioInitData_NW_LH[0]), mUp2_GpioInitData_NW_LH); + + if (SystemConfiguration.ScIshEnabled =3D=3D 0) { + DEBUG ((DEBUG_INFO, "Switch ISH_I2C0 & ISH_I2C1 to LPSS_I2C5 and L= PSS I2C6. \n" )); + GpioPadConfigTable(sizeof(mUp2_GpioInitData_LPSS_I2C)/sizeof(mUp2_= GpioInitData_LPSS_I2C[0]), mUp2_GpioInitData_LPSS_I2C); + } + break; + default: + + // + // PAD programming + // + GpioPadConfigTable (sizeof (mUp2_GpioInitData_N) / sizeof (mUp2_GpioIn= itData_N[0]), PlatformInfoHob->PlatformGpioSetting_N); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_NW) / sizeof (mUp2_GpioI= nitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_W) / sizeof (mUp2_GpioIn= itData_W[0]), PlatformInfoHob->PlatformGpioSetting_W); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_SW) / sizeof (mUp2_GpioI= nitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW); + + // + // Note1: This BXT BIOS WA needs to be applied after PAD programming t= o overwrite the GPIO setting to take effect. + // Note2: Enable TDO in BIOS SETUP as default for BXT Power-On only, n= eed to set to AUTO prior to deliver to customer. + // For BXT A0 Stepping only, to disable TDO GPIO to save power. + // + if (PlatformInfoHob->FABID =3D=3D FAB2) { + DEBUG ((DEBUG_INFO, "FAB ID: FAB2\n")); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_FAB2 )/ sizeof (mUp2_G= pioInitData_FAB2[0]), mUp2_GpioInitData_FAB2); + } + + if (SystemConfiguration.TDO =3D=3D 2) { //Auto + if (BxtA0 =3D=3D BxtStepping()) { + DEBUG ((DEBUG_INFO, " BxtA0 TDO disable\n" )); + } + } else if (SystemConfiguration.TDO =3D=3D 0) { // Disable + DEBUG ((DEBUG_INFO, " Setup option to disable TDO\n" )); + } + + if (SystemConfiguration.ScHdAudioIoBufferOwnership =3D=3D 3) { + DEBUG ((DEBUG_INFO, "HD Audio IO Buffer Ownership is I2S. Change GPI= O pin settings for it. \n" )); + GpioPadConfigTable ( sizeof (mUp2_GpioInitData_Audio_SSP6) / sizeof = (mUp2_GpioInitData_Audio_SSP6[0]), mUp2_GpioInitData_Audio_SSP6); + } + + if (SystemConfiguration.PcieRootPortEn[4] =3D=3D FALSE) { + DEBUG ((DEBUG_INFO, "Onboard LAN disable. \n" )); + GpioPadConfigTable ( sizeof (Up2LomDisableGpio) / sizeof (Up2LomDisa= bleGpio[0]), Up2LomDisableGpio); + } + + if (SystemConfiguration.EPIEnable =3D=3D 1) { + DEBUG((DEBUG_INFO, "Overriding GPIO 191 for EPI\n")); + GpioPadConfigTable (sizeof (mUp2_GpioInitData_EPI_Override) / sizeof= (mUp2_GpioInitData_EPI_Override[0]), mUp2_GpioInitData_EPI_Override); + } + if (SystemConfiguration.GpioLock =3D=3D TRUE) { + Up2SetGpioPadCfgLock (); + } + DEBUG ((DEBUG_INFO, "No board ID available for this board ....\n")); + break; + } + + // + // Dump Community registers + // + DumpGpioCommunityRegisters (NORTH); + DumpGpioCommunityRegisters (NORTHWEST); + DumpGpioCommunityRegisters (WEST); + DumpGpioCommunityRegisters (SOUTHWEST); + + switch (PlatformInfoHob->BoardId) { + case BOARD_ID_UP2: + // + // PAD programming + // + DEBUG ((DEBUG_INFO, "Dump Community pad registers, Board ID: 0x%X\n"= , PlatformInfoHob->BoardId)); + DumpGpioPadTable (sizeof (mUp2_GpioInitData_N) / sizeof (mUp2_GpioIn= itData_N[0]), PlatformInfoHob->PlatformGpioSetting_N); + DumpGpioPadTable (sizeof (mUp2_GpioInitData_NW_LH) / sizeof (mUp2_Gp= ioInitData_NW_LH[0]), PlatformInfoHob->PlatformGpioSetting_NW); + DumpGpioPadTable (sizeof (mUp2_GpioInitData_W_LH) / sizeof (mUp2_Gpi= oInitData_W_LH[0]), PlatformInfoHob->PlatformGpioSetting_W); + DumpGpioPadTable (sizeof (mUp2_GpioInitData_SW_LH) / sizeof (mUp2_Gp= ioInitData_SW_LH[0]), PlatformInfoHob->PlatformGpioSetting_SW); + break; + default: + + // + // Dump Community pad registers + // + DumpGpioPadTable (sizeof (mUp2_GpioInitData_N) / sizeof (mUp2_GpioIn= itData_N[0]), PlatformInfoHob->PlatformGpioSetting_N); + DumpGpioPadTable (sizeof (mUp2_GpioInitData_NW) / sizeof (mUp2_GpioI= nitData_NW[0]), PlatformInfoHob->PlatformGpioSetting_NW); + DumpGpioPadTable (sizeof (mUp2_GpioInitData_W) / sizeof (mUp2_GpioIn= itData_W[0]), PlatformInfoHob->PlatformGpioSetting_W); + DumpGpioPadTable (sizeof (mUp2_GpioInitData_SW) / sizeof (mUp2_GpioI= nitData_SW[0]), PlatformInfoHob->PlatformGpioSetting_SW); + break; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardGp= ios.h b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardGpios.h new file mode 100644 index 0000000000..048e5f3892 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardGpios.h @@ -0,0 +1,470 @@ +/** @file + GPIO setting for Broxton. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _MYBOARD_BOARDGPIOS_H_ +#define _MYBOARD_BOARDGPIOS_H_ + +#include +#include"ChipsetAccess.h" +#include"PlatformBaseAddresses.h" +#include "BoardInitMiscs.h" +#include +#include +#include +#include + + +/** +GPIO input pin interrupt type configuration: + +Interrupt type GPI Route Host SW Enable/S= tatus Comment + GPI None GPIO Driver Mode GPI Int= errupt Status\Enable GPIO driver to handle it. + Direct IRQ GPIROUTIOXAPIC ACPI Mode = IRQ number is fixed to each GPIO pin= in N and NW communities. + SCI/GPE GPIROUTSCI ACPI Mode GPI Gen= eral Purpose Events Status\Enable SCI is not supported in BXT A0. The = reason is because the PMC lacks the ACPI registers and status tunneling. Th= is will be fixed in derivatives. + SMI GPIROUTSMI ACPI Mode SMI Sta= tus\Enable Don't enable SMI for BXT0. It is cur= rently unsupported by the PMC. + NMI GPIROUTNMI ACPI Mode = Not supported on BXT. + +Interrupt trigger type Configuration Comment + Rising edge Edge+No_invert + Falling edge Edge+Invert + Both edge BothEdge+Invert + Level high Level+No_invert Direct = IRQ pin mostly use this config.Wake pin MUST use it. + Level low Level+Invert + +HostSw: + * All GPIO pins which are 'M0' PMode, have to set HostSw to GPIO_D, indic= ating GPIO driver owns it. + * Others, such as Native function(M1,M2,M3..) and SCI/SMI/NMI/Direct IRQ,= need to set it to ACPI_D or NA. + * Default is ACPI_D for NA + +IOSstate: + * For interrupt or wake pin, need to set it to TxDRxE. + +Wake_Enabled: + * It is for direct IRQ only. + +**/ + +// +// North Community +// +BXT_GPIO_PAD_INIT mUp2_GpioInitData_N[] =3D +{ + // + // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,G= PO_STATE,INT_Trigger, Wake_Enabled ,Term_H_L,Inverted, GPI_ROUT, IOSstae, = IOSTerm, MMIO_Offset ,Community + // + BXT_GPIO_PAD_CONF(L"GPIO_0", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0000, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_1", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0008, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_2", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0010, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_3", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0018, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_4", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0020, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_5", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0028, NORTH),//Mux with CSE_PG based on the SW3 swit= ch + BXT_GPIO_PAD_CONF(L"GPIO_6", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0030, NORTH),//Mux with DISP1_RST_N based on the SW3= switch + BXT_GPIO_PAD_CONF(L"GPIO_7", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0038, NORTH),//Mux with DISP1_TOUCH_INT_N based on t= he SW3 switch + BXT_GPIO_PAD_CONF(L"GPIO_8", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = SAME, GPIO_PADBAR+0x0040, NORTH),//Mux with DISP1_TOUCH_RST_N based on t= he SW3 switch + BXT_GPIO_PAD_CONF(L"GPIO_9", M0 , GPI , NA ,= NA , Level , Wake_Disabled, P_20K_L, Inverted,IOAPIC, TxDRxE , = NA, GPIO_PADBAR+0x0048, NORTH),//Feature:Interrupt Net in= Sch: SPI_TPM_HDR_IRQ_N + BXT_GPIO_PAD_CONF(L"GPIO_10", M0 , GPI , NA ,= NA , Level , Wake_Enabled , P_20K_L, Inverted,IOAPIC, TxDRxE , = NA, GPIO_PADBAR+0x0050, NORTH),//Feature:WAKE Net in= Sch: SLTA_SDIO_WAKE_N + BXT_GPIO_PAD_CONF(L"GPIO_11", M0 , GPI , NA ,= NA , Edge , Wake_Disabled, P_20K_L, Inverted, SCI, TxDRxE , = NA, GPIO_PADBAR+0x0058, NORTH),//Feature:Runtime SCI Net in= Sch: SOC_RUNTIME_SCI_N + BXT_GPIO_PAD_CONF(L"GPIO_12", M0 , GPI , NA ,= NA , Edge , Wake_Disabled, P_20K_L, Inverted, SCI, TxDRxE , = NA, GPIO_PADBAR+0x0060, NORTH),//Feature:Wake SCI Net in= Sch: EC_WAKE_SCI_N + BXT_GPIO_PAD_CONF(L"GPIO_14", M0 , GPI , GPIO_D,= NA , Edge , Wake_Disabled, P_20K_L, Inverted,IOAPIC, TxDRxE , = NA, GPIO_PADBAR+0x0070, NORTH),//Feature:Interrupt Net in= Sch: FGR_INT + BXT_GPIO_PAD_CONF(L"GPIO_16", M0 , GPI , NA ,= NA , Edge , Wake_Disabled, P_20K_H, Inverted,IOAPIC, HizRx0I ,D= isPuPd, GPIO_PADBAR+0x0080, NORTH),//Feature:SIM Card Detect Net in= Sch: SIM_CON_CD1, falling edge trigger + BXT_GPIO_PAD_CONF(L"GPIO_18", M0 , GPI , NA ,= NA , Level , Wake_Disabled, P_20K_H, Inverted ,IOAPIC, TxDRxE , = NA, GPIO_PADBAR+0x0090, NORTH),//Feature:Interrupt Net in= Sch: TCHPAD_INT_N + BXT_GPIO_PAD_CONF(L"GPIO_20", M0 , GPI , NA ,= NA , Edge , Wake_Disabled, P_20K_L, NA ,IOAPIC, TxDRxE, = NA, GPIO_PADBAR+0x00A0, NORTH),//Feature:Interrupt Net in= Sch: NFC_IRQ_CONN + BXT_GPIO_PAD_CONF(L"GPIO_21", M0 , GPI , NA ,= NA , Level , Wake_Disabled, P_20K_H, Inverted,IOAPIC, TxDRxE, = NA, GPIO_PADBAR+0x00A8, NORTH),//Feature:Interrupt Net in= Sch: TCH_PNL_INTR_LS_N + BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPI , GPIO_D,= NA , Level , Wake_Disabled, P_20K_L,Inverted , NA, NA , = NA, GPIO_PADBAR+0x00B8, NORTH),//Feature:Present Pin Net in= Sch: SATA_ODD_PRSNT_N + BXT_GPIO_PAD_CONF(L"GPIO_24", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x00C0, NORTH),//SATA_DEVSLP0 + BXT_GPIO_PAD_CONF(L"GPIO_25", M0 , GPI , ACPI_D,= NA , Level , Wake_Disabled, P_20K_H, Inverted, SCI, NA , = NA, GPIO_PADBAR+0x00C8, NORTH),//Feature:ODD MD/DA SCI Net in= Sch: SATA_ODD_DA_IN + BXT_GPIO_PAD_CONF(L"GPIO_26", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00D0, NORTH),//SATA_LEDN + BXT_GPIO_PAD_CONF(L"GPIO_27", M0 , GPO , GPIO_D,= HI , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00D8, NORTH),//Feature:DFU Net in= Sch: NFC_DFU + BXT_GPIO_PAD_CONF(L"GPIO_28", M2 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00E0, NORTH),// Net in= Sch: ISH_GPIO10 + BXT_GPIO_PAD_CONF(L"GPIO_29", M2 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00E8, NORTH),// Net in= Sch: ISH_GPIO11 + BXT_GPIO_PAD_CONF(L"GPIO_30", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00F0, NORTH),// Net in= Sch: ISH_GPIO12 + BXT_GPIO_PAD_CONF(L"GPIO_31", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00F8, NORTH),// Net in= Sch: SUSCLK1 + BXT_GPIO_PAD_CONF(L"GPIO_32", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0100, NORTH),// Net in= Sch: SUSCLK2 + BXT_GPIO_PAD_CONF(L"GPIO_33", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0108, NORTH),// Net in= Sch: ISH_GPIO15, SUSCLK3 + BXT_GPIO_PAD_CONF(L"GPIO_34 PWM0", M0 , GPO , GPIO_D,= HI , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0110, NORTH),//Feature:Power Enable Net in= Sch: USB2_CAM_PWR_EN + BXT_GPIO_PAD_CONF(L"GPIO_35 PWM1", M0 , GPO , GPIO_D,= HI , NA , Wake_Disabled, P_5K_H , NA , NA, NA , = NA, GPIO_PADBAR+0x0118, NORTH),//Feature:Power Enable Net in= Sch: TCH_PNL_PG + BXT_GPIO_PAD_CONF(L"GPIO_36 PWM2", M0 , GPO , GPIO_D,= HI , NA , Wake_Disabled, P_5K_H , NA , NA, NA , = NA, GPIO_PADBAR+0x0120, NORTH),//Feature:Reset Net in= Sch: TCH_PNL_RST_LS_N + BXT_GPIO_PAD_CONF(L"GPIO_38 LPSS_UART0_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx1I,D= isPuPd, GPIO_PADBAR+0x0130, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_39 LPSS_UART0_TXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,Last_Value,D= isPuPd, GPIO_PADBAR+0x0138, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_40 LPSS_UART0_RTS_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,Last_Value,D= isPuPd, GPIO_PADBAR+0x0140, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_41 LPSS_UART0_CTS_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx1I,D= isPuPd, GPIO_PADBAR+0x0148, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_42 LPSS_UART1_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx1I,D= isPuPd, GPIO_PADBAR+0x0150, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_43 LPSS_UART1_TXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I,D= isPuPd, GPIO_PADBAR+0x0158, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_44 LPSS_UART1_RTS_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,Last_Value,D= isPuPd, GPIO_PADBAR+0x0160, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_45 LPSS_UART1_CTS_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_NONE , NA , NA, HizRx0I,D= isPuPd, GPIO_PADBAR+0x0168, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_48 LPSS_UART2_RTS_B", M0 , GPI , GPIO_D,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0180, NORTH),//Not used on RVP + BXT_GPIO_PAD_CONF(L"GPIO_49 LPSS_UART2_CTS_B", M0 , GPI , NA ,= NA , Edge , Wake_Disabled, P_20K_H,Inverted , SMI, NA , = NA, GPIO_PADBAR+0x0188, NORTH),//Feature:SOC_EXTSMI_N Net in= Sch: SOC_EXTSMI_N + BXT_GPIO_PAD_CONF(L"GPIO_62 GP_CAMERASB00", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x0190, NORTH),//CAM_FLASH_RST_N + BXT_GPIO_PAD_CONF(L"GPIO_63 GP_CAMERASB01", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x0198, NORTH),//CAM_FLASH_TORCH + BXT_GPIO_PAD_CONF(L"GPIO_64 GP_CAMERASB02", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x01A0, NORTH),//CAM_FLASH_TRIG + BXT_GPIO_PAD_CONF(L"GPIO_65 GP_CAMERASB03", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x01A8, NORTH),//CAM_GRP1_RST_N + BXT_GPIO_PAD_CONF(L"GPIO_66 GP_CAMERASB04", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x01B0, NORTH),//CAM_GRP2_RST_N + BXT_GPIO_PAD_CONF(L"GPIO_67 GP_CAMERASB05", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x01B8, NORTH),//CAM_GRP3_RST_N + BXT_GPIO_PAD_CONF(L"GPIO_68 GP_CAMERASB06", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x01C0, NORTH),//CAM_GRP4_RST_N + BXT_GPIO_PAD_CONF(L"GPIO_69 GP_CAMERASB07", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x01C8, NORTH),//CAM_XENON_CHRG + BXT_GPIO_PAD_CONF(L"GPIO_70 GP_CAMERASB08", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x01D0, NORTH),//CAM_AFLED_TRIG + BXT_GPIO_PAD_CONF(L"GPIO_71 GP_CAMERASB09", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x01D8, NORTH),//CAM_SPARE + BXT_GPIO_PAD_CONF(L"GPIO_72 GP_CAMERASB10", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x01E0, NORTH),//CAM_SPARE + BXT_GPIO_PAD_CONF(L"GPIO_73 GP_CAMERASB11", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, = NA, GPIO_PADBAR+0x01E8, NORTH),//CAM_SPARE + BXT_GPIO_PAD_CONF(L"TCK", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x01F0, NORTH), + BXT_GPIO_PAD_CONF(L"TRST_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x01F8, NORTH), + BXT_GPIO_PAD_CONF(L"TMS", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0200, NORTH), + BXT_GPIO_PAD_CONF(L"TDI", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0208, NORTH), + BXT_GPIO_PAD_CONF(L"CX_PMODE", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0210, NORTH), + BXT_GPIO_PAD_CONF(L"CX_PREQ_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0218, NORTH), + BXT_GPIO_PAD_CONF(L"JTAGX", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0220, NORTH), + BXT_GPIO_PAD_CONF(L"CX_PRDY_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0228, NORTH), + BXT_GPIO_PAD_CONF(L"TDO", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0230, NORTH), + BXT_GPIO_PAD_CONF(L"CNV_BRI_DT", M0 , GPI , GPIO_D,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0238, NORTH),//Not used on RVP + BXT_GPIO_PAD_CONF(L"GPIO_217 CNV_BRI_RSP", M0 , GPI , GPIO_D,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0240, NORTH),//DGPU_SEL + BXT_GPIO_PAD_CONF(L"GPIO_218 CNV_RGI_DT", M0 , GPO , GPIO_D,= HI , NA , Wake_Disabled, P_1K_H , NA , NA,NA , = NA, GPIO_PADBAR+0x0248, NORTH),//GPS_RESET_N (GNSS_RST_N) + BXT_GPIO_PAD_CONF(L"GPIO_219 CNV_RGI_RSP", M0 , GPO , GPIO_D,= HI , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0250, NORTH),//EMMC Reset + BXT_GPIO_PAD_CONF(L"SVID0_ALERT_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0258, NORTH), + BXT_GPIO_PAD_CONF(L"SVID0_DATA", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0260, NORTH), + BXT_GPIO_PAD_CONF(L"SVID0_CLK", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0268, NORTH), +}; + +// +// North West Community +// +BXT_GPIO_PAD_INIT mUp2_GpioInitData_NW [] =3D +{ + // + // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,G= PO_STATE,INT_Trigger, Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, IO= STerm, MMIO_Offset , Community + // + BXT_GPIO_PAD_CONF(L"GPIO_187 HV_DDI0_DDC_SDA", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx0I , = SAME, GPIO_PADBAR+0x0000, NORTHWEST),//DDI0_CTRL_DATA + BXT_GPIO_PAD_CONF(L"GPIO_188 HV_DDI0_DDC_SCL", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx0I , = SAME, GPIO_PADBAR+0x0008, NORTHWEST),//DDI0_CTRL_CLK + BXT_GPIO_PAD_CONF(L"GPIO_189 HV_DDI1_DDC_SDA", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_2K_H, NA , NA ,NA , = NA, GPIO_PADBAR+0x0010, NORTHWEST),//DDI1_CTRL_DATA + BXT_GPIO_PAD_CONF(L"GPIO_190 HV_DDI1_DDC_SCL", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_2K_H, NA , NA ,NA , = NA, GPIO_PADBAR+0x0018, NORTHWEST),//DDI1_CTRL_CLK + BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M0 , HI_Z ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_H, NA , NA ,NA , = NA, GPIO_PADBAR+0x0020, NORTHWEST),//Feature: SD_I2C MUX SEL Net = in Sch: INA_MUX_SEL // Due to Silicon bug, unable to set GPIO to 1 - change= d to HI_Z + BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M0 , GPO ,GPIO_D, = LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0028, NORTHWEST),//Feature: Codec Power Down PD Net= in Sch: SOC_CODEC_PD_N + BXT_GPIO_PAD_CONF(L"GPIO_193 PANEL0_VDDEN", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I , = SAME, GPIO_PADBAR+0x0030, NORTHWEST),//DISP0_VDDEN + BXT_GPIO_PAD_CONF(L"GPIO_194 PANEL0_BKLTEN", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I , = SAME, GPIO_PADBAR+0x0038, NORTHWEST),//DISP0_BKLTEN + BXT_GPIO_PAD_CONF(L"GPIO_195 PANEL0_BKLTCTL", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I , = SAME, GPIO_PADBAR+0x0040, NORTHWEST),//DISP0_BLTCTL + BXT_GPIO_PAD_CONF(L"GPIO_196 PANEL1_VDDEN", M0 , GPO ,GPIO_D, = LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0048, NORTHWEST),//DISP1_VDDEN + BXT_GPIO_PAD_CONF(L"GPIO_197 PANEL1_BKLTEN", M0 , GPO ,GPIO_D, = LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0050, NORTHWEST),//DISP1_BKLTEN + BXT_GPIO_PAD_CONF(L"GPIO_198 PANEL1_BKLTCTL", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0058, NORTHWEST),//DISP1_BLTCTL + BXT_GPIO_PAD_CONF(L"GPIO_199 DBI_CSX", M2 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,NA , = NA, GPIO_PADBAR+0x0060, NORTHWEST),//HDMI_HPD + BXT_GPIO_PAD_CONF(L"GPIO_200 DBI_RESX", M2 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,NA , = NA, GPIO_PADBAR+0x0068, NORTHWEST),//EDP_HPD + BXT_GPIO_PAD_CONF(L"GPIO_201 GP_INTD_DSI_TE1", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I , = SAME, GPIO_PADBAR+0x0070, NORTHWEST),//DISP_INTD_TE1 + BXT_GPIO_PAD_CONF(L"GPIO_202 GP_INTD_DSI_TE2", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I , = SAME, GPIO_PADBAR+0x0078, NORTHWEST),//DISP_INTD_TE2 + BXT_GPIO_PAD_CONF(L"GPIO_203 USB_OC0_B", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0080, NORTHWEST),//HOST_USB_OC_N + BXT_GPIO_PAD_CONF(L"GPIO_204 USB_OC1_B", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0088, NORTHWEST),//OTG_USB_OC_N, PMIC_GPIO0_P0_UIBT + BXT_GPIO_PAD_CONF(L"PMC_SPI_FS0", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0090, NORTHWEST), + BXT_GPIO_PAD_CONF(L"PMC_SPI_FS1", M2 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0098, NORTHWEST), + BXT_GPIO_PAD_CONF(L"PMC_SPI_FS2", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x00A0, NORTHWEST), + BXT_GPIO_PAD_CONF(L"PMC_SPI_RXD", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x00A8, NORTHWEST), + BXT_GPIO_PAD_CONF(L"PMC_SPI_TXD", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x00B0, NORTHWEST), + BXT_GPIO_PAD_CONF(L"PMC_SPI_CLK", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x00B8, NORTHWEST), + BXT_GPIO_PAD_CONF(L"PMIC_PWRGOOD", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_1K_H , NA , NA ,NA , = NA, GPIO_PADBAR+0x00C0, NORTHWEST),//Feature: Reset Net i= n Sch: GNSS_RST_N + BXT_GPIO_PAD_CONF(L"PMIC_RESET_B", M0 , GPI ,GPIO_D, = NA , NA ,Wake_Disabled, P_NONE , NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x00C8, NORTHWEST),//Not used on RVP + BXT_GPIO_PAD_CONF(L"GPIO_213 PMIC_SDWN_B", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_NONE , NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x00D0, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_214 PMIC_BCUDISW2", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x00D8, NORTHWEST),//Feature: BT WAKE to Device Net i= n Sch: NGFF_BT_DEV_WAKE_N + BXT_GPIO_PAD_CONF(L"GPIO_215 PMIC_BCUDISCRIT", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x00E0, NORTHWEST),//Feature: RF_KILL_GPS Net i= n Sch: RF_KILL_GPS_1P8_N + BXT_GPIO_PAD_CONF(L"PMIC_THERMTRIP_B", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x00E8, NORTHWEST), + BXT_GPIO_PAD_CONF(L"PMIC_STDBY", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x00F0, NORTHWEST),//Feature: WIFI_Disable Net i= n Sch: WIFI_DISABLE1_1P8_N + BXT_GPIO_PAD_CONF(L"PROCHOT_B", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I , = SAME, GPIO_PADBAR+0x00F8, NORTHWEST), + BXT_GPIO_PAD_CONF(L"PMIC_I2C_SCL", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_1K_H , NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0100, NORTHWEST), + BXT_GPIO_PAD_CONF(L"PMIC_I2C_SDA", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_1K_H , NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0108, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_74 AVS_I2S1_MCLK", M0 , GPO ,GPIO_D, = LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0110, NORTHWEST),//Feature:SOC_CS_WAKE Net i= n Sch:SOC_CS_WAKE + BXT_GPIO_PAD_CONF(L"GPIO_75 AVS_I2S1_BCLK", M0 , GPI ,GPIO_D, = NA , Level ,Wake_Disabled, P_20K_L, Inverted,IOAPIC ,TxDRxE , = NA, GPIO_PADBAR+0x0118, NORTHWEST),//Feature:Wake Net i= n Sch:NGFF_CONN_UART_WAKE_N + BXT_GPIO_PAD_CONF(L"GPIO_76 AVS_I2S1_WS_SYNC", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0120, NORTHWEST),//Feature:Wake Net i= n Sch:GNSS_UART_WAKE_N + BXT_GPIO_PAD_CONF(L"GPIO_77 AVS_I2S1_SDI", M0 , GPO ,GPIO_D, = LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0128, NORTHWEST),//Feature:Reset Net i= n Sch:MIPI_DSI_RST_1_8V + BXT_GPIO_PAD_CONF(L"GPIO_78 AVS_I2S1_SDO", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx0I ,D= isPuPd, GPIO_PADBAR+0x0130, NORTHWEST),//Feature:Power enable Net i= n Sch:USB2_WWAN_PWR_EN + BXT_GPIO_PAD_CONF(L"GPIO_79 AVS_M_CLK_A1", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0138, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_80 AVS_M_CLK_B1", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0140, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_81 AVS_M_DATA_1", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,TxDRxE , = EnPd, GPIO_PADBAR+0x0148, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_82 AVS_M_CLK_AB2", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0150, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_83 AVS_M_DATA_2", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,TxDRxE , = EnPd, GPIO_PADBAR+0x0158, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_84 AVS_I2S2_MCLK", M2 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0160, NORTHWEST),//Spare signal, set to GPI. Net i= n Sch:HDA_RSTB + BXT_GPIO_PAD_CONF(L"GPIO_85 AVS_I2S2_BCLK", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0168, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_86 AVS_I2S2_WS_SYNC", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0170, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_87 AVS_I2S2_SDI", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,TxDRxE , = EnPd, GPIO_PADBAR+0x0178, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_88 AVS_I2S2_SDO", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0180, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_89 AVS_I2S3_BCLK", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0188, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_90 AVS_I2S3_WS_SYNC", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x0190, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_91 AVS_I2S3_SDI", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,TxDRxE , = EnPd, GPIO_PADBAR+0x0198, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_92 AVS_I2S3_SDO", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01A0, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_97 FST_SPI_CS0_B", M1 , NA , NA , = NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01A8, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_98 FST_SPI_CS1_B", M1 , NA , NA , = NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01B0, NORTHWEST),//TPM_SPI_CS1 + BXT_GPIO_PAD_CONF(L"GPIO_99 FST_SPI_MOSI_IO0", M1 , NA , NA , = NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01B8, NORTHWEST), //Default for BXT is Native + BXT_GPIO_PAD_CONF(L"GPIO_100 FST_SPI_MISO_IO1",M1 , NA , NA , = NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01C0, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_101 FST_SPI_IO2", M1 , NA , NA , = NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01C8, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_102 FST_SPI_IO3", M1 , NA , NA , = NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01D0, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_103 FST_SPI_CLK", M1 , NA , NA , = NA , NA ,Wake_Disabled, Native_control,NA, NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01D8, NORTHWEST), + BXT_GPIO_PAD_CONF(L"FST_SPI_CLK_FB", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_NONE , NA , NA ,IOS_Masked, = SAME, GPIO_PADBAR+0x01E0, NORTHWEST),//no pin out + BXT_GPIO_PAD_CONF(L"GPIO_104 GP_SSP_0_CLK", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x01E8, NORTHWEST),//no pin out + BXT_GPIO_PAD_CONF(L"GPIO_105 GP_SSP_0_FS0", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x01F0, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_106 GP_SSP_0_FS1", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx0I ,D= isPuPd, GPIO_PADBAR+0x01F8, NORTHWEST),//GP_SSP_0_FS1 + BXT_GPIO_PAD_CONF(L"GPIO_109 GP_SSP_0_RXD", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx0I , = SAME, GPIO_PADBAR+0x0200, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_110 GP_SSP_0_TXD", M1 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0208, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 , GPI ,GPIO_D, = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on RVP + BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0218, NORTHWEST),//Feature: Reset Net = in Sch: FGR_RESET_N + BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M0 , GPI ,GPIO_D, = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0220, NORTHWEST),//Not used on RVP + BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M0 , GPI , NA , = NA , Level ,Wake_Disabled, P_20K_L, NA ,IOAPIC ,TxDRxE , = NA, GPIO_PADBAR+0x0228, NORTHWEST),//Feature: Interrput Net = in Sch: SOC_CODEC_IRQ + BXT_GPIO_PAD_CONF(L"GPIO_117 GP_SSP_1_TXD", M0 , GPO ,GPIO_D, = HI , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0230, NORTHWEST),//Feature: Reset Net = in Sch: NGFF_MODEM_RESET_N + BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0238, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0240, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0248, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0250, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx0I , = SAME, GPIO_PADBAR+0x0258, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_123 GP_SSP_2_TXD", M3 , NA , NA , = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0260, NORTHWEST), +}; + +// +// West Community +// +BXT_GPIO_PAD_INIT mUp2_GpioInitData_W [] =3D +{ + // + // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,= GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L, Inverted,GPI_ROUT,IOSstae, IO= STerm, MMIO_Offset , Community + // + BXT_GPIO_PAD_CONF(L"GPIO_124 LPSS_I2C0_SDA", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0000, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_125 LPSS_I2C0_SCL", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0008, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_126 LPSS_I2C1_SDA", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0010, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_127 LPSS_I2C1_SCL", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0018, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_128 LPSS_I2C2_SDA", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0020, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_129 LPSS_I2C2_SCL", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0028, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_130 LPSS_I2C3_SDA", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0030, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_131 LPSS_I2C3_SCL", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0038, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_132 LPSS_I2C4_SDA", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0040, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_133 LPSS_I2C4_SCL", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0048, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_138 LPSS_I2C7_SDA", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D0RxDRx0I, = EnPu, GPIO_PADBAR+0x0070, WEST),// RFKILL_N + BXT_GPIO_PAD_CONF(L"GPIO_139 LPSS_I2C7_SCL", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D0RxDRx0I, = EnPu, GPIO_PADBAR+0x0078, WEST),//HALL_STATE + BXT_GPIO_PAD_CONF(L"GPIO_146 ISH_GPIO_0", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0080, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_147 ISH_GPIO_1", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0088, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_148 ISH_GPIO_2", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0090, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_149 ISH_GPIO_3", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0098, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_150 ISH_GPIO_4", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00A0, WEST),//Feature: Reset Net in= Sch: NFC_RESET_N + BXT_GPIO_PAD_CONF(L"GPIO_151 ISH_GPIO_5", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00A8, WEST),//Feature: RF_KILL_WWAN Net in= Sch: NGFF_WWAN_RF_KILL_1P8_N + BXT_GPIO_PAD_CONF(L"GPIO_153 ISH_GPIO_7", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00B8, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_154 ISH_GPIO_8", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00C0, WEST),//Feature: BT_Disable Net in= Sch: BT_DISABLE2_1P8_N + BXT_GPIO_PAD_CONF(L"GPIO_155 ISH_GPIO_9", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00C8, WEST),//CG2000 PDB: If PDB =3D 0: power-down; = If PDB =3D 1: power-up, it is the same in ISH/LPSS mode + BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_0", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00F0, WEST), + BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_1", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00F8, WEST), + BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_2", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x0100, WEST), + BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_3", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x0108, WEST), + BXT_GPIO_PAD_CONF(L"OSC_CLK_OUT_4", M0 , GPI ,GPIO_D, = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x0110, WEST),//Not used on RVP + + BXT_GPIO_PAD_CONF(L"PMU_AC_PRESENT", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0118, WEST),//Check, OBS + BXT_GPIO_PAD_CONF(L"PMU_BATLOW_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0120, WEST),//Check, OBS + BXT_GPIO_PAD_CONF(L"PMU_PLTRST_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0128, WEST), + BXT_GPIO_PAD_CONF(L"PMU_PWRBTN_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0130, WEST), + BXT_GPIO_PAD_CONF(L"PMU_RESETBUTTON_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0138, WEST), + BXT_GPIO_PAD_CONF(L"PMU_SLP_S0_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0140, WEST),//Check, OBS + BXT_GPIO_PAD_CONF(L"PMU_SLP_S3_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0148, WEST),//Check, OBS + BXT_GPIO_PAD_CONF(L"PMU_SLP_S4_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0150, WEST), + BXT_GPIO_PAD_CONF(L"PMU_SUSCLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0158, WEST), + BXT_GPIO_PAD_CONF(L"PMU_WAKE_B", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_H, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0160, WEST),//Power cycling for EMMC/RVP + BXT_GPIO_PAD_CONF(L"SUS_STAT_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0168, WEST), + BXT_GPIO_PAD_CONF(L"SUSPWRDNACK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_NONE , NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0170, WEST), +}; + + // + // South West Community + // +BXT_GPIO_PAD_INIT mUp2_GpioInitData_SW[]=3D +{ + // + // Group Pin#: pad_name, PMode,GPIO_Config,HostS= w,GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, = IOSTerm, MMIO_Offset , Community + // + BXT_GPIO_PAD_CONF(L"GPIO_205 PCIE_WAKE0_B", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Maske= d,SAME ,GPIO_PADBAR+0x0000 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_206 PCIE_WAKE1_B", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Maske= d,SAME ,GPIO_PADBAR+0x0008 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_207 PCIE_WAKE2_B", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Maske= d,SAME ,GPIO_PADBAR+0x0010 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_208 PCIE_WAKE3_B", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Maske= d,SAME ,GPIO_PADBAR+0x0018 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_156 EMMC0_CLK", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I= ,SAME ,GPIO_PADBAR+0x0020 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_157 EMMC0_D0", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0028 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_158 EMMC0_D1", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0030 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_159 EMMC0_D2", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0038 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_160 EMMC0_D3", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0040 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_161 EMMC0_D4", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0048 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_162 EMMC0_D5", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0050 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_163 EMMC0_D6", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0058 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_164 EMMC0_D7", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0060 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_165 EMMC0_CMD", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0068 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_166 SDIO_CLK", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,D0RxDRx0I= ,SAME ,GPIO_PADBAR+0x0070 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_167 SDIO_D0", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0078 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_168 SDIO_D1", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0080 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_169 SDIO_D2", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0088 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_170 SDIO_D3", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0090 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_171 SDIO_CMD", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x0098 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_172 SDCARD_CLK", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx1I = ,DisPuPd,GPIO_PADBAR+0x00A0 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_179 SDCARD_CLK_FB", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA = ,NA ,GPIO_PADBAR+0x00A8 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_173 SDCARD_D0", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,DisPuPd,GPIO_PADBAR+0x00B0 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_174 SDCARD_D1", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x00B8 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_175 SDCARD_D2", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x00C0 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_176 SDCARD_D3", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,SAME ,GPIO_PADBAR+0x00C8 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_177 SDCARD_CD_B", M0, GPI , GPIO_D = , NA , Edge ,Wake_Disabled, P_20K_H, NA , NA ,TxDRxE = ,NA ,GPIO_PADBAR+0x00D0 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_178 SDCARD_CMD", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,HizRx1I = ,DisPuPd,GPIO_PADBAR+0x00D8 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_186 SDCARD_LVL_WP", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,Last_Valu= e,SAME ,GPIO_PADBAR+0x00E0 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_182 EMMC0_STROBE", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,HizRx0I = ,SAME ,GPIO_PADBAR+0x00E8 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_183 SDIO_PWR_DOWN_B", M0, GPO , GPIO_D = , LO , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA = ,NA ,GPIO_PADBAR+0x00F0 , SOUTHWEST),// Feature:Power Enable Net in = Sch:SD_CARD_PWR_EN_N + BXT_GPIO_PAD_CONF(L"SMB_ALERTB", M0, GPI , GPIO_D = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Maske= d,SAME ,GPIO_PADBAR+0x00F8 , SOUTHWEST),//not used on RVP +}; + +BXT_GPIO_PAD_INIT mUp2_GpioInitData_Audio_SSP6 []=3D +{ + // + // Group Pin#: pad_name, PMode,GPIO_Config,HostS= w,GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, I= OSTerm,MMIO_Offset, Community + // + BXT_GPIO_PAD_CONF(L"GPIO_146 ISH_GPIO_0", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0080, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_147 ISH_GPIO_1", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0088, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_148 ISH_GPIO_2", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0090, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_149 ISH_GPIO_3", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0098, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_84 AVS_I2S2_MCLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x0160, NORTHWEST),//Spare signal, set to GPI. Net in= Sch:HDA_RSTB + BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M0 , GPI , NA , = NA , Level , Wake_Disabled, P_20K_H, NA ,IOAPIC,TxDRxE , = NA , GPIO_PADBAR+0x0228, NORTHWEST),//Feature: Interrput Net i= n Sch: SOC_CODEC_IRQ + BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M0 , HI_Z ,GPIO_D, = HI , NA , Wake_Disabled, P_2K_H, NA , NA,NA , = NA , GPIO_PADBAR+0x0028, NORTHWEST),//Feature: Codec Power Down PD Net = in Sch: SOC_CODEC_PD_N +}; + +BXT_GPIO_PAD_INIT mUp2_GpioInitData_FAB2[] =3D +{ + // + // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,G= PO_STATE,INT_Trigger, Wake_Enabled ,Term_H_L,Inverted, GPI_ROUT, IOSstae, = IOSTerm, MMIO_Offset ,Community + // + BXT_GPIO_PAD_CONF(L"GPIO_76 AVS_I2S1_WS_SYNC", M0 , GPI ,GPIO_D, = NA , Level , Wake_Disabled, P_20K_L, NA ,IOAPIC, TxDRxE, = NA, GPIO_PADBAR+0x0120, NORTHWEST),//Feature:SSIC_WWAN_Wake + BXT_GPIO_PAD_CONF(L"GPIO_6", M0 , GPI ,GPIO_D, = NA , Level , Wake_Disabled, P_20K_L, NA ,IOAPIC, TxDRxE, = NA, GPIO_PADBAR+0x0030, NORTH), //Feature:DGPU Power OK + BXT_GPIO_PAD_CONF(L"GPIO_217 CNV_BRI_RSP", M0 , GPO ,GPIO_D, = LO , NA , Wake_Disabled, P_20K_L, NA , NA, NA, = NA, GPIO_PADBAR+0x0240, NORTH), //Feature:DGPU_SEL +}; + +// +// GPIO 191 is only used if EPI reworks are applied on the board. This GPI= O switches between SD Card data (if set to 1) and EPI data (if set to 0). +// +BXT_GPIO_PAD_INIT mUp2_GpioInitData_EPI_Override[] =3D +{ + // + // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,G= PO_STATE,INT_Trigger, Wake_Enabled ,Term_H_L,Inverted, GPI_ROUT, IOSstae, = IOSTerm, MMIO_Offset ,Community + // + BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M0, GPO, GPIO_D,L= O, NA, Wake_Disabled,P_20K_L, NA, NA, NA, = NA, GPIO_PADBAR + 0x0020, NORTHWEST),//Feature: SD_I2C MUX SEL = Net in Sch: INA_MUX_SEL +}; + +// +// North West Community +// +BXT_GPIO_PAD_INIT mUp2_GpioInitData_NW_LH []=3D +{ + // + // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,G= PO_STATE,INT_Trigger, Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, IO= STerm, MMIO_Offset, Community + // + BXT_GPIO_PAD_CONF(L"GPIO_74 AVS_I2S1_MCLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0110, NORTHWEST),//Feature:AVS_I2S1_MCLK + BXT_GPIO_PAD_CONF(L"GPIO_75 AVS_I2S1_BCLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0118, NORTHWEST),//Feature:AVS_I2S1_BCLK + BXT_GPIO_PAD_CONF(L"GPIO_77 AVS_I2S1_SDI", M0 , GPI , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0128, NORTHWEST),//Feature:LPE Hdr + BXT_GPIO_PAD_CONF(L"GPIO_78 AVS_I2S1_SDO", M0 , GPI , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0130, NORTHWEST),//Feature:LPE Hdr + BXT_GPIO_PAD_CONF(L"GPIO_79 AVS_M_CLK_A1", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0138, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_80 AVS_M_CLK_B1", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0140, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_81 AVS_M_DATA_1", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,TxDRxE , = EnPd, GPIO_PADBAR+0x0148, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_82 AVS_M_CLK_AB2", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0150, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_104 GP_SSP_0_CLK", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x01E8, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_105 GP_SSP_0_FS0", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x01F0, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_106 GP_SSP_0_FS1", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x01F8, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_109 GP_SSP_0_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x0200, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_110 GP_SSP_0_TXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x0208, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0218, NORTHWEST),//Feature: LPSS UART Hdr + BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0228, NORTHWEST),//Feature: LPSS UART Hdr + BXT_GPIO_PAD_CONF(L"GPIO_117 GP_SSP_1_TXD", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0230, NORTHWEST),//Feature: LPSS UART Hdr + BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0020, NORTHWEST),//Feature: DBI_SDA + BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0028, NORTHWEST),//Feature: DBI_SCL + BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0238, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0240, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0248, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0250, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0258, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_123 GP_SSP_2_TXD", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0260, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_196 PANEL1_VDDEN", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0048, NORTHWEST),//DISP1_VDDEN + BXT_GPIO_PAD_CONF(L"GPIO_197 PANEL1_BKLTEN", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0050, NORTHWEST),//DISP1_BKLTEN + BXT_GPIO_PAD_CONF(L"GPIO_198 PANEL1_BKLTCTL", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0058, NORTHWEST),//DISP1_BLTCTL + BXT_GPIO_PAD_CONF(L"GPIO_84 AVS_I2S2_MCLK", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0160, NORTHWEST),//Spare signal, set to GPI. Net i= n Sch:HDA_RSTB + BXT_GPIO_PAD_CONF(L"GPIO_85 AVS_I2S2_BCLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0168, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_86 AVS_I2S2_WS_SYNC", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0170, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_87 AVS_I2S2_SDI", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0178, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_88 AVS_I2S2_SDO", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0180, NORTHWEST), +}; + + +BXT_GPIO_PAD_INIT mUp2_GpioInitData_N_LH[] =3D +{ + // + // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,G= PO_STATE,INT_Trigger, Wake_Enabled ,Term_H_L,Inverted, GPI_ROUT, IOSstae, = IOSTerm,MMIO_Offset,Community + // + BXT_GPIO_PAD_CONF(L"GPIO_9", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0048, NORTH),//Feature:LB + BXT_GPIO_PAD_CONF(L"GPIO_11", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0058, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_12", M1 , NA , NA ,= NA , NA , Wake_Enabled , P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0060, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_13", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0068, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_14", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0070, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_15", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0078, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_17", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0088, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_18", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0090, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_19", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0098, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_20", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00A0, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_21", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00A8, NORTH),//Feature: LB + BXT_GPIO_PAD_CONF(L"GPIO_23", M0 , GPO , NA , = HI , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x00B8, NORTH),//Feature: LB USB Power in LFH + BXT_GPIO_PAD_CONF(L"GPIO_31", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00F8, NORTH),//Feature: SUSCLK1 + BXT_GPIO_PAD_CONF(L"GPIO_33", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0108, NORTH),//Feature: SUSCLK3 + BXT_GPIO_PAD_CONF(L"GPIO_34 PWM0", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0110, NORTH),//Feature: PWM + BXT_GPIO_PAD_CONF(L"GPIO_36 PWM2", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0120, NORTH),//Feature: PWM + BXT_GPIO_PAD_CONF(L"GPIO_49 LPSS_UART2_CTS_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0188, NORTH),//Feature: LPSS_UART1 +}; + +// +// West Community +// +BXT_GPIO_PAD_INIT mUp2_GpioInitData_W_LH [] =3D +{ + // + // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,= GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L, Inverted,GPI_ROUT,IOSstae, IO= STerm, MMIO_Offset, Community + // + BXT_GPIO_PAD_CONF(L"GPIO_150 ISH_GPIO_4", M2 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00A0, WEST),//Feature: AVS_I2S5_BCLK + BXT_GPIO_PAD_CONF(L"GPIO_152 ISH_GPIO_6", M2 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+ 0x00B0, WEST),//Feature: AVS_I2S5_SDI + BXT_GPIO_PAD_CONF(L"GPIO_209 PCIE_CLKREQ0_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_NONE, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00D0, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_210 PCIE_CLKREQ1_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00D8, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_211 PCIE_CLKREQ2_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00E0, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_212 PCIE_CLKREQ3_B", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA, HizRx0I, E= nPd, GPIO_PADBAR+0x00E8, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_146 ISH_GPIO_0", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0080, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_147 ISH_GPIO_1", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0088, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_148 ISH_GPIO_2", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0090, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_149 ISH_GPIO_3", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0098, WEST), +}; + + // + // South West Community + // +BXT_GPIO_PAD_INIT mUp2_GpioInitData_SW_LH []=3D +{ + // + // Group Pin#: pad_name, PMode,GPIO_Config,HostS= w,GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L,Inverted,GPI_ROUT,IOSstae, I= OSTerm,MMIO_Offset, Community + // + BXT_GPIO_PAD_CONF(L"GPIO_177 SDCARD_CD_B", M0, GPI , GPIO_D = , NA , Edge ,Wake_Disabled, P_NONE, NA , NA ,TxDRxE = , NA, GPIO_PADBAR+ 0x00D0 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_186 SDCARD_LVL_WP", M0, GPI , GPIO_D = , NA , Edge ,Wake_Disabled, P_20K_L,Inverted , NA ,Last_Valu= e, SAME,GPIO_PADBAR+ 0x00E0 , SOUTHWEST), + BXT_GPIO_PAD_CONF(L"SMB_ALERTB", M1, NA , NA = , NA , NA ,Wake_Disabled, P_20K_H, NA , NA ,IOS_Maske= d, SAME, GPIO_PADBAR+ 0x00F8 , SOUTHWEST),//Feature: SMB_ALERTB +}; + +BXT_GPIO_PAD_INIT mUp2_GpioInitData_LPSS_I2C[] =3D +{ + BXT_GPIO_PAD_CONF(L"GPIO_134 LPSS_I2C5_SDA", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I, = EnPd, GPIO_PADBAR+0x0050, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_135 LPSS_I2C5_SCL", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I, = EnPd, GPIO_PADBAR+0x0058, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_136 LPSS_I2C6_SDA", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I, = EnPd, GPIO_PADBAR+0x0060, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_137 LPSS_I2C6_SCL", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx0I, = EnPd, GPIO_PADBAR+0x0068, WEST), +}; + +BXT_GPIO_PAD_INIT Up2LomDisableGpio[] =3D +{ + // + // LAN + // + BXT_GPIO_PAD_CONF(L"GPIO_210 PCIE_CLKREQ1_B", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x00D8, WEST), // CLKREQ# + BXT_GPIO_PAD_CONF(L"GPIO_37 PWM3", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0128, NORTH), // PERST# +}; + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardIn= it.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c new file mode 100644 index 0000000000..6228285911 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.c @@ -0,0 +1,190 @@ +/** @file + Board Init driver. + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include "BoardInit.h" +#include "BoardInitMiscs.h" +#include "HdaVerbTables.h" + +EFI_STATUS +EFIAPI +Up2PostMemInitCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + + +static EFI_PEI_NOTIFY_DESCRIPTOR mUp2PostMemNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gBoardPostMemInitStartGuid, + Up2PostMemInitCallback +}; + +static EFI_PEI_PPI_DESCRIPTOR mUp2PostMemDonePpi =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gBoardPostMemInitDoneGuid, + NULL +}; + +EFI_STATUS +EFIAPI +Up2PostMemInitCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + VOID *Instance; + UINT8 BoardId; + UINT8 FabId; + UINT8 ResetType; + UINTN BufferSize; + UINT8 MaxPkgCState; + UINTN VariableSize; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + SYSTEM_CONFIGURATION SystemConfiguration; + + VariableSize =3D sizeof (SYSTEM_CONFIGURATION); + ZeroMem (&SystemConfiguration, sizeof (SYSTEM_CONFIGURATION)); + + (*PeiServices)->LocatePpi ( + (CONST EFI_PEI_SERVICES **)PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **) &VariableServices + ); + + VariableServices->GetVariable ( + VariableServices, + PLATFORM_SETUP_VARIABLE_NAME, + &gEfiSetupVariableGuid, + NULL, + &VariableSize, + &SystemConfiguration + ); + + Status =3D PeiServicesLocatePpi ( + &gBoardPostMemInitDoneGuid, + 0, + NULL, + &Instance + ); + if (!EFI_ERROR (Status)) { + return EFI_SUCCESS; + } + + BoardId =3D (UINT8) PcdGet8 (PcdBoardId); + FabId =3D (UINT8) PcdGet8 (PcdFabId); + DEBUG ((EFI_D_INFO, "PostMemInit: BoardId =3D=3D 0x%X, FabId =3D=3D 0x%= X\n", BoardId, FabId)); + if (BoardId !=3D (UINT8) BOARD_ID_UP2) {//MyBoardPorting + return EFI_SUCCESS; + } + + DEBUG ((EFI_D_INFO, "Up2 Post Mem Init callback\n")); + + // + // Set init function PCD + // + PcdSet64 (PcdBoardPostMemInitFunc, (UINT64) (UINTN) Up2MultiPlatformInfo= Init); + =20 + // + // Set Reset Type according to different Board + // + ResetType =3D V_RST_CNT_FULLRESET; + PcdSet8 (PcdResetType, (UINT8) ResetType); + + // + // Board specific VBT table. + // + BufferSize =3D sizeof (EFI_GUID); + PcdSetPtr(PcdBoardVbtFileGuid, &BufferSize, (UINT8 *)&gPeiUp2VbtGuid); + =20 + // + // Set PcdSueCreek + // + PcdSetBool (PcdSueCreek, FALSE); + + // + // Set PcdMaxPkgCState + // + MaxPkgCState =3D MAX_PKG_CSTATE_C2; + PcdSet8 (PcdMaxPkgCState, (UINT8) MaxPkgCState); + =20 + // + // Set PcdeMMCHostMaxSpeed + // + PcdSet8 (PcdeMMCHostMaxSpeed, (UINT8) (SystemConfiguration.ScceMMCHostMa= xSpeed)); + + // + // HDA audio verb table + // + PcdSet64 (PcdHdaVerbTablePtr, (UINT64) (UINTN) &HdaVerbTableAlc662); + PcdSet8(HdaVerbTableEntryNum, 1); + + // + // I2S NHLT Virtual Bus ID + // + PcdSet8(HdaEndpointBtRenderVirtualBusId, 2); //I2S3 + PcdSet8(HdaEndpointBtCaptureVirtualBusId, 2); //I2S3 + PcdSet8(HdaEndpointI2sRenderSKPVirtualBusId, 5); //I2S6 + PcdSet8(HdaEndpointI2sRenderHPVirtualBusId, 5); //I2S6 + PcdSet8(HdaEndpointI2sCaptureVirtualBusId, 5); //I2S6 + =20 + // + // Add init steps here + // + // + // Install a flag signalling a board's post mem init is done + // + Status =3D PeiServicesInstallPpi (&mUp2PostMemDonePpi); + + return EFI_SUCCESS; +} + + +/** + This function performs Board initialization in Pre-Memory. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of me= mory). + +**/ +EFI_STATUS +EFIAPI +Up2InitConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + DEBUG ((EFI_D_INFO, "Up2 Post Mem Init Constructor \n")); + + DEBUG ((EFI_D_INFO, "Notify on Post Mem Init Start PPI \n")); + Status =3D PeiServicesNotifyPpi (&mUp2PostMemNotifyList); + + return Status; +} + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardIn= it.h b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.h new file mode 100644 index 0000000000..7f32f0085e --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInit.h @@ -0,0 +1,30 @@ +/** @file + GPIO setting for CherryView. + This file includes package header files, library classes. + + Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _MYBOARD_BOARDINIT_H_ +#define _MYBOARD_BOARDINIT_H_ + +#include +#include +#include +#include +#include +#include + +VOID Up2GpioTest (VOID); + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardIn= itMiscs.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardIni= tMiscs.c new file mode 100644 index 0000000000..564e2312f6 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitMiscs= .c @@ -0,0 +1,179 @@ +/** @file + This file does Multiplatform initialization. + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "BoardInitMiscs.h" + +/** + Configure GPIO group GPE tier. + + @param[in] PlatformInfo + + @retval none. + +**/ +VOID +Up2GpioGroupTierInit ( + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ) +{ + DEBUG ((DEBUG_INFO, "Up2GpioGroupTierInit Start\n")); + switch (PlatformInfoHob->BoardId) { + default: + GpioSetGroupToGpeDwX (GPIO_BXTP_GROUP_7, // map group 7 to GPE 0 ~ = 31 + GPIO_BXTP_GROUP_0, // map group 0 to GPE 32 ~= 63 // We don't have SCI pin in Group0 as of now, but still need to assign = a unique group to this field. + GPIO_BXTP_GROUP_1); // map group 1 to GPE 64 ~= 95 // We don't have SCI pin in Group1 as of now, but still need to assign = a unique group to this field. + break; + } + + DEBUG ((DEBUG_INFO, "Up2GpioGroupTierInit End\n")); +} + + +EFI_STATUS +EFIAPI +Up2MultiPlatformInfoInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ) +{ + EFI_STATUS Status; + +#if (ENBDT_PF_ENABLE =3D=3D 1) + DEBUG ((EFI_D_INFO, "Platform BoardId:%x FabId%x\n", PlatformInfoHob->B= oardId, PlatformInfoHob->FABID)); +#endif + + // + // Device ID + // + PlatformInfoHob->IohSku =3D MmPci16 (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN,= PCI_DEVICE_ID_OFFSET); + PlatformInfoHob->IohRevision =3D MmPci8 (0, SA_MC_BUS, SA_MC_DEV, SA_MC_= FUN, PCI_REVISION_ID_OFFSET); + + // + // Don't support BASE above 4GB currently + // + PlatformInfoHob->PciData.PciExpressSize =3D 0x04000000; + PlatformInfoHob->PciData.PciExpressBase =3D (UINTN) PcdGet64 (PcdPci= ExpressBaseAddress); + + PlatformInfoHob->PciData.PciResourceMem32Base =3D (UINT32) (PlatformInf= oHob->PciData.PciExpressBase - RES_MEM32_MIN_LEN); + PlatformInfoHob->PciData.PciResourceMem32Limit =3D (UINT32) (PlatformInf= oHob->PciData.PciExpressBase -1); + + PlatformInfoHob->PciData.PciResourceMem64Base =3D RES_MEM64_36_BASE; + PlatformInfoHob->PciData.PciResourceMem64Limit =3D RES_MEM64_36_LIMIT; + PlatformInfoHob->CpuData.CpuAddressWidth =3D 36; + + PlatformInfoHob->MemData.MemMir0 =3D PlatformInfoHob->PciData.PciResourc= eMem64Base; + PlatformInfoHob->MemData.MemMir1 =3D PlatformInfoHob->PciData.PciResourc= eMem64Limit + 1; + + PlatformInfoHob->PciData.PciResourceMinSecBus =3D 1; //can be changed = by SystemConfiguration->PciMinSecondaryBus; + + // + // Set MemMaxTolm to the lowest address between PCIe Base and PCI32 Base + // + if (PlatformInfoHob->PciData.PciExpressBase > PlatformInfoHob->PciData.P= ciResourceMem32Base ) { + PlatformInfoHob->MemData.MemMaxTolm =3D (UINT32) PlatformInfoHob->PciD= ata.PciResourceMem32Base; + } else { + PlatformInfoHob->MemData.MemMaxTolm =3D (UINT32) PlatformInfoHob->PciD= ata.PciExpressBase; + } + PlatformInfoHob->MemData.MemTolm =3D PlatformInfoHob->MemData.MemMaxTolm; + + // + // Platform PCI MMIO Size in unit of 1MB + // + PlatformInfoHob->MemData.MmioSize =3D 0x1000 - (UINT16) (PlatformInfoHob= ->MemData.MemMaxTolm >> 20); + + // + // Enable ICH IOAPIC + // + PlatformInfoHob->SysData.SysIoApicEnable =3D ICH_IOAPIC; + + DEBUG ((EFI_D_INFO, "PlatformFlavor is %x (%x=3Dtablet,%x=3Dmobile,%x= =3Ddesktop)\n", PlatformInfoHob->PlatformFlavor, FlavorTablet, FlavorMobile= , FlavorDesktop)); + + // + // Get Platform Info and fill the Hob + // + PlatformInfoHob->RevisonId =3D PLATFORM_INFO_HOB_REVISION; + + // + // Get GPIO table + // + Status =3D Up2MultiPlatformGpioTableInit (PeiServices, PlatformInfoHob); + ASSERT_EFI_ERROR (Status); + + // + // Program GPIO + // + Status =3D Up2MultiPlatformGpioProgram (PeiServices, PlatformInfoHob); + + if (GetBxtSeries () =3D=3D BxtP) { + Up2GpioGroupTierInit (PlatformInfoHob); + } + + // + // Update OemId + // + Status =3D Up2InitializeBoardOemId (PeiServices, PlatformInfoHob); + Status =3D Up2InitializeBoardSsidSvid (PeiServices, PlatformInfoHob); + + return EFI_SUCCESS; +} + + +EFI_STATUS +Up2InitializeBoardOemId ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ) +{ + UINT64 OemId; + UINT64 OemTableId; + + // + // Set OEM ID according to Board ID. + // + switch (PlatformInfoHob->BoardId) { + default: + OemId =3D EFI_ACPI_OEM_ID_DEFAULT; + OemTableId =3D EFI_ACPI_OEM_TABLE_ID_DEFAULT; + break; + } + + PlatformInfoHob->AcpiOemId =3D OemId; + PlatformInfoHob->AcpiOemTableId =3D OemTableId; + + return EFI_SUCCESS; +} + + +EFI_STATUS +Up2InitializeBoardSsidSvid ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ) +{ + UINT32 SsidSvidValue =3D 0; + + // + // Set OEM ID according to Board ID. + // + switch (PlatformInfoHob->BoardId) { + default: + SsidSvidValue =3D SUBSYSTEM_SVID_SSID;//SUBSYSTEM_SVID_SSID_DEFAULT; + break; + } + PlatformInfoHob->SsidSvid =3D SsidSvidValue; + + return EFI_SUCCESS; +} + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardIn= itMiscs.h b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardIni= tMiscs.h new file mode 100644 index 0000000000..281b278dde --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitMiscs= .h @@ -0,0 +1,132 @@ +/** @file + Multiplatform initialization header file. + This file includes package header files, library classes. + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _MYBOARD_MULTIPLATFORM_LIB_H_ +#define _MYBOARD_MULTIPLATFORM_LIB_H_ + +#define LEN_64M 0x4000000 +// +// Default PCI32 resource size +// +#define RES_MEM32_MIN_LEN 0x38000000 + +#define RES_IO_BASE 0x0D00 +#define RES_IO_LIMIT 0xFFFF +#include +#include +#include +#include "PlatformBaseAddresses.h" +#include "ScAccess.h" +#include "SetupMode.h" +#include "PlatformBootMode.h" +#include "CpuRegs.h" +#include "Platform.h" +#include "CMOSMap.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EFI_ACPI_OEM_ID_DEFAULT SIGNATURE_64('I', 'N', 'T', 'E', 'L', '= ', ' ', ' ') // max 6 chars +#define EFI_ACPI_OEM_ID1 SIGNATURE_64('I', 'N', 'T', 'E', 'L', '= 1', ' ', ' ') // max 6 chars +#define EFI_ACPI_OEM_ID2 SIGNATURE_64('I', 'N', 'T', 'E', 'L', '= 2', ' ', ' ') // max 6 chars + +#define EFI_ACPI_OEM_TABLE_ID_DEFAULT SIGNATURE_64('E', 'D', 'K', '2', '= ', ' ', ' ', ' ') +#define EFI_ACPI_OEM_TABLE_ID1 SIGNATURE_64('E', 'D', 'K', '2', '= _', '1', ' ', ' ') +#define EFI_ACPI_OEM_TABLE_ID2 SIGNATURE_64('E', 'D', 'K', '2', '= _', '2', ' ', ' ') + +// +// Default Vendor ID and Subsystem ID +// +#define SUBSYSTEM_VENDOR_ID1 0x8086 +#define SUBSYSTEM_DEVICE_ID1 0x1999 +#define SUBSYSTEM_SVID_SSID1 (SUBSYSTEM_VENDOR_ID1 + (SUBSYSTEM_DEVICE_I= D1 << 16)) + +#define SUBSYSTEM_VENDOR_ID2 0x8086 +#define SUBSYSTEM_DEVICE_ID2 0x1888 +#define SUBSYSTEM_SVID_SSID2 (SUBSYSTEM_VENDOR_ID2 + (SUBSYSTEM_DEVICE_I= D2 << 16)) + +#define SUBSYSTEM_VENDOR_ID 0x8086 +#define SUBSYSTEM_DEVICE_ID 0x1234 +#define SUBSYSTEM_SVID_SSID (SUBSYSTEM_VENDOR_ID + (SUBSYSTEM_DEVICE_ID = << 16)) + +// +// MaxPkgCState identifier. +// +#define MAX_PKG_CSTATE_C0 0x00 +#define MAX_PKG_CSTATE_C1 0x01 +#define MAX_PKG_CSTATE_C2 0x02 +EFI_STATUS +Up2GetPlatformInfoHob ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob + ); + +EFI_STATUS +Up2MultiPlatformGpioTableInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ); + +EFI_STATUS +Up2MultiPlatformGpioProgram ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ); + +EFI_STATUS +Up2MultiPlatformInfoInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ); + +EFI_STATUS +Up2InitializeBoardOemId ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ); + +EFI_STATUS +Up2InitializeBoardSsidSvid ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PLATFORM_INFO_HOB *PlatformInfoHob + ); + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardIn= itPostMem.inf b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/Boar= dInitPostMem.inf new file mode 100644 index 0000000000..4468894483 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/BoardInitPostM= em.inf @@ -0,0 +1,93 @@ +## @file +# Board detected module for Intel(R) Atom(TM) x5 Processor Series. +# +# It will detect the board ID. +# +# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D Up2InitPostMem + FILE_GUID =3D E46D7025-D587-4998-B874-26EA7F469CE4 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + CONSTRUCTOR =3D Up2InitConstructor + +[Sources] + BoardInit.c + BoardInit.h + BoardInitMiscs.c + BoardInitMiscs.h + PlatformInfoHob.c + BoardGpios.c + BoardGpios.h + HdaVerbTables.c + +[LibraryClasses] + PeiServicesLib + PcdLib + DebugLib + HeciMsgLib + HobLib + IoLib + SteppingLib + GpioLib + +[Packages] + MdePkg/MdePkg.dec + BroxtonPlatformPkg/PlatformPkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + SecurityPkg/SecurityPkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid + gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress + gPlatformModuleTokenSpaceGuid.PcdBoardPostMemInitFunc + gPlatformModuleTokenSpaceGuid.PcdBoardId + gPlatformModuleTokenSpaceGuid.PcdFabId + gPlatformModuleTokenSpaceGuid.PcdResetType + gPlatformModuleTokenSpaceGuid.PcdBoardVbtFileGuid + gPlatformModuleTokenSpaceGuid.PcdSueCreek + gPlatformModuleTokenSpaceGuid.PcdMaxPkgCState + gPlatformModuleTokenSpaceGuid.PcdeMMCHostMaxSpeed + gPlatformModuleTokenSpaceGuid.PcdHdaVerbTablePtr + gPlatformModuleTokenSpaceGuid.HdaVerbTableEntryNum + gEfiBxtTokenSpaceGuid.HdaEndpointBtRenderVirtualBusId + gEfiBxtTokenSpaceGuid.HdaEndpointBtCaptureVirtualBusId + gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderSKPVirtualBusId + gEfiBxtTokenSpaceGuid.HdaEndpointI2sRenderHPVirtualBusId + gEfiBxtTokenSpaceGuid.HdaEndpointI2sCaptureVirtualBusId + =20 +[Guids] + gEfiPlatformInfoGuid + gEfiAuthenticatedVariableGuid + gEfiVariableGuid + gPeiVariableCacheHobGuid + gEfiTpmDeviceSelectedGuid + gEfiTpmDeviceInstanceNoneGuid + gEfiTpmDeviceInstanceTpm12Guid + gEfiTpmDeviceInstanceTpm20DtpmGuid + gTpmDeviceInstanceTpm20PttPtpGuid + gPeiUp2VbtGuid + +[Ppis] + gBoardPostMemInitStartGuid + gBoardPostMemInitDoneGuid + gEfiPeiReadOnlyVariable2PpiGuid + gSeCfTPMPolicyPpiGuid + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/HdaVerb= Tables.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/HdaVerbTa= bles.c new file mode 100644 index 0000000000..69cd29ad9a --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/HdaVerbTables.c @@ -0,0 +1,145 @@ +/** @file + HD Audio Verb Table. + + Copyright (c) 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "HdaVerbTables.h" + +HDAUDIO_VERB_TABLE HdaVerbTableAlc662 =3D { + { + 0x10EC0662, // Vendor ID / Device ID + 0xFF, // Revision ID + 0xFF, // SDI number, 0xFF matches any SDI. + 15 * 4 // Number of data DWORDs following the header. + }, + { + + 0x00172000, + 0x00172100, + 0x00172286, + 0x00172380, + + // + // Pin Widget Verb-table + // Widget node 0x01 : + // + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + + // + // Pin widget 0x12 - DMIC + // + 0x01271C00, + 0x01271D00, + 0x01271E13, + 0x01271F40, + + // + // Pin widget 0x14 - FRONT (Port-D) + // + 0x01471C10, + 0x01471D40, + 0x01471E01, + 0x01471F01, + + // + // Pin widget 0x15 - SURR (Port-A) + // + 0x01571C12, + 0x01571D10, + 0x01571E01, + 0x01571F01, + + // + // Pin widget 0x16 - CEN/LFE (Port-G) + // + 0x01671C11, + 0x01671D60, + 0x01671E01, + 0x01671F01, + + // + // Pin widget 0x18 - MIC1 (Port-B) + // + 0x01871C30, + 0x01871D90, + 0x01871EA1, + 0x01871F01, + + // + // Pin widget 0x19 - MIC2 (Port-F) + // + 0x01971C40, + 0x01971D90, + 0x01971EA1, + 0x01971F02, + + // + // Pin widget 0x1A - LINE1 (Port-C) + // + 0x01A71C3F, + 0x01A71D30, + 0x01A71E81, + 0x01A71F01, + + // + // Pin widget 0x1B - LINE2 (Port-E) + // + 0x01B71C1F, + 0x01B71D40, + 0x01B71E21, + 0x01B71F02, + + // + // Pin widget 0x1C - CD-IN + // + 0x01C71CF0, + 0x01C71D11, + 0x01C71E11, + 0x01C71F41, + + // + // Pin widget 0x1D - BEEP-IN + // + 0x01D71C01, + 0x01D71DE6, + 0x01D71E45, + 0x01D71F40, + + // + // Pin widget 0x1E - S/PDIF-OUT + // + 0x01E71C20, + 0x01E71D11, + 0x01E71E44, + 0x01E71F01, + + // + // Widget node 0x20 : + // + 0x02050004, + 0x02040001, + 0x02050004, + 0x02040001, + + // + // Widget node 0x20 - 1 : + // + 0x02050005, + 0x02040080, + 0x02050001, + 0x0204A9B8 + } +}; diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/HdaVerb= Tables.h b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/HdaVerbTa= bles.h new file mode 100644 index 0000000000..4261f789cb --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/HdaVerbTables.h @@ -0,0 +1,38 @@ +/** @file + HD Audio Verb Table header file. + This file includes package header files, library classes. + + Copyright (c) 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _HDA_VERBTABLES_H_ +#define _HDA_VERBTABLES_H_ + +#pragma pack (push,1) + + +typedef struct { + UINT32 VendorDeviceId; ///< Codec Vendor/Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matche= s any revision. + UINT8 SdiNo; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs following the h= eader. +} HDA_VERB_TABLE_HEADER; + +typedef struct { + HDA_VERB_TABLE_HEADER VerbTableHeader; + UINT32 VerbTableData[]; +} HDAUDIO_VERB_TABLE; +#pragma pack (pop) + +extern HDAUDIO_VERB_TABLE HdaVerbTableAlc662; + +#endif // _HDA_VERBTABLES_H_ diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/Platfor= mInfoHob.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/Platfor= mInfoHob.c new file mode 100644 index 0000000000..e2058db579 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPostMem/PlatformInfoHo= b.c @@ -0,0 +1,59 @@ +/** @file + This file does Multiplatform initialization. + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "BoardInitMiscs.h" + + +/** + Returns the Platform Info of the platform from the HOB. + + @param[in] PeiServices General purpose services available to = every PEIM. + @param[in] PlatformInfoHob Pointer to the PLATFORM_INFO_HOB Point= er. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND PlatformInfoHob data doesn't exist, us= e default instead. + +**/ +EFI_STATUS +Up2GetPlatformInfoHob ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob + ) +{ + EFI_PEI_HOB_POINTERS GuidHob; + + // + // Find the PlatformInfo HOB + // + GuidHob.Raw =3D GetHobList (); + if (GuidHob.Raw =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + if ((GuidHob.Raw =3D GetNextGuidHob (&gEfiPlatformInfoGuid, GuidHob.Raw)= ) !=3D NULL) { + *PlatformInfoHob =3D GET_GUID_HOB_DATA (GuidHob.Guid); + } + + // + // PlatformInfo PEIM should provide this HOB data, if not ASSERT and ret= urn error. + // + ASSERT_EFI_ERROR (*PlatformInfoHob !=3D NULL); + if (!(*PlatformInfoHob)) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardIni= t.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInit.c new file mode 100644 index 0000000000..ef451894b2 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInit.c @@ -0,0 +1,180 @@ +/** @file + Board Init driver. + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include "BoardInit.h" +#include "PlatformId.h" +#include "BoardInitMiscs.h" + +EFI_STATUS +EFIAPI +Up2PreMemInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_BOARD_PRE_MEM_INIT_PPI *This + ); + +static PEI_BOARD_PRE_MEM_INIT_PPI mUp2PreMemInitPpiInstance =3D { + Up2PreMemInit +}; + +static EFI_PEI_PPI_DESCRIPTOR mUp2PreMemInitPpi =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gBoardPreMemInitPpiGuid, + &mUp2PreMemInitPpiInstance +}; + +static EFI_PEI_PPI_DESCRIPTOR mUp2PreMemInitDonePpi =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gBoardPreMemInitDoneGuid, + NULL +}; + +EFI_STATUS +EFIAPI +Up2PreMemInit ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_BOARD_PRE_MEM_INIT_PPI *This + ) +{ + EFI_STATUS Status; + VOID *Instance; + UINT8 BoardId; + UINT8 FabId; + + BoardId =3D 0; + FabId =3D 0; + Status =3D PeiServicesLocatePpi ( + &gBoardPreMemInitDoneGuid, + 0, + NULL, + &Instance + ); + if (!EFI_ERROR (Status)) { + return EFI_SUCCESS; + } + + // + // Pre Mem Board Init + // + Status =3D Up2GetEmbeddedBoardIdFabId (PeiServices, &BoardId, &FabId); + if (BoardId !=3D (UINT8) BOARD_ID_UP2) {//MyBoardPorting + return EFI_SUCCESS; + } + + DEBUG ((EFI_D_INFO, "This is Up2.\n")); + + PcdSet8 (PcdBoardId, BoardId); + PcdSet8 (PcdFabId, FabId); + + // + // Set board specific function as dynamic PCD to be called by common pla= tform code + // + PcdSet64 (PcdUpdateFspmUpdFunc, (UINT64) (UINTN) mUp2UpdateFspmUpdPtr); + PcdSet64 (PcdDramCreatePolicyDefaultsFunc, (UINT64) (UINTN) mUp2DramCrea= tePolicyDefaultsPtr); + + // + // Install a flag signalling a board is detected and pre-mem init is done + // + Status =3D PeiServicesInstallPpi (&mUp2PreMemInitDonePpi); + + return EFI_SUCCESS; +} + + +/** + This function performs Board initialization in Pre-Memory. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES No enough resoruces (such as out of me= mory). + +**/ +EFI_STATUS +EFIAPI +Up2InitConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + VOID *Ppi; + EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor; + UINTN Instance; + + DEBUG ((EFI_D_INFO, "Up2 Pre Mem Init Constructor \n")); + + Status =3D PeiServicesLocatePpi ( + &gBoardPreMemInitDoneGuid, + 0, + &PeiPpiDescriptor, + &Ppi + ); + if (!EFI_ERROR (Status)) { + // + // Board detection previously done, so this is a re-invocation shadowe= d in memory. + // Reinstall PPIs to eliminate PPI descriptors in torn down temp RAM. + // + // + // Reinstall PreMemInit Done PPI + // + DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init Done PPI\n")); + Status =3D PeiServicesReInstallPpi ( + PeiPpiDescriptor, + &mUp2PreMemInitDonePpi + ); + ASSERT_EFI_ERROR (Status); + + // + // Reinstall all instances of Pre Mem Init PPIs. + // These PPIs are no longer used so it doesn't matter which board's in= stance is finally installed. + // According to PeiServicesReInstallPpi behavior: + // The first run of this loop would replace all descrioptors with a si= nge in-RAM descriptor; + // Subsequent runs of this loop will only replace the first (already i= n-RAM) descriptor. + // As long as all descriptors are in ram, we are fine. + // + Instance =3D 0; + do { + Status =3D PeiServicesLocatePpi ( + &gBoardPreMemInitPpiGuid, + Instance, + &PeiPpiDescriptor, + &Ppi + ); + if (Status =3D=3D EFI_NOT_FOUND) { + break; + } + ASSERT_EFI_ERROR (Status); + DEBUG ((EFI_D_INFO, "Reinstall Pre Mem Init PPI\n")); + Status =3D PeiServicesReInstallPpi ( + PeiPpiDescriptor, + &mUp2PreMemInitPpi + ); + ASSERT_EFI_ERROR (Status); + Instance++; + } while (TRUE); + return Status; + } + DEBUG ((EFI_D_INFO, "Install Pre Mem Init PPI \n")); + Status =3D PeiServicesInstallPpi (&mUp2PreMemInitPpi); + + return Status; +} + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardIni= t.h b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInit.h new file mode 100644 index 0000000000..a24c2b121f --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInit.h @@ -0,0 +1,29 @@ +/** @file + GPIO setting for CherryView. + This file includes package header files, library classes. + + Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _MYBOARD_BOARDINIT_H_ +#define _MYBOARD_BOARDINIT_H_ + +#include +#include +#include +#include +#include + +VOID Up2GpioTest (VOID); + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardIni= tMiscs.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitM= iscs.c new file mode 100644 index 0000000000..d5092c2490 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.c @@ -0,0 +1,342 @@ +/** @file + This file does Multiplatform initialization. + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "BoardInitMiscs.h" +#include "MmrcData.h" + +UPDATE_FSPM_UPD_FUNC mUp2UpdateFspmUpdPtr =3D Up2UpdateFspmUpd; +DRAM_CREATE_POLICY_DEFAULTS_FUNC mUp2DramCreatePolicyDefaultsPtr =3D Up2= DramCreatePolicyDefaults; + +UINT8 ChSwizzle_UP2[DRAM_POLICY_NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS] = =3D { + {13,10,8,11,12,15,14,9,6,0,3,4,7,1,5,2,28,26,25,27,29,31,30,24,16,23,21,= 22,20,18,19,17}, // Channel 0 =20 + {0,7,4,5,6,2,3,1,8,15,13,11,10,9,14,12,23,17,19,18,20,21,22,16,28,26,29,= 31,24,25,30,27}, // Channel 1 =20 + {13,8,11,14,12,15,9,10,4,7,1,6,2,3,0,5,24,25,28,26,29,30,31,27,17,19,21,= 16,22,18,23,20}, // Channel 2 + {0,5,4,7,3,2,6,1,10,11,8,9,12,14,13,15,18,22,20,19,23,17,21,16,25,31,29,= 27,30,24,28,26} // Channel 3 +}; + + + +EFI_STATUS +EFIAPI +Up2UpdateFspmUpd ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN FSPM_UPD *FspUpdRgn + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_PLATFORM_INFO_HOB *PlatformInfo =3D NULL; + DRAM_POLICY_PPI *DramPolicy; + EFI_STATUS Status; + MRC_PARAMS_SAVE_RESTORE *MrcNvData; + BOOT_VARIABLE_NV_DATA *BootVariableNvData; + MRC_PARAMS_SAVE_RESTORE *MrcParamsHob; + BOOT_VARIABLE_NV_DATA *BootVariableNvDataHob; + + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gDramPolicyPpiGuid, + 0, + NULL, + (VOID **) &DramPolicy + ); + + if (!EFI_ERROR (Status)) { + FspUpdRgn->FspmConfig.Package =3D DramPolicy= ->Package; + FspUpdRgn->FspmConfig.Profile =3D DramPolicy= ->Profile; + FspUpdRgn->FspmConfig.MemoryDown =3D DramPolicy= ->MemoryDown; + FspUpdRgn->FspmConfig.DDR3LPageSize =3D DramPolicy= ->DDR3LPageSize; + FspUpdRgn->FspmConfig.DDR3LASR =3D DramPolicy= ->DDR3LASR; + FspUpdRgn->FspmConfig.MemorySizeLimit =3D DramPolicy= ->SystemMemorySizeLimit; + FspUpdRgn->FspmConfig.DIMM0SPDAddress =3D DramPolicy= ->SpdAddress[0]; + FspUpdRgn->FspmConfig.DIMM1SPDAddress =3D DramPolicy= ->SpdAddress[1]; + FspUpdRgn->FspmConfig.DDR3LPageSize =3D DramPolicy= ->DDR3LPageSize; + FspUpdRgn->FspmConfig.DDR3LASR =3D DramPolicy= ->DDR3LASR; + FspUpdRgn->FspmConfig.HighMemoryMaxValue =3D DramPolicy= ->HighMemMaxVal; + FspUpdRgn->FspmConfig.LowMemoryMaxValue =3D DramPolicy= ->LowMemMaxVal; + FspUpdRgn->FspmConfig.DisableFastBoot =3D DramPolicy= ->DisableFastBoot; + FspUpdRgn->FspmConfig.RmtMode =3D DramPolicy= ->RmtMode; + FspUpdRgn->FspmConfig.RmtCheckRun =3D DramPolicy= ->RmtCheckRun; + FspUpdRgn->FspmConfig.RmtMarginCheckScaleHighThreshold =3D DramPolicy= ->RmtMarginCheckScaleHighThreshold; + FspUpdRgn->FspmConfig.MsgLevelMask =3D DramPolicy= ->MsgLevelMask; + + FspUpdRgn->FspmConfig.ChannelHashMask =3D DramPolicy= ->ChannelHashMask; + FspUpdRgn->FspmConfig.SliceHashMask =3D DramPolicy= ->SliceHashMask; + FspUpdRgn->FspmConfig.ChannelsSlicesEnable =3D DramPolicy= ->ChannelsSlicesEnabled; + FspUpdRgn->FspmConfig.ScramblerSupport =3D DramPolicy= ->ScramblerSupport; + FspUpdRgn->FspmConfig.InterleavedMode =3D DramPolicy= ->InterleavedMode; + FspUpdRgn->FspmConfig.MinRefRate2xEnable =3D DramPolicy= ->MinRefRate2xEnabled; + FspUpdRgn->FspmConfig.DualRankSupportEnable =3D DramPolicy= ->DualRankSupportEnabled; + + CopyMem (&(FspUpdRgn->FspmConfig.Ch0_RankEnable), &DramPolicy->ChDrp, = sizeof (DramPolicy->ChDrp)); + CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), &DramPolicy->ChSw= izzle, sizeof (DramPolicy->ChSwizzle)); + + if (((VOID *)(UINT32)DramPolicy->MrcTrainingDataPtr !=3D 0) && + ((VOID *)(UINT32)DramPolicy->MrcBootDataPtr !=3D 0)) { + DEBUG ((DEBUG_INFO, "UpdateFspmUpd - NvsBufferPtr\n")); + MrcNvData =3D (MRC_PARAMS_SAVE_RESTORE *) AllocateZeroPool = (sizeof (MRC_PARAMS_SAVE_RESTORE)); + BootVariableNvData =3D (BOOT_VARIABLE_NV_DATA *) AllocateZeroPool (s= izeof (BOOT_VARIABLE_NV_DATA)); + + MrcParamsHob =3D (MRC_PARAMS_SAVE_RESTORE*)((UINT32)DramPol= icy->MrcTrainingDataPtr); + BootVariableNvDataHob =3D (BOOT_VARIABLE_NV_DATA*)((UINT32)DramPolic= y->MrcBootDataPtr); + + CopyMem(MrcNvData, MrcParamsHob, sizeof (MRC_PARAMS_SAVE_RESTORE)); + CopyMem(BootVariableNvData, BootVariableNvDataHob, sizeof (BOOT_VARI= ABLE_NV_DATA)); + FspUpdRgn->FspmArchUpd.NvsBufferPtr =3D (VOID *)(UINT32)MrcNv= Data; + FspUpdRgn->FspmConfig.VariableNvsBufferPtr =3D (VOID *)(UINT32)BootV= ariableNvData; + } + + } + // + // Override RankEnable settings for UP2 + // + FspUpdRgn->FspmConfig.Ch0_RankEnable =3D 1; + FspUpdRgn->FspmConfig.Ch1_RankEnable =3D 1; + FspUpdRgn->FspmConfig.Ch2_RankEnable =3D 0; + FspUpdRgn->FspmConfig.Ch3_RankEnable =3D 0; + + DEBUG ((DEBUG_INFO, "UpdateFspmUpd - gEfiPlatformInfoGuid\n")); + Hob.Raw =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (Hob.Raw !=3D NULL); + PlatformInfo =3D GET_GUID_HOB_DATA (Hob.Raw); + + DEBUG ((DEBUG_INFO, "***** Up2 - UpdateFspmUpd,BoardId =3D %d\n", Platfo= rmInfo->BoardId)); + + if (PlatformInfo->BoardId !=3D BOARD_ID_UP2) {//MyBoardPorting + // + // ASSERT false if BoardId isn't UP2 + // + ASSERT (FALSE); + } + + =20 + FspUpdRgn->FspmConfig.Package =3D 1; + FspUpdRgn->FspmConfig.Profile =3D 0xB; // 2400MHz + FspUpdRgn->FspmConfig.MemoryDown =3D 1; + FspUpdRgn->FspmConfig.DDR3LPageSize =3D 0; + FspUpdRgn->FspmConfig.DDR3LASR =3D 0; + FspUpdRgn->FspmConfig.MemorySizeLimit =3D 0; + FspUpdRgn->FspmConfig.DIMM0SPDAddress =3D 0; + FspUpdRgn->FspmConfig.DIMM1SPDAddress =3D 0; + FspUpdRgn->FspmConfig.DDR3LPageSize =3D 0; + FspUpdRgn->FspmConfig.DDR3LASR =3D 0; + + FspUpdRgn->FspmConfig.Ch0_RankEnable =3D 1; //=20 + FspUpdRgn->FspmConfig.Ch0_DeviceWidth =3D 1;=20 + FspUpdRgn->FspmConfig.Ch0_DramDensity =3D 2; + FspUpdRgn->FspmConfig.Ch0_Option =3D 3; + + FspUpdRgn->FspmConfig.Ch1_RankEnable =3D 1;=20 + FspUpdRgn->FspmConfig.Ch1_DeviceWidth =3D 1; // x16 + FspUpdRgn->FspmConfig.Ch1_DramDensity =3D 2; // 8GB + FspUpdRgn->FspmConfig.Ch1_Option =3D 3; + + FspUpdRgn->FspmConfig.Ch2_RankEnable =3D 0; // empty + FspUpdRgn->FspmConfig.Ch2_DeviceWidth =3D 1; + FspUpdRgn->FspmConfig.Ch2_DramDensity =3D 2; + FspUpdRgn->FspmConfig.Ch2_Option =3D 3; + + FspUpdRgn->FspmConfig.Ch3_RankEnable =3D 0; + FspUpdRgn->FspmConfig.Ch3_DeviceWidth =3D 1; + FspUpdRgn->FspmConfig.Ch3_DramDensity =3D 2; + FspUpdRgn->FspmConfig.Ch3_Option =3D 3; + + FspUpdRgn->FspmConfig.ChannelHashMask =3D 0; + FspUpdRgn->FspmConfig.SliceHashMask =3D 0; + FspUpdRgn->FspmConfig.ChannelsSlicesEnable =3D 0; + FspUpdRgn->FspmConfig.ScramblerSupport =3D 1; + FspUpdRgn->FspmConfig.InterleavedMode =3D 0; + FspUpdRgn->FspmConfig.MinRefRate2xEnable =3D 0; + FspUpdRgn->FspmConfig.DualRankSupportEnable =3D 0; + + // + // Swizzling + // + if (ChSwizzle_UP2 !=3D NULL) { + CopyMem (&(FspUpdRgn->FspmConfig.Ch0_Bit_swizzling), ChSwizzle_UP2[0],= DRAM_POLICY_NUMBER_BITS * sizeof(UINT8)); + CopyMem (&(FspUpdRgn->FspmConfig.Ch1_Bit_swizzling), ChSwizzle_UP2[1],= DRAM_POLICY_NUMBER_BITS * sizeof(UINT8)); + CopyMem (&(FspUpdRgn->FspmConfig.Ch2_Bit_swizzling), ChSwizzle_UP2[2],= DRAM_POLICY_NUMBER_BITS * sizeof(UINT8)); + CopyMem (&(FspUpdRgn->FspmConfig.Ch3_Bit_swizzling), ChSwizzle_UP2[3],= DRAM_POLICY_NUMBER_BITS * sizeof(UINT8)); + } + + return EFI_SUCCESS; +} + + +/** + DramCreatePolicyDefaults creates the default setting of Dram Policy. + + @param[out] DramPolicyPpi The pointer to get Dram Policy PPI i= nstance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buf= fer + +**/ +EFI_STATUS +EFIAPI +Up2DramCreatePolicyDefaults ( + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi, + OUT DRAM_POLICY_PPI **DramPolicyPpi, + IN IAFWDramConfig *DramConfigData, + IN UINTN *MrcTrainingDataAddr, + IN UINTN *MrcBootDataAddr, + IN UINT8 BoardId + ) +{ + DRAM_POLICY_PPI *DramPolicy; + SYSTEM_CONFIGURATION SystemConfiguration; + UINTN VariableSize; + EFI_STATUS Status; + DRP_DRAM_POLICY *DrpPtr; + UINT8 (*ChSwizlePtr)[DRAM_POLICY_NUMBER_CH= ANNELS][DRAM_POLICY_NUMBER_BITS]; + PlatfromDramConf *DramConfig; + BOOLEAN ReadSetupVars; + EFI_PEI_HOB_POINTERS Hob; + + DEBUG ((EFI_D_INFO, "*** Up2 DramCreatePolicyDefaults\n")); + DramPolicy =3D (DRAM_POLICY_PPI *) AllocateZeroPool (sizeof (DRAM_POLICY= _PPI)); + if (DramPolicy =3D=3D NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + ReadSetupVars =3D FALSE; + DrpPtr =3D NULL; + ChSwizlePtr =3D NULL; + DramConfig =3D NULL; + + VariableSize =3D sizeof (SYSTEM_CONFIGURATION); + Status =3D VariablePpi->GetVariable ( + VariablePpi, + PLATFORM_SETUP_VARIABLE_NAME, + &gEfiSetupVariableGuid, + NULL, + &VariableSize, + &SystemConfiguration + ); + +#if !(ONLY_USE_SMIP_DRAM_POLICY =3D=3D 1) + Status =3D EFI_UNSUPPORTED; +#endif + + if (!EFI_ERROR (Status)) { + DEBUG ((EFI_D_INFO, "Using setup options data for DRAM policy\n")); + ReadSetupVars =3D TRUE; + DramPolicy->ChannelHashMask =3D SystemConfiguration.ChannelHas= hMask; + DramPolicy->SliceHashMask =3D SystemConfiguration.SliceHashM= ask; + DramPolicy->ChannelsSlicesEnabled =3D SystemConfiguration.ChannelsSl= icesEnabled; + DramPolicy->ScramblerSupport =3D SystemConfiguration.ScramblerS= upport; + DramPolicy->InterleavedMode =3D SystemConfiguration.Interleave= dMode; + DramPolicy->MinRefRate2xEnabled =3D SystemConfiguration.MinRefRate= 2xEnabled; + DramPolicy->DualRankSupportEnabled =3D SystemConfiguration.DualRankSu= pportEnabled; + } + + DramConfig =3D &(DramConfigData->PlatformDram4); + + DEBUG ((EFI_D_INFO, "Using smip platform override: %d\n", DramConfigData= ->Platform_override)); + switch (DramConfigData->Platform_override) { + case 0: + DramConfig =3D &(DramConfigData->PlatformDram0); + break; + case 1: + DramConfig =3D &(DramConfigData->PlatformDram1); + break; + case 2: + DramConfig =3D &(DramConfigData->PlatformDram2); + break; + case 3: + DramConfig =3D &(DramConfigData->PlatformDram3); + break; + case 4: + DramConfig =3D &(DramConfigData->PlatformDram4); + break; + default: + // + // Do nothing if the override value does not exist. 0xFF is the + // default Platform_override value when no override is selected + // + break; + } + + DramPolicy->Package =3D DramConfig->Package; + DramPolicy->Profile =3D DramConfig->Profile; + DramPolicy->MemoryDown =3D DramConfig->MemoryDow= n; + DramPolicy->DDR3LPageSize =3D DramConfig->DDR3LPage= Size; + DramPolicy->DDR3LASR =3D DramConfig->DDR3LASR; + DramPolicy->SystemMemorySizeLimit =3D DramConfig->MemorySiz= eLimit; + DramPolicy->SpdAddress[0] =3D DramConfig->SpdAddres= s0; + DramPolicy->SpdAddress[1] =3D DramConfig->SpdAddres= s1; + DramPolicy->DDR3LPageSize =3D DramConfig->DDR3LPage= Size; + DramPolicy->DDR3LASR =3D DramConfig->DDR3LASR; + DramPolicy->HighMemMaxVal =3D DramConfig->HighMemMa= xVal; + DramPolicy->LowMemMaxVal =3D DramConfig->LowMemMax= Val; + DramPolicy->DisableFastBoot =3D DramConfig->DisableFa= stBoot; + DramPolicy->RmtMode =3D DramConfig->RmtMode; + DramPolicy->RmtCheckRun =3D DramConfig->RmtCheckR= un; + DramPolicy->RmtMarginCheckScaleHighThreshold =3D DramConfig->RmtMargin= CheckScaleHighThreshold; + + DramPolicy->MsgLevelMask =3D DramConfigData->Messa= ge_level_mask; + DrpPtr =3D (DRP_DRAM_POLICY *) (= &(DramConfig->Ch0RankEnabled)); + ChSwizlePtr =3D (UINT8(*)[DRAM_POLICY= _NUMBER_CHANNELS][DRAM_POLICY_NUMBER_BITS]) (&(DramConfig->Ch0_Bit00_swizzl= ing)); + + if (!ReadSetupVars) { + DEBUG ((EFI_D_INFO, "Using smip data for DRAM policy\n")); + DramPolicy->ChannelHashMask =3D DramConfig->ChannelHashMask; + DramPolicy->SliceHashMask =3D DramConfig->SliceHashMask; + DramPolicy->ChannelsSlicesEnabled =3D DramConfig->ChannelsSlicesEnab= led; + DramPolicy->ScramblerSupport =3D DramConfig->ScramblerSupport; + DramPolicy->InterleavedMode =3D DramConfig->InterleavedMode; + DramPolicy->MinRefRate2xEnabled =3D DramConfig->MinRefRate2xEnable= d; + DramPolicy->DualRankSupportEnabled =3D DramConfig->DualRankSupportEna= bled; + } + + if (DrpPtr !=3D NULL) { + CopyMem (DramPolicy->ChDrp, DrpPtr, sizeof (DramPolicy->ChDrp)); + } + + Status =3D VariablePpi->GetVariable ( + VariablePpi, + PLATFORM_SETUP_VARIABLE_NAME, + &gEfiSetupVariableGuid, + NULL, + &VariableSize, + &SystemConfiguration + ); + + if (!EFI_ERROR (Status)) { + if (SystemConfiguration.Max2G =3D=3D 0) { + DramPolicy->SystemMemorySizeLimit =3D 0x800; + } + } + + if (ChSwizlePtr !=3D NULL) CopyMem (DramPolicy->ChSwizzle, ChSwizlePtr, = sizeof (DramPolicy->ChSwizzle)); + + DramPolicy->MrcTrainingDataPtr =3D (EFI_PHYSICAL_ADDRESS) *MrcTrainingDa= taAddr; + DramPolicy->MrcBootDataPtr =3D (EFI_PHYSICAL_ADDRESS) *MrcBootDataAd= dr; + + // + // Get Platform Info HOB + // + Hob.Raw =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (Hob.Raw !=3D NULL); + + + DEBUG ((EFI_D_INFO, "UP2 has single rank memory\n")); + DramPolicy->DualRankSupportEnabled =3D FALSE; + + *DramPolicyPpi =3D DramPolicy; + + return EFI_SUCCESS; +} + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardIni= tMiscs.h b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitM= iscs.h new file mode 100644 index 0000000000..ea847c4be3 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitMiscs.h @@ -0,0 +1,46 @@ +/** @file + Multiplatform initialization header file. + This file includes package header files, library classes. + + Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _MYBOARD_MULTIPLATFORM_LIB_H_ +#define _MYBOARD_MULTIPLATFORM_LIB_H_ + +#include +#include +#include + +extern UPDATE_FSPM_UPD_FUNC mUp2UpdateFspmUpdPtr; +extern DRAM_CREATE_POLICY_DEFAULTS_FUNC mUp2DramCreatePolicyDefaultsPtr; + +EFI_STATUS +EFIAPI +Up2UpdateFspmUpd ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN FSPM_UPD *FspUpdRgn + ); + +EFI_STATUS +EFIAPI +Up2DramCreatePolicyDefaults ( + IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi, + OUT DRAM_POLICY_PPI **DramPolicyPpi, + IN IAFWDramConfig *DramConfigData, + IN UINTN *MrcTrainingDataAddr, + IN UINTN *MrcBootDataAddr, + IN UINT8 BoardId + ); + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardIni= tPreMem.inf b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardIn= itPreMem.inf new file mode 100644 index 0000000000..7a43a20860 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/BoardInitPreMem= .inf @@ -0,0 +1,57 @@ +## @file +# Board detected module for Intel(R) Atom(TM) x5 Processor Series. +# It will detect the board ID. +# +# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D Up2InitPreMem + FILE_GUID =3D EFCE74E2-1B98-4846-9A90-6B8AEB80F567 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + CONSTRUCTOR =3D Up2InitConstructor + +[Sources] + BoardInit.c + PlatformId.c + BoardInitMiscs.c + +[LibraryClasses] + PeiServicesLib + PcdLib + +[Packages] + MdePkg/MdePkg.dec + BroxtonPlatformPkg/PlatformPkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + BroxtonFspPkg/BroxtonFspPkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + BroxtonPlatformPkg/Common/SampleCode/IntelFsp2WrapperPkg/IntelFsp2Wrappe= rPkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/MemoryInit/MemoryInit.dec + +[Pcd] + gPlatformModuleTokenSpaceGuid.PcdBoardId + gPlatformModuleTokenSpaceGuid.PcdFabId + gPlatformModuleTokenSpaceGuid.PcdUpdateFspmUpdFunc + gPlatformModuleTokenSpaceGuid.PcdDramCreatePolicyDefaultsFunc + gMinnowModuleTokenSpaceGuid.PcdDefaultFabId ## CONSUMES + gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetectionRun ## CONSUMES + gMinnowModuleTokenSpaceGuid.PcdMinnowBoardDetected ## CONSUMES + +[Guids] + +[Ppis] + gBoardPreMemInitPpiGuid + gBoardPreMemInitDoneGuid diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/Platform= Id.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.c new file mode 100644 index 0000000000..cec7a7c565 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.c @@ -0,0 +1,57 @@ +/** @file + Implement Platform ID code. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include "PlatformId.h" + +// +// Board ID pin definiton +// +// Bit SoC Pin Value (Leaf Hill) Value (Minnow Board 3) = Value (Benson Glacier) Value (Aurora Glacier) +// 0 GPIO_224 (J45) PU (1) PU (1) = PD (0) PD (0) +// 1 GPIO_213 (M47) PU (1) PU (1) = PD (0) PU (1) +// 2 GPIO_223 (H48) PU (1) PU (1) = PU (1) PU (1) +// 3 GP_CAMERASB10 (R34) PD (0) PU (1) = PU (1) PU (1) +// + +EFI_STATUS +EFIAPI +Up2GetEmbeddedBoardIdFabId( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT8 *BoardId, + OUT UINT8 *FabId + ) +{ + // + // Hardcode to UP2. + // + *BoardId =3D 0x01;=20 + DEBUG ((DEBUG_INFO, "BoardId is: %02X\n", *BoardId)); + =20 + // + // Hardcode to FAB_A. + // + *FabId =3D 0x00; + DEBUG ((EFI_D_INFO, "FabId is: %02X\n", *FabId)); + + + return EFI_SUCCESS; +} + + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/Platform= Id.h b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.h new file mode 100644 index 0000000000..8e98dcdce8 --- /dev/null +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.h @@ -0,0 +1,74 @@ +/** @file + Header file for the Platform ID code. + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __MYBOARD_PLATFORM_ID_H__ +#define __MYBOARD_PLATFORM_ID_H__ + +// +// Strap Fw Cfg ID define +// +#define IO_EXPANDER_I2C_BUS_NO 0x06 +#define IO_EXPANDER_SLAVE_ADDR 0x22 +#define IO_EXPANDER_INPUT_REG_0 0x00 +#define IO_EXPANDER_INPUT_REG_1 0x01 +#define IO_EXPANDER_INPUT_REG_2 0x02 + +EFI_STATUS +EFIAPI +Up2GetFwCfgId ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT8 *FwCfgId + ); + +EFI_STATUS +EFIAPI +Up2GetBoardIdFabId ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT8 *BoardId, + OUT UINT8 *FabId + ); + +EFI_STATUS +EFIAPI +Up2GetEmbeddedBoardIdFabId ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT8 *BoardId, + OUT UINT8 *FabId + ); + + +EFI_STATUS +EFIAPI +Up2GetDockId ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT8 *DockId + ); + +EFI_STATUS +EFIAPI +Up2GetOsSelPss ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT8 *OsSelPss + ); + +EFI_STATUS +EFIAPI +Up2GetBomIdPss ( + IN CONST EFI_PEI_SERVICES **PeiServices, + OUT UINT8 *BomIdPss + ); + +#endif + diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/Vbt/Vbt.bin b/Platform/B= roxtonPlatformPkg/Board/UP2/Vbt/Vbt.bin new file mode 100644 index 0000000000000000000000000000000000000000..0d94dac62a8e410c4f456b52f4d= e37a50a6655e6 GIT binary patch literal 5632 zcmeHKZ)_Ar6o0$h`!~CLy>5$?qn6>1W9idGF1?6>T-Gw5GYKy|rl@wI~WI*cW_`-y5kW*woTd>u>dU)HE~&w$jt^ z0G!FWei0zbaf_rWgAM=3DwIyY0>3XcGEG@5GzfmT& zn*vRZp=3Dq|2iM8~G5|CH z3gDd8PpX0k`1Kr*jS5gdXG#m31HucKco2>iEy{qecY((P7g3#}%wfts;Nd8a#3Bv8 zk1(yPmKG0ye}->q8LHIMcDqb0tBA=3D=3DtfX|V*36ojc{;O@GXGDt1f0Xw=3DMdhSHU}Id z05_+?PFFr`7JM)$@bH3A0n0K@g40D|mCFNfr~M9;cHJdYqAErX})k zO|s-kJf(RKTzKa5V8abU0u5@R9{e*bjCC9=3DMNvJfnJR{;9yKGd0(?NRl_AQ&M8l#B zg*KoRGWi)mf0OljvEzYR6~`?CD0~%!hY9T@$^an;34NC+pAhl|p+6Jl4?;MRt`wDx zA_<7JTT~8+%ieDmICAwEqUXsWWiGCz0UrFRUiT*Ar z4w+=3Dhbc3t}Wzr(k{j&11OkR`er?T>`On#K~{c zv$K0iWq5omrWP;*DhO)KY?9}j>(M+j5V*MQCJ;U-8JY}x3$*s5$uV$oyMdtD$I=3D)>eYK``jg@KIi6nyE zya7pVwsb7Hb7|Z0FyyOsamyFXl5ykg#G#~Phv$pqqY-burc%onXvvH?-eJ*_x+9%g z_^R~LzOm(qP{djRFki%tdx|t_8%`r0-Ygs)4-YR>LvJjcMi4+`c}cUUgP;~^CnLjA zH8*VD2iX_|3?_zfi!o^+$R>h~rZJ0)UKkD0g{q_mSS!O0LLAqlVaW<39$1j4j%vPA z&)r+GMr&V_^o0PK1_Ewk_W9REp#~8hvLhZ(7HegW0ryiRsi7{^5$fC%>)F=3D1JN7>) zuu09PRWE{l%SpVGAHQ?okLM6ShgL6uBXu~eAl}rsLkOa?exAyIiuq&MT8_B-;T+%bMb9RF^@SF~~8S8ihO_DyH zHP=3D%v-r87B6v3TWR8iO3)!p~({sRYJ(49KG17H4m{_^