From nobody Sat Apr 20 00:47:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1534473319802312.26223868189766; Thu, 16 Aug 2018 19:35:19 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5A77F210F41D3; Thu, 16 Aug 2018 19:35:18 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 25BF9210F3D8E for ; Thu, 16 Aug 2018 19:35:15 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2018 19:35:15 -0700 Received: from shwdeopenpsi014.ccr.corp.intel.com ([10.239.9.19]) by orsmga004.jf.intel.com with ESMTP; 16 Aug 2018 19:35:13 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=hao.a.wu@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,249,1531810800"; d="scan'208";a="225329310" From: Hao Wu To: edk2-devel@lists.01.org Date: Fri, 17 Aug 2018 10:35:10 +0800 Message-Id: <20180817023511.6420-2-hao.a.wu@intel.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20180817023511.6420-1-hao.a.wu@intel.com> References: <20180817023511.6420-1-hao.a.wu@intel.com> Subject: [edk2] [PATCH v3 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5715] Stuff RSB before RSM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Hao Wu , Laszlo Ersek , Michael D Kinney , Jiewen Yao , Eric Dong MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RDMRC_1 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1093 Return Stack Buffer (RSB) is used to predict the target of RET instructions. When the RSB underflows, some processors may fall back to using branch predictors. This might impact software using the retpoline mitigation strategy on those processors. This commit will add RSB stuffing logic before returning from SMM (the RSM instruction) to avoid interfering with non-SMM usage of the retpoline technique. After the stuffing, RSB entries will contain a trap like: @SpecTrap: pause lfence jmp @SpecTrap A more detailed explanation of the purpose of commit is under the 'Branch target injection mitigation' section of the below link: https://software.intel.com/security-software-guidance/insights/host-firmwar= e-speculative-execution-side-channel-mitigation Please note that this commit requires further actions (BZ 1091) to remove the duplicated 'StuffRsb.inc' files and merge them into one under a UefiCpuPkg package-level directory (such as UefiCpuPkg/Include/). REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1091 Cc: Jiewen Yao Cc: Eric Dong Cc: Laszlo Ersek Cc: Michael D Kinney Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu Acked-by: Laszlo Ersek Regression-tested-by: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 3 ++ UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 3 ++ UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc | 55 ++++++++++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 3 ++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm | 3 ++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc | 55 ++++++++++++++++++++ 6 files changed, 122 insertions(+) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSm= mCpuDxeSmm/Ia32/SmiEntry.nasm index 509e7a0a66..6bbc339c53 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -18,6 +18,8 @@ ; ;-------------------------------------------------------------------------= ------ =20 +%include "StuffRsb.inc" + %define MSR_IA32_MISC_ENABLE 0x1A0 %define MSR_EFER 0xc0000080 %define MSR_EFER_XD 0x800 @@ -204,6 +206,7 @@ ASM_PFX(SmiHandler): wrmsr =20 .7: + StuffRsb32 rsm =20 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/Ia32/SmmInit.nasm index 5ff3cd2e73..322b1ab556 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm @@ -18,6 +18,8 @@ ; ;-------------------------------------------------------------------------= ------ =20 +%include "StuffRsb.inc" + extern ASM_PFX(SmmInitHandler) extern ASM_PFX(mRebasedFlag) extern ASM_PFX(mSmmRelocationOriginalAddress) @@ -75,6 +77,7 @@ BITS 32 mov esp, strict dword 0 ; source operand will be patched ASM_PFX(gPatchSmmInitStack): call ASM_PFX(SmmInitHandler) + StuffRsb32 rsm =20 BITS 16 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc b/UefiCpuPkg/PiSmm= CpuDxeSmm/Ia32/StuffRsb.inc new file mode 100644 index 0000000000..14267c3fde --- /dev/null +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc @@ -0,0 +1,55 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2018, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +; Abstract: +; +; This file provides macro definitions for stuffing the Return Stack Buf= fer (RSB). +; +;-------------------------------------------------------------------------= ----- + +%define RSB_STUFF_ENTRIES 0x20 + +; +; parameters: +; @param 1: register to use as counter (e.g. IA32:eax, X64:rax) +; @param 2: stack pointer to restore (IA32:esp, X64:rsp) +; @param 3: the size of a stack frame (IA32:4, X64:8) +; +%macro StuffRsb 3 + mov %1, RSB_STUFF_ENTRIES / 2 + %%Unroll1: + call %%Unroll2 + %%SpecTrap1: + pause + lfence + jmp %%SpecTrap1 + %%Unroll2: + call %%StuffLoop + %%SpecTrap2: + pause + lfence + jmp %%SpecTrap2 + %%StuffLoop: + dec %1 + jnz %%Unroll1 + add %2, RSB_STUFF_ENTRIES * %3 ; Restore the stack pointer +%endmacro + +; +; RSB stuffing macros for IA32 and X64 +; +%macro StuffRsb32 0 + StuffRsb eax, esp, 4 +%endmacro + +%macro StuffRsb64 0 + StuffRsb rax, rsp, 8 +%endmacro diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index 97c7b01d0d..315d0f8670 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -18,6 +18,8 @@ ; ;-------------------------------------------------------------------------= ------ =20 +%include "StuffRsb.inc" + ; ; Variables referrenced by C code ; @@ -217,6 +219,7 @@ _SmiHandler: wrmsr =20 .1: + StuffRsb64 rsm =20 ASM_PFX(gcSmiHandlerSize) DW $ - _SmiEntryPoint diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmC= puDxeSmm/X64/SmmInit.nasm index 0b0c3f28e5..24357d5870 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm @@ -18,6 +18,8 @@ ; ;-------------------------------------------------------------------------= ------ =20 +%include "StuffRsb.inc" + extern ASM_PFX(SmmInitHandler) extern ASM_PFX(mRebasedFlag) extern ASM_PFX(mSmmRelocationOriginalAddress) @@ -101,6 +103,7 @@ ASM_PFX(gPatchSmmInitStack): movdqa xmm4, [rsp + 0x40] movdqa xmm5, [rsp + 0x50] =20 + StuffRsb64 rsm =20 BITS 16 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc b/UefiCpuPkg/PiSmmC= puDxeSmm/X64/StuffRsb.inc new file mode 100644 index 0000000000..14267c3fde --- /dev/null +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc @@ -0,0 +1,55 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2018, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BS= D License +; which accompanies this distribution. The full text of the license may b= e found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +; +; Abstract: +; +; This file provides macro definitions for stuffing the Return Stack Buf= fer (RSB). +; +;-------------------------------------------------------------------------= ----- + +%define RSB_STUFF_ENTRIES 0x20 + +; +; parameters: +; @param 1: register to use as counter (e.g. IA32:eax, X64:rax) +; @param 2: stack pointer to restore (IA32:esp, X64:rsp) +; @param 3: the size of a stack frame (IA32:4, X64:8) +; +%macro StuffRsb 3 + mov %1, RSB_STUFF_ENTRIES / 2 + %%Unroll1: + call %%Unroll2 + %%SpecTrap1: + pause + lfence + jmp %%SpecTrap1 + %%Unroll2: + call %%StuffLoop + %%SpecTrap2: + pause + lfence + jmp %%SpecTrap2 + %%StuffLoop: + dec %1 + jnz %%Unroll1 + add %2, RSB_STUFF_ENTRIES * %3 ; Restore the stack pointer +%endmacro + +; +; RSB stuffing macros for IA32 and X64 +; +%macro StuffRsb32 0 + StuffRsb eax, esp, 4 +%endmacro + +%macro StuffRsb64 0 + StuffRsb rax, rsp, 8 +%endmacro --=20 2.12.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel