From nobody Thu Dec 26 00:26:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506497542053580.5547911881301; Wed, 27 Sep 2017 00:32:22 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3DF9821F322DB; Wed, 27 Sep 2017 00:29:07 -0700 (PDT) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 91B9521F322CB for ; Wed, 27 Sep 2017 00:29:06 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Sep 2017 00:32:19 -0700 Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga003.jf.intel.com with ESMTP; 27 Sep 2017 00:32:18 -0700 Received: from fmsmsx126.amr.corp.intel.com (10.18.125.43) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 27 Sep 2017 00:32:18 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX126.amr.corp.intel.com (10.18.125.43) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 27 Sep 2017 00:32:18 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.213]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.159]) with mapi id 14.03.0319.002; Wed, 27 Sep 2017 15:32:16 +0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=mang.guo@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,444,1500966000"; d="dat'59?scan'59,208,59";a="1018912282" From: "Guo, Mang" To: "edk2-devel@lists.01.org" Thread-Topic: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Changed Max Baud Rate Thread-Index: AdM3Yr3xP5SghKeQRQOMQX5UnbL9qA== Date: Wed, 27 Sep 2017 07:32:16 +0000 Message-ID: <22D2C85ED001C54AA20BFE3B0E4751D15256F11C@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: <22D2C85ED001C54AA20BFE3B0E4751D15256F11C@SHSMSX103.ccr.corp.intel.com> x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: [edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Changed Max Baud Rate X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Lu, ShifeiX A" , "Wei, David" Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Change Max Baud Rate to 115200. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang --- .../BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsLpss.h | 9 +++++= ++-- .../PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.c | 3 +-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/Re= gsLpss.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/Regs= Lpss.h index 51e4e95..6f2f91d 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsLpss.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsLpss.h @@ -17,7 +17,7 @@ - Registers / bits of new devices introduced in a SC generation will be = just named as "_PCH_" without inserted. =20 - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -124,8 +124,13 @@ #define B_LPSS_IO_MEM_PCP_N_VAL 0x7FFF0000 ///< N value for th= e M over N divider #define B_LPSS_IO_MEM_PCP_M_VAL 0x0000FFFE ///< M value for th= e M over N divider #define B_LPSS_IO_MEM_PCP_CLK_EN BIT0 ///< Clock Enable -#define V_LPSS_IO_PPR_CLK_M_DIV 1152 ///< Max Baudrate = =3D (100MHz * (1152 / 15625)) / 16 =3D 460800Hz +#define V_LPSS_IO_PPR_CLK_M_DIV 288 ///< Max Baudrate = =3D (100MHz * (288 / 15625)) / 16 =3D 115200Hz + /// 2304 -> 921600 + /// 1152 -> 460800 + /// 576 -> 230400 + /// 288 -> 115200 #define V_LPSS_IO_PPR_CLK_N_DIV 15625 +#define MAX_BAUD_RATE 115200 /// ((100000000 * (= V_LPSS_IO_PPR_CLK_M_DIV / V_LPSS_IO_PPR_CLK_N_DIV)) / 16) =20 #define R_LPSS_IO_MEM_RESETS 0x204 ///< Software Reset #define B_LPSS_IO_MEM_HC_RESET_REL (BIT0|BIT1) ///< LPSS IO Host C= ontroller Reset Release diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmm= PchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.c b/Silicon/BroxtonSoC/Broxt= onSiPkg/SouthCluster/Library/PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerial= IoUartLib.c index ed34140..4a3bdcc 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSeri= alIoUartLib/PeiDxeSmmPchSerialIoUartLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/PeiDxeSmmPchSeri= alIoUartLib/PeiDxeSmmPchSerialIoUartLib.c @@ -3,7 +3,7 @@ All function in this library is available for PEI, DXE, and SMM, But do not support UEFI RUNTIME environment call. =20 - Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -24,7 +24,6 @@ #include #include =20 -#define MAX_BAUD_RATE 460800 // Maximum Baud per SoC spec =20 #define R_PCH_SERIAL_IO_8BIT_UART_RXBUF 0x00 #define R_PCH_SERIAL_IO_8BIT_UART_TXBUF 0x00 --=20 2.10.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel