From nobody Tue Dec 24 17:18:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1511926230649861.2217267430294; Tue, 28 Nov 2017 19:30:30 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5777521A04E2F; Tue, 28 Nov 2017 19:26:05 -0800 (PST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E30AA203564C4 for ; Tue, 28 Nov 2017 19:26:03 -0800 (PST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Nov 2017 19:30:27 -0800 Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga006.fm.intel.com with ESMTP; 28 Nov 2017 19:30:26 -0800 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 28 Nov 2017 19:30:26 -0800 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.319.2; Tue, 28 Nov 2017 19:30:25 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.213]) by shsmsx102.ccr.corp.intel.com ([169.254.2.175]) with mapi id 14.03.0319.002; Wed, 29 Nov 2017 11:30:24 +0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=mang.guo@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,470,1505804400"; d="dat'59?scan'59,208,59";a="181790826" From: "Guo, Mang" To: "edk2-devel@lists.01.org" Thread-Topic: [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Spi driver change Thread-Index: AdNowmPsYhgokNSnR/u9zE/F5GaAJA== Date: Wed, 29 Nov 2017 03:30:23 +0000 Message-ID: <22D2C85ED001C54AA20BFE3B0E4751D15257CF21@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: <22D2C85ED001C54AA20BFE3B0E4751D15257CF21@SHSMSX103.ccr.corp.intel.com> x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: [edk2] [Patch][edk2-platforms/devel-MinnowBoard3-UDK2017] Spi driver change X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Wei, David" Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang --- .../BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSpi.h | 3 ++- .../SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c | 10 ++++++++++ .../BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c | 16 ++++++++++++= ++++ 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/Re= gsSpi.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsS= pi.h index 27cc50b..5c961e6 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSpi.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSpi.h @@ -17,7 +17,7 @@ - Registers / bits of new devices introduced in a SC generation will be = just named as "_SC_" without inserted. =20 - Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -92,6 +92,7 @@ #define B_SPI_HSFS_FLOCKDN BIT15 ///< Flash Configur= ation Lock-Down #define B_SPI_HSFS_FDV BIT14 ///< Flash Descript= or Valid #define B_SPI_HSFS_FDOPSS BIT13 ///< Flash Descript= or Override Pin-Strap Status +#define B_SPI_HSFS_WRSDIS BIT11 ///< Write Status D= isable #define B_SPI_HSFS_SCIP BIT5 ///< SPI Cycle in P= rogress #define B_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) ///< Block/Sector E= rase Size #define V_SPI_HSFS_BERASE_256B 0//0x00 ///< Block/Sector = =3D 256 Bytes diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpi= CommonLib/SpiCommon.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Librar= y/BaseScSpiCommonLib/SpiCommon.c index 97a13fa..722f297 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonL= ib/SpiCommon.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonL= ib/SpiCommon.c @@ -601,6 +601,7 @@ SendSpiCmd ( UINT8 BiosCtlSave; UINT32 SmiEnSave; UINT16 ABase; + UINT32 HsfstsCtl; =20 Status =3D EFI_SUCCESS; SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This); @@ -653,6 +654,15 @@ SendSpiCmd ( goto SendSpiCmdEnd; } =20 + + if (FlashCycleType =3D=3D FlashCycleWriteStatus) { + HsfstsCtl =3D MmioRead32 (ScSpiBar0 + R_SPI_HSFS); + if ((HsfstsCtl & B_SPI_HSFS_WRSDIS) !=3D 0) { + Status =3D EFI_ACCESS_DENIED; + goto SendSpiCmdEnd; + } + } + HardwareSpiAddr =3D Address; if ((FlashCycleType =3D=3D FlashCycleRead) || (FlashCycleType =3D=3D FlashCycleWrite) || diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit= .c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c index 3fb37ea..ebb424b 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c @@ -639,6 +639,8 @@ ScOnEndOfDxe ( UINT16 Data16Or; SI_POLICY_HOB *SiPolicyHob; EFI_PEI_HOB_POINTERS HobPtr; + UINT16 Data16; + UINTN SpiBar0; =20 NumOfDevltrOverride =3D 0; PciLpcRegBase =3D MmPciBase ( @@ -678,6 +680,20 @@ ScOnEndOfDxe ( (VOID *) (UINTN) (PmcBase + R_PMC_PMIR) ); =20 + if (BxtSeries =3D=3D BxtP){ + SpiBar0 =3D MmioRead32 (PciSpiRegBase + R_SPI_BASE) &~(B_SPI_BAR0_MASK= ); + + Data16 =3D (UINT16) (B_SPI_HSFS_FLOCKDN | B_SPI_HSFS_WRSDIS); + MmioWrite16 ((UINTN) (SpiBar0 + R_SPI_HSFS), Data16); + S3BootScriptSaveMemWrite ( + EfiBootScriptWidthUint16, + (UINTN) (SpiBar0 + R_SPI_HSFS), + 1, + &Data16 + ); + + } + =20 Status =3D GetConfigBlock ((VOID *) mScPolicy, &gLockDownConfigGuid, (VO= ID *) &LockDownConfig); ASSERT_EFI_ERROR (Status); if (LockDownConfig->GlobalSmi =3D=3D TRUE) { --=20 2.10.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel