[libvirt] [PATCH 0/4] cpu: modularize the CPU map data file

Daniel P. Berrangé posted 4 patches 5 years, 7 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/libvirt tags/patchew/20180801170232.17672-1-berrange@redhat.com
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libvirt.spec.in                              |    2 +-
mingw-libvirt.spec.in                        |    4 +-
src/Makefile.am                              |    2 +-
src/cpu/cpu_map.c                            |  160 +-
src/cpu/cpu_map.h                            |   22 +-
src/cpu/cpu_map.xml                          | 2415 +-----------------
src/cpu/cpu_map_ppc64_POWER6.xml             |    6 +
src/cpu/cpu_map_ppc64_POWER7.xml             |    7 +
src/cpu/cpu_map_ppc64_POWER8.xml             |    8 +
src/cpu/cpu_map_ppc64_POWER9.xml             |    6 +
src/cpu/cpu_map_ppc64_POWERPC_e5500.xml      |    6 +
src/cpu/cpu_map_ppc64_POWERPC_e6500.xml      |    6 +
src/cpu/cpu_map_ppc64_vendors.xml            |    4 +
src/cpu/cpu_map_x86_486.xml                  |    7 +
src/cpu/cpu_map_x86_Broadwell-IBRS.xml       |   61 +
src/cpu/cpu_map_x86_Broadwell-noTSX-IBRS.xml |   59 +
src/cpu/cpu_map_x86_Broadwell-noTSX.xml      |   58 +
src/cpu/cpu_map_x86_Broadwell.xml            |   60 +
src/cpu/cpu_map_x86_Conroe.xml               |   33 +
src/cpu/cpu_map_x86_EPYC-IBRS.xml            |   73 +
src/cpu/cpu_map_x86_EPYC.xml                 |   72 +
src/cpu/cpu_map_x86_Haswell-IBRS.xml         |   57 +
src/cpu/cpu_map_x86_Haswell-noTSX-IBRS.xml   |   55 +
src/cpu/cpu_map_x86_Haswell-noTSX.xml        |   54 +
src/cpu/cpu_map_x86_Haswell.xml              |   56 +
src/cpu/cpu_map_x86_IvyBridge-IBRS.xml       |   51 +
src/cpu/cpu_map_x86_IvyBridge.xml            |   50 +
src/cpu/cpu_map_x86_Nehalem-IBRS.xml         |   38 +
src/cpu/cpu_map_x86_Nehalem.xml              |   37 +
src/cpu/cpu_map_x86_Opteron_G1.xml           |   31 +
src/cpu/cpu_map_x86_Opteron_G2.xml           |   35 +
src/cpu/cpu_map_x86_Opteron_G3.xml           |   40 +
src/cpu/cpu_map_x86_Opteron_G4.xml           |   50 +
src/cpu/cpu_map_x86_Opteron_G5.xml           |   53 +
src/cpu/cpu_map_x86_Penryn.xml               |   35 +
src/cpu/cpu_map_x86_SandyBridge-IBRS.xml     |   45 +
src/cpu/cpu_map_x86_SandyBridge.xml          |   44 +
src/cpu/cpu_map_x86_Skylake-Client-IBRS.xml  |   70 +
src/cpu/cpu_map_x86_Skylake-Client.xml       |   69 +
src/cpu/cpu_map_x86_Skylake-Server-IBRS.xml  |   77 +
src/cpu/cpu_map_x86_Skylake-Server.xml       |   76 +
src/cpu/cpu_map_x86_Westmere-IBRS.xml        |   39 +
src/cpu/cpu_map_x86_Westmere.xml             |   38 +
src/cpu/cpu_map_x86_athlon.xml               |   28 +
src/cpu/cpu_map_x86_core2duo.xml             |   33 +
src/cpu/cpu_map_x86_coreduo.xml              |   29 +
src/cpu/cpu_map_x86_cpu64-rhel5.xml          |   29 +
src/cpu/cpu_map_x86_cpu64-rhel6.xml          |   31 +
src/cpu/cpu_map_x86_features.xml             |  440 ++++
src/cpu/cpu_map_x86_kvm32.xml                |   26 +
src/cpu/cpu_map_x86_kvm64.xml                |   30 +
src/cpu/cpu_map_x86_n270.xml                 |   30 +
src/cpu/cpu_map_x86_pentium.xml              |   13 +
src/cpu/cpu_map_x86_pentium2.xml             |   22 +
src/cpu/cpu_map_x86_pentium3.xml             |   23 +
src/cpu/cpu_map_x86_pentiumpro.xml           |   21 +
src/cpu/cpu_map_x86_phenom.xml               |   36 +
src/cpu/cpu_map_x86_qemu32.xml               |   22 +
src/cpu/cpu_map_x86_qemu64.xml               |   40 +
src/cpu/cpu_map_x86_vendors.xml              |    4 +
src/cpu/cpu_ppc64.c                          |  112 +-
src/cpu/cpu_x86.c                            |  196 +-
62 files changed, 2703 insertions(+), 2633 deletions(-)
create mode 100644 src/cpu/cpu_map_ppc64_POWER6.xml
create mode 100644 src/cpu/cpu_map_ppc64_POWER7.xml
create mode 100644 src/cpu/cpu_map_ppc64_POWER8.xml
create mode 100644 src/cpu/cpu_map_ppc64_POWER9.xml
create mode 100644 src/cpu/cpu_map_ppc64_POWERPC_e5500.xml
create mode 100644 src/cpu/cpu_map_ppc64_POWERPC_e6500.xml
create mode 100644 src/cpu/cpu_map_ppc64_vendors.xml
create mode 100644 src/cpu/cpu_map_x86_486.xml
create mode 100644 src/cpu/cpu_map_x86_Broadwell-IBRS.xml
create mode 100644 src/cpu/cpu_map_x86_Broadwell-noTSX-IBRS.xml
create mode 100644 src/cpu/cpu_map_x86_Broadwell-noTSX.xml
create mode 100644 src/cpu/cpu_map_x86_Broadwell.xml
create mode 100644 src/cpu/cpu_map_x86_Conroe.xml
create mode 100644 src/cpu/cpu_map_x86_EPYC-IBRS.xml
create mode 100644 src/cpu/cpu_map_x86_EPYC.xml
create mode 100644 src/cpu/cpu_map_x86_Haswell-IBRS.xml
create mode 100644 src/cpu/cpu_map_x86_Haswell-noTSX-IBRS.xml
create mode 100644 src/cpu/cpu_map_x86_Haswell-noTSX.xml
create mode 100644 src/cpu/cpu_map_x86_Haswell.xml
create mode 100644 src/cpu/cpu_map_x86_IvyBridge-IBRS.xml
create mode 100644 src/cpu/cpu_map_x86_IvyBridge.xml
create mode 100644 src/cpu/cpu_map_x86_Nehalem-IBRS.xml
create mode 100644 src/cpu/cpu_map_x86_Nehalem.xml
create mode 100644 src/cpu/cpu_map_x86_Opteron_G1.xml
create mode 100644 src/cpu/cpu_map_x86_Opteron_G2.xml
create mode 100644 src/cpu/cpu_map_x86_Opteron_G3.xml
create mode 100644 src/cpu/cpu_map_x86_Opteron_G4.xml
create mode 100644 src/cpu/cpu_map_x86_Opteron_G5.xml
create mode 100644 src/cpu/cpu_map_x86_Penryn.xml
create mode 100644 src/cpu/cpu_map_x86_SandyBridge-IBRS.xml
create mode 100644 src/cpu/cpu_map_x86_SandyBridge.xml
create mode 100644 src/cpu/cpu_map_x86_Skylake-Client-IBRS.xml
create mode 100644 src/cpu/cpu_map_x86_Skylake-Client.xml
create mode 100644 src/cpu/cpu_map_x86_Skylake-Server-IBRS.xml
create mode 100644 src/cpu/cpu_map_x86_Skylake-Server.xml
create mode 100644 src/cpu/cpu_map_x86_Westmere-IBRS.xml
create mode 100644 src/cpu/cpu_map_x86_Westmere.xml
create mode 100644 src/cpu/cpu_map_x86_athlon.xml
create mode 100644 src/cpu/cpu_map_x86_core2duo.xml
create mode 100644 src/cpu/cpu_map_x86_coreduo.xml
create mode 100644 src/cpu/cpu_map_x86_cpu64-rhel5.xml
create mode 100644 src/cpu/cpu_map_x86_cpu64-rhel6.xml
create mode 100644 src/cpu/cpu_map_x86_features.xml
create mode 100644 src/cpu/cpu_map_x86_kvm32.xml
create mode 100644 src/cpu/cpu_map_x86_kvm64.xml
create mode 100644 src/cpu/cpu_map_x86_n270.xml
create mode 100644 src/cpu/cpu_map_x86_pentium.xml
create mode 100644 src/cpu/cpu_map_x86_pentium2.xml
create mode 100644 src/cpu/cpu_map_x86_pentium3.xml
create mode 100644 src/cpu/cpu_map_x86_pentiumpro.xml
create mode 100644 src/cpu/cpu_map_x86_phenom.xml
create mode 100644 src/cpu/cpu_map_x86_qemu32.xml
create mode 100644 src/cpu/cpu_map_x86_qemu64.xml
create mode 100644 src/cpu/cpu_map_x86_vendors.xml
[libvirt] [PATCH 0/4] cpu: modularize the CPU map data file
Posted by Daniel P. Berrangé 5 years, 7 months ago
Currently we have a cpu_map.xml file that contains all the features and
CPU models for all architectures in one place. I frequently find myself
wondering about the differences between CPU models, but it is hard to
compare them as the list of features is huge.

With this patch series we end up with a large set of small files, one
per named CPU model, along with one for the feature and vendor
definitions

   cpu_map_ppc64_POWER6.xml
   cpu_map_ppc64_POWER7.xml
   cpu_map_ppc64_POWER8.xml
   cpu_map_ppc64_POWER9.xml
   cpu_map_ppc64_POWERPC_e5500.xml
   cpu_map_ppc64_POWERPC_e6500.xml
   cpu_map_ppc64_vendors.xml
   cpu_map_x86_486.xml
   cpu_map_x86_athlon.xml
   cpu_map_x86_Broadwell-IBRS.xml
   cpu_map_x86_Broadwell-noTSX-IBRS.xml
   cpu_map_x86_Broadwell-noTSX.xml
   cpu_map_x86_Broadwell.xml
   cpu_map_x86_Conroe.xml
   cpu_map_x86_core2duo.xml
   cpu_map_x86_coreduo.xml
   cpu_map_x86_cpu64-rhel5.xml
   cpu_map_x86_cpu64-rhel6.xml
   cpu_map_x86_EPYC-IBRS.xml
   cpu_map_x86_EPYC.xml
   cpu_map_x86_features.xml
   cpu_map_x86_Haswell-IBRS.xml
   cpu_map_x86_Haswell-noTSX-IBRS.xml
   cpu_map_x86_Haswell-noTSX.xml
   cpu_map_x86_Haswell.xml
   cpu_map_x86_IvyBridge-IBRS.xml
   cpu_map_x86_IvyBridge.xml
   cpu_map_x86_kvm32.xml
   cpu_map_x86_kvm64.xml
   cpu_map_x86_n270.xml
   cpu_map_x86_Nehalem-IBRS.xml
   cpu_map_x86_Nehalem.xml
   cpu_map_x86_Opteron_G1.xml
   cpu_map_x86_Opteron_G2.xml
   cpu_map_x86_Opteron_G3.xml
   cpu_map_x86_Opteron_G4.xml
   cpu_map_x86_Opteron_G5.xml
   cpu_map_x86_Penryn.xml
   cpu_map_x86_pentium2.xml
   cpu_map_x86_pentium3.xml
   cpu_map_x86_pentiumpro.xml
   cpu_map_x86_pentium.xml
   cpu_map_x86_phenom.xml
   cpu_map_x86_qemu32.xml
   cpu_map_x86_qemu64.xml
   cpu_map_x86_SandyBridge-IBRS.xml
   cpu_map_x86_SandyBridge.xml
   cpu_map_x86_Skylake-Client-IBRS.xml
   cpu_map_x86_Skylake-Client.xml
   cpu_map_x86_Skylake-Server-IBRS.xml
   cpu_map_x86_Skylake-Server.xml
   cpu_map_x86_vendors.xml
   cpu_map_x86_Westmere-IBRS.xml
   cpu_map_x86_Westmere.xml

The main cpu_map.xml file is now just a list of <include filename="XXX"/>
statements to pull in the individual files

Now we can easily see the differences in each model:

    $ diff cpu_map_x86_Broadwell.xml cpu_map_x86_Skylake-Client.xml
    2,3c2,3
    <   <model name='Broadwell'>
    <     <signature family='6' model='61'/>
    ---
    >   <model name='Skylake-Client'>
    >     <signature family='6' model='94'/>
    5a6
    >     <feature name='abm'/>
    8a10
    >     <feature name='arat'/>
    18a21
    >     <feature name='f16c'/>
    30a34
    >     <feature name='mpx'/>
    42a47
    >     <feature name='rdrand'/>
    56a62
    >     <feature name='vme'/>
    57a64
    >     <feature name='xgetbv1'/>
    58a66,67
    >     <feature name='xsavec'/>
    >     <feature name='xsaveopt'/>

Daniel P. Berrangé (4):
  cpu: allow include files for CPU definition
  cpu: push more parsing logic into common code
  cpu: split PPC64 map data into separate files
  cpu: split x86 map data into separate files

 libvirt.spec.in                              |    2 +-
 mingw-libvirt.spec.in                        |    4 +-
 src/Makefile.am                              |    2 +-
 src/cpu/cpu_map.c                            |  160 +-
 src/cpu/cpu_map.h                            |   22 +-
 src/cpu/cpu_map.xml                          | 2415 +-----------------
 src/cpu/cpu_map_ppc64_POWER6.xml             |    6 +
 src/cpu/cpu_map_ppc64_POWER7.xml             |    7 +
 src/cpu/cpu_map_ppc64_POWER8.xml             |    8 +
 src/cpu/cpu_map_ppc64_POWER9.xml             |    6 +
 src/cpu/cpu_map_ppc64_POWERPC_e5500.xml      |    6 +
 src/cpu/cpu_map_ppc64_POWERPC_e6500.xml      |    6 +
 src/cpu/cpu_map_ppc64_vendors.xml            |    4 +
 src/cpu/cpu_map_x86_486.xml                  |    7 +
 src/cpu/cpu_map_x86_Broadwell-IBRS.xml       |   61 +
 src/cpu/cpu_map_x86_Broadwell-noTSX-IBRS.xml |   59 +
 src/cpu/cpu_map_x86_Broadwell-noTSX.xml      |   58 +
 src/cpu/cpu_map_x86_Broadwell.xml            |   60 +
 src/cpu/cpu_map_x86_Conroe.xml               |   33 +
 src/cpu/cpu_map_x86_EPYC-IBRS.xml            |   73 +
 src/cpu/cpu_map_x86_EPYC.xml                 |   72 +
 src/cpu/cpu_map_x86_Haswell-IBRS.xml         |   57 +
 src/cpu/cpu_map_x86_Haswell-noTSX-IBRS.xml   |   55 +
 src/cpu/cpu_map_x86_Haswell-noTSX.xml        |   54 +
 src/cpu/cpu_map_x86_Haswell.xml              |   56 +
 src/cpu/cpu_map_x86_IvyBridge-IBRS.xml       |   51 +
 src/cpu/cpu_map_x86_IvyBridge.xml            |   50 +
 src/cpu/cpu_map_x86_Nehalem-IBRS.xml         |   38 +
 src/cpu/cpu_map_x86_Nehalem.xml              |   37 +
 src/cpu/cpu_map_x86_Opteron_G1.xml           |   31 +
 src/cpu/cpu_map_x86_Opteron_G2.xml           |   35 +
 src/cpu/cpu_map_x86_Opteron_G3.xml           |   40 +
 src/cpu/cpu_map_x86_Opteron_G4.xml           |   50 +
 src/cpu/cpu_map_x86_Opteron_G5.xml           |   53 +
 src/cpu/cpu_map_x86_Penryn.xml               |   35 +
 src/cpu/cpu_map_x86_SandyBridge-IBRS.xml     |   45 +
 src/cpu/cpu_map_x86_SandyBridge.xml          |   44 +
 src/cpu/cpu_map_x86_Skylake-Client-IBRS.xml  |   70 +
 src/cpu/cpu_map_x86_Skylake-Client.xml       |   69 +
 src/cpu/cpu_map_x86_Skylake-Server-IBRS.xml  |   77 +
 src/cpu/cpu_map_x86_Skylake-Server.xml       |   76 +
 src/cpu/cpu_map_x86_Westmere-IBRS.xml        |   39 +
 src/cpu/cpu_map_x86_Westmere.xml             |   38 +
 src/cpu/cpu_map_x86_athlon.xml               |   28 +
 src/cpu/cpu_map_x86_core2duo.xml             |   33 +
 src/cpu/cpu_map_x86_coreduo.xml              |   29 +
 src/cpu/cpu_map_x86_cpu64-rhel5.xml          |   29 +
 src/cpu/cpu_map_x86_cpu64-rhel6.xml          |   31 +
 src/cpu/cpu_map_x86_features.xml             |  440 ++++
 src/cpu/cpu_map_x86_kvm32.xml                |   26 +
 src/cpu/cpu_map_x86_kvm64.xml                |   30 +
 src/cpu/cpu_map_x86_n270.xml                 |   30 +
 src/cpu/cpu_map_x86_pentium.xml              |   13 +
 src/cpu/cpu_map_x86_pentium2.xml             |   22 +
 src/cpu/cpu_map_x86_pentium3.xml             |   23 +
 src/cpu/cpu_map_x86_pentiumpro.xml           |   21 +
 src/cpu/cpu_map_x86_phenom.xml               |   36 +
 src/cpu/cpu_map_x86_qemu32.xml               |   22 +
 src/cpu/cpu_map_x86_qemu64.xml               |   40 +
 src/cpu/cpu_map_x86_vendors.xml              |    4 +
 src/cpu/cpu_ppc64.c                          |  112 +-
 src/cpu/cpu_x86.c                            |  196 +-
 62 files changed, 2703 insertions(+), 2633 deletions(-)
 create mode 100644 src/cpu/cpu_map_ppc64_POWER6.xml
 create mode 100644 src/cpu/cpu_map_ppc64_POWER7.xml
 create mode 100644 src/cpu/cpu_map_ppc64_POWER8.xml
 create mode 100644 src/cpu/cpu_map_ppc64_POWER9.xml
 create mode 100644 src/cpu/cpu_map_ppc64_POWERPC_e5500.xml
 create mode 100644 src/cpu/cpu_map_ppc64_POWERPC_e6500.xml
 create mode 100644 src/cpu/cpu_map_ppc64_vendors.xml
 create mode 100644 src/cpu/cpu_map_x86_486.xml
 create mode 100644 src/cpu/cpu_map_x86_Broadwell-IBRS.xml
 create mode 100644 src/cpu/cpu_map_x86_Broadwell-noTSX-IBRS.xml
 create mode 100644 src/cpu/cpu_map_x86_Broadwell-noTSX.xml
 create mode 100644 src/cpu/cpu_map_x86_Broadwell.xml
 create mode 100644 src/cpu/cpu_map_x86_Conroe.xml
 create mode 100644 src/cpu/cpu_map_x86_EPYC-IBRS.xml
 create mode 100644 src/cpu/cpu_map_x86_EPYC.xml
 create mode 100644 src/cpu/cpu_map_x86_Haswell-IBRS.xml
 create mode 100644 src/cpu/cpu_map_x86_Haswell-noTSX-IBRS.xml
 create mode 100644 src/cpu/cpu_map_x86_Haswell-noTSX.xml
 create mode 100644 src/cpu/cpu_map_x86_Haswell.xml
 create mode 100644 src/cpu/cpu_map_x86_IvyBridge-IBRS.xml
 create mode 100644 src/cpu/cpu_map_x86_IvyBridge.xml
 create mode 100644 src/cpu/cpu_map_x86_Nehalem-IBRS.xml
 create mode 100644 src/cpu/cpu_map_x86_Nehalem.xml
 create mode 100644 src/cpu/cpu_map_x86_Opteron_G1.xml
 create mode 100644 src/cpu/cpu_map_x86_Opteron_G2.xml
 create mode 100644 src/cpu/cpu_map_x86_Opteron_G3.xml
 create mode 100644 src/cpu/cpu_map_x86_Opteron_G4.xml
 create mode 100644 src/cpu/cpu_map_x86_Opteron_G5.xml
 create mode 100644 src/cpu/cpu_map_x86_Penryn.xml
 create mode 100644 src/cpu/cpu_map_x86_SandyBridge-IBRS.xml
 create mode 100644 src/cpu/cpu_map_x86_SandyBridge.xml
 create mode 100644 src/cpu/cpu_map_x86_Skylake-Client-IBRS.xml
 create mode 100644 src/cpu/cpu_map_x86_Skylake-Client.xml
 create mode 100644 src/cpu/cpu_map_x86_Skylake-Server-IBRS.xml
 create mode 100644 src/cpu/cpu_map_x86_Skylake-Server.xml
 create mode 100644 src/cpu/cpu_map_x86_Westmere-IBRS.xml
 create mode 100644 src/cpu/cpu_map_x86_Westmere.xml
 create mode 100644 src/cpu/cpu_map_x86_athlon.xml
 create mode 100644 src/cpu/cpu_map_x86_core2duo.xml
 create mode 100644 src/cpu/cpu_map_x86_coreduo.xml
 create mode 100644 src/cpu/cpu_map_x86_cpu64-rhel5.xml
 create mode 100644 src/cpu/cpu_map_x86_cpu64-rhel6.xml
 create mode 100644 src/cpu/cpu_map_x86_features.xml
 create mode 100644 src/cpu/cpu_map_x86_kvm32.xml
 create mode 100644 src/cpu/cpu_map_x86_kvm64.xml
 create mode 100644 src/cpu/cpu_map_x86_n270.xml
 create mode 100644 src/cpu/cpu_map_x86_pentium.xml
 create mode 100644 src/cpu/cpu_map_x86_pentium2.xml
 create mode 100644 src/cpu/cpu_map_x86_pentium3.xml
 create mode 100644 src/cpu/cpu_map_x86_pentiumpro.xml
 create mode 100644 src/cpu/cpu_map_x86_phenom.xml
 create mode 100644 src/cpu/cpu_map_x86_qemu32.xml
 create mode 100644 src/cpu/cpu_map_x86_qemu64.xml
 create mode 100644 src/cpu/cpu_map_x86_vendors.xml

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Re: [libvirt] [PATCH 0/4] cpu: modularize the CPU map data file
Posted by Jiri Denemark 5 years, 7 months ago
On Wed, Aug 01, 2018 at 18:02:28 +0100, Daniel P. Berrangé wrote:
> Currently we have a cpu_map.xml file that contains all the features and
> CPU models for all architectures in one place. I frequently find myself
> wondering about the differences between CPU models, but it is hard to
> compare them as the list of features is huge.
> 
> With this patch series we end up with a large set of small files, one
> per named CPU model, along with one for the feature and vendor
> definitions
> 
>    cpu_map_ppc64_POWER6.xml
>    cpu_map_ppc64_POWER7.xml
>    cpu_map_ppc64_POWER8.xml
>    cpu_map_ppc64_POWER9.xml
>    cpu_map_ppc64_POWERPC_e5500.xml
>    cpu_map_ppc64_POWERPC_e6500.xml
>    cpu_map_ppc64_vendors.xml
>    cpu_map_x86_486.xml
>    cpu_map_x86_athlon.xml

Could we make a cpu_map subdirectory and create the CPU definitions
there instead? For example

    src/cpu_map/ppc64_POWER6.xml
    src/cpu_map/x86_Broadwell-IBRS.xml

I think it would make navigation through both the sources and the CPU
models a lot easier.

Jirka

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Re: [libvirt] [PATCH 0/4] cpu: modularize the CPU map data file
Posted by John Ferlan 5 years, 7 months ago

On 08/14/2018 05:00 AM, Jiri Denemark wrote:
> On Wed, Aug 01, 2018 at 18:02:28 +0100, Daniel P. Berrangé wrote:
>> Currently we have a cpu_map.xml file that contains all the features and
>> CPU models for all architectures in one place. I frequently find myself
>> wondering about the differences between CPU models, but it is hard to
>> compare them as the list of features is huge.
>>
>> With this patch series we end up with a large set of small files, one
>> per named CPU model, along with one for the feature and vendor
>> definitions
>>
>>    cpu_map_ppc64_POWER6.xml
>>    cpu_map_ppc64_POWER7.xml
>>    cpu_map_ppc64_POWER8.xml
>>    cpu_map_ppc64_POWER9.xml
>>    cpu_map_ppc64_POWERPC_e5500.xml
>>    cpu_map_ppc64_POWERPC_e6500.xml
>>    cpu_map_ppc64_vendors.xml
>>    cpu_map_x86_486.xml
>>    cpu_map_x86_athlon.xml
> 
> Could we make a cpu_map subdirectory and create the CPU definitions
> there instead? For example
> 
>     src/cpu_map/ppc64_POWER6.xml
>     src/cpu_map/x86_Broadwell-IBRS.xml

Hmm... The cpu_map or even some sort of 'arch' based subdirectory naming
scheme could be useful... If it was src/cpu/cpu_map/ppc64/ and
src/cpu/cpu_map/x86/, then for each .xml file in the @arch subdirectory
type logic is possible, but that could possibly "miss" something that
was 'previously available' from the parent cpu_map.xml file too since
the include could have a directory or arch attribute rather than
filename attribute. Is deleting a CPU a problem? Surely it'd make adding
a new CPU easier since it would simply be adding a new file and no need
to also add the include filename= to the main map.

John

> 
> I think it would make navigation through both the sources and the CPU
> models a lot easier.
> 
> Jirka
> 
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> 

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Re: [libvirt] [PATCH 0/4] cpu: modularize the CPU map data file
Posted by Jiri Denemark 5 years, 7 months ago
On Tue, Aug 14, 2018 at 08:21:40 -0400, John Ferlan wrote:
> 
> 
> On 08/14/2018 05:00 AM, Jiri Denemark wrote:
> > On Wed, Aug 01, 2018 at 18:02:28 +0100, Daniel P. Berrangé wrote:
> >> Currently we have a cpu_map.xml file that contains all the features and
> >> CPU models for all architectures in one place. I frequently find myself
> >> wondering about the differences between CPU models, but it is hard to
> >> compare them as the list of features is huge.
> >>
> >> With this patch series we end up with a large set of small files, one
> >> per named CPU model, along with one for the feature and vendor
> >> definitions
> >>
> >>    cpu_map_ppc64_POWER6.xml
> >>    cpu_map_ppc64_POWER7.xml
> >>    cpu_map_ppc64_POWER8.xml
> >>    cpu_map_ppc64_POWER9.xml
> >>    cpu_map_ppc64_POWERPC_e5500.xml
> >>    cpu_map_ppc64_POWERPC_e6500.xml
> >>    cpu_map_ppc64_vendors.xml
> >>    cpu_map_x86_486.xml
> >>    cpu_map_x86_athlon.xml
> > 
> > Could we make a cpu_map subdirectory and create the CPU definitions
> > there instead? For example
> > 
> >     src/cpu_map/ppc64_POWER6.xml
> >     src/cpu_map/x86_Broadwell-IBRS.xml
> 
> Hmm... The cpu_map or even some sort of 'arch' based subdirectory naming
> scheme could be useful... If it was src/cpu/cpu_map/ppc64/ and
> src/cpu/cpu_map/x86/, then for each .xml file in the @arch subdirectory
> type logic is possible, but that could possibly "miss" something that
> was 'previously available' from the parent cpu_map.xml file too since
> the include could have a directory or arch attribute rather than
> filename attribute. Is deleting a CPU a problem? Surely it'd make adding
> a new CPU easier since it would simply be adding a new file and no need
> to also add the include filename= to the main map.

I think we can still keep the <include filename="..."/> elements even
after moving the files into separate directory(ies). Adding a new file
is not that frequent to be worth optimizing by loading all files
automatically. And explicit includes makes possible issues with missing
files, wrong permissions, etc. easier to spot.

Jirka

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