[v1] Emulate guest vector operations with host vector operations

[Qemu-devel] [PATCH v2.1 10/21] target/arm: use vector opcode to handle vadd.<size> instruction

Posted by Kirill Batuzov 8 years, 5 months ago

Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
---
 target/arm/translate.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index d7578e2..90e14df 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5628,6 +5628,37 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             return 1;
         }
 
+        /* Use vector ops to handle what we can */
+        switch (op) {
+        case NEON_3R_VADD_VSUB:
+            if (!u) {
+                void (* const gen_add_v128[])(TCGv_v128, TCGv_v128,
+                                             TCGv_v128) = {
+                    tcg_gen_add_i8x16,
+                    tcg_gen_add_i16x8,
+                    tcg_gen_add_i32x4,
+                    tcg_gen_add_i64x2
+                };
+                void (* const gen_add_v64[])(TCGv_v64, TCGv_v64,
+                                             TCGv_v64) = {
+                    tcg_gen_add_i8x8,
+                    tcg_gen_add_i16x4,
+                    tcg_gen_add_i32x2,
+                    tcg_gen_add_i64x1
+                };
+                if (q) {
+                    gen_add_v128[size](cpu_Q[rd >> 1], cpu_Q[rn >> 1],
+                                       cpu_Q[rm >> 1]);
+                } else {
+                    gen_add_v64[size](cpu_D[rd], cpu_D[rn], cpu_D[rm]);
+                }
+                return 0;
+            }
+            break;
+        default:
+            break;
+        }
+
         for (pass = 0; pass < (q ? 4 : 2); pass++) {
 
         if (pairwise) {
-- 
2.1.4

Re: [Qemu-devel] [PATCH v2.1 10/21] target/arm: use vector opcode to handle vadd.<size> instruction

Posted by Philippe Mathieu-Daudé 8 years, 4 months ago


On 02/02/2017 11:34 AM, Kirill Batuzov wrote:
> Signed-off-by: Kirill Batuzov <batuzovk@ispras.ru>
> ---
>  target/arm/translate.c | 31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index d7578e2..90e14df 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -5628,6 +5628,37 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
>              return 1;
>          }
>
> +        /* Use vector ops to handle what we can */
> +        switch (op) {
> +        case NEON_3R_VADD_VSUB:
> +            if (!u) {
> +                void (* const gen_add_v128[])(TCGv_v128, TCGv_v128,
> +                                             TCGv_v128) = {
> +                    tcg_gen_add_i8x16,
> +                    tcg_gen_add_i16x8,
> +                    tcg_gen_add_i32x4,
> +                    tcg_gen_add_i64x2
> +                };

I'd rather prefer to have gen_add_v128 'static const'.

> +                void (* const gen_add_v64[])(TCGv_v64, TCGv_v64,
> +                                             TCGv_v64) = {
> +                    tcg_gen_add_i8x8,
> +                    tcg_gen_add_i16x4,
> +                    tcg_gen_add_i32x2,
> +                    tcg_gen_add_i64x1
> +                };

same with gen_add_v64.

> +                if (q) {
> +                    gen_add_v128[size](cpu_Q[rd >> 1], cpu_Q[rn >> 1],
> +                                       cpu_Q[rm >> 1]);
> +                } else {
> +                    gen_add_v64[size](cpu_D[rd], cpu_D[rn], cpu_D[rm]);
> +                }
> +                return 0;
> +            }
> +            break;
> +        default:
> +            break;
> +        }
> +
>          for (pass = 0; pass < (q ? 4 : 2); pass++) {
>
>          if (pairwise) {
>