From nobody Thu Jul 3 16:08:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486047360513430.93552960496936; Thu, 2 Feb 2017 06:56:00 -0800 (PST) Received: from localhost ([::1]:57077 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZInl-0007M1-Me for importer@patchew.org; Thu, 02 Feb 2017 09:55:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZIU7-0005RI-PN for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cZIU0-0005Ry-HR for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:39 -0500 Received: from bran.ispras.ru ([83.149.199.196]:39800 helo=smtp.ispras.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cZIU0-0005OW-7l for qemu-devel@nongnu.org; Thu, 02 Feb 2017 09:35:32 -0500 Received: from bulbul.intra.ispras.ru (spartak.intra.ispras.ru [10.10.3.51]) by smtp.ispras.ru (Postfix) with ESMTP id A330F6178E; Thu, 2 Feb 2017 17:35:31 +0300 (MSK) From: Kirill Batuzov To: qemu-devel@nongnu.org Date: Thu, 2 Feb 2017 17:34:58 +0300 Message-Id: <1486046099-17726-21-git-send-email-batuzovk@ispras.ru> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1486046099-17726-1-git-send-email-batuzovk@ispras.ru> References: <1486046099-17726-1-git-send-email-batuzovk@ispras.ru> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 83.149.199.196 Subject: [Qemu-devel] [PATCH v2.1 20/21] target/arm: load two consecutive 64-bits vector regs as a 128-bit vector reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , Kirill Batuzov , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ARM instruction set does not have loads to 128-bit vector register (q-regs). Instead it can read several consecutive 64-bit vector register (d-regs) which is used by GCC to load 128-bit registers from memory. For vector operations to work we need to detect such loads and transform th= em into 128-bit loads to 128-bit temporaries. Signed-off-by: Kirill Batuzov --- target/arm/translate.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 90e14df..5bd0b1c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4710,6 +4710,21 @@ static int disas_neon_ls_insn(DisasContext *s, uint3= 2_t insn) tcg_gen_addi_i32(addr, addr, 1 << size); } if (size =3D=3D 3) { +#ifdef TCG_TARGET_HAS_REG128 + if (rd % 2 =3D=3D 0 && nregs =3D=3D 2) { + TCGv aa32addr =3D gen_aa32_addr(s, addr, MO_TE | MO_12= 8); + /* 128-bit load */ + if (load) { + tcg_gen_qemu_ld_v128(cpu_Q[rd / 2], aa32addr, + get_mem_index(s), MO_TE | MO_= 128); + } else { + tcg_gen_qemu_st_v128(cpu_Q[rd / 2], aa32addr, + get_mem_index(s), MO_TE | MO_= 128); + } + tcg_temp_free(aa32addr); + break; + } +#endif tmp64 =3D tcg_temp_new_i64(); if (load) { gen_aa32_ld64(s, tmp64, addr, get_mem_index(s)); --=20 2.1.4