From nobody Tue Jul 1 05:29:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1486456709331864.5574996031144; Tue, 7 Feb 2017 00:38:29 -0800 (PST) Received: from localhost ([::1]:52642 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cb1IB-0000aM-Uf for importer@patchew.org; Tue, 07 Feb 2017 03:38:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36697) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cb198-0001dc-PR for qemu-devel@nongnu.org; Tue, 07 Feb 2017 03:29:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cb197-00044L-Gm for qemu-devel@nongnu.org; Tue, 07 Feb 2017 03:29:06 -0500 Received: from mx1.redhat.com ([209.132.183.28]:42092) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cb197-00043g-7Q for qemu-devel@nongnu.org; Tue, 07 Feb 2017 03:29:05 -0500 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 59D8AC04BD5B; Tue, 7 Feb 2017 08:29:05 +0000 (UTC) Received: from pxdev.xzpeter.org.com (ovpn-8-29.pek2.redhat.com [10.72.8.29]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v178SQeX025608; Tue, 7 Feb 2017 03:29:00 -0500 From: Peter Xu To: qemu-devel@nongnu.org Date: Tue, 7 Feb 2017 16:28:08 +0800 Message-Id: <1486456099-7345-7-git-send-email-peterx@redhat.com> In-Reply-To: <1486456099-7345-1-git-send-email-peterx@redhat.com> References: <1486456099-7345-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Tue, 07 Feb 2017 08:29:05 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v7 06/17] intel_iommu: renaming gpa to iova where proper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tianyu.lan@intel.com, kevin.tian@intel.com, mst@redhat.com, jan.kiszka@siemens.com, jasowang@redhat.com, peterx@redhat.com, alex.williamson@redhat.com, bd.aviv@gmail.com, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are lots of places in current intel_iommu.c codes that named "iova" as "gpa". It is really confusing to use a name "gpa" in these places (which is very easily to be understood as "Guest Physical Address", while it's not). To make the codes (much) easier to be read, I decided to do this once and for all. No functional change is made. Only literal ones. Reviewed-by: Jason Wang Signed-off-by: Peter Xu Reviewed-by: David Gibson --- hw/i386/intel_iommu.c | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 86d19bb..0c94b79 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -259,7 +259,7 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16= _t source_id, uint64_t *key =3D g_malloc(sizeof(*key)); uint64_t gfn =3D vtd_get_iotlb_gfn(addr, level); =20 - VTD_DPRINTF(CACHE, "update iotlb sid 0x%"PRIx16 " gpa 0x%"PRIx64 + VTD_DPRINTF(CACHE, "update iotlb sid 0x%"PRIx16 " iova 0x%"PRIx64 " slpte 0x%"PRIx64 " did 0x%"PRIx16, source_id, addr, slpt= e, domain_id); if (g_hash_table_size(s->iotlb) >=3D VTD_IOTLB_MAX_SIZE) { @@ -575,12 +575,12 @@ static uint64_t vtd_get_slpte(dma_addr_t base_addr, u= int32_t index) return slpte; } =20 -/* Given a gpa and the level of paging structure, return the offset of cur= rent - * level. +/* Given an iova and the level of paging structure, return the offset + * of current level. */ -static inline uint32_t vtd_gpa_level_offset(uint64_t gpa, uint32_t level) +static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level) { - return (gpa >> vtd_slpt_level_shift(level)) & + return (iova >> vtd_slpt_level_shift(level)) & ((1ULL << VTD_SL_LEVEL_BITS) - 1); } =20 @@ -628,12 +628,12 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, ui= nt32_t level) } } =20 -/* Given the @gpa, get relevant @slptep. @slpte_level will be the last lev= el +/* Given the @iova, get relevant @slptep. @slpte_level will be the last le= vel * of the translation, can be used for deciding the size of large page. */ -static int vtd_gpa_to_slpte(VTDContextEntry *ce, uint64_t gpa, bool is_wri= te, - uint64_t *slptep, uint32_t *slpte_level, - bool *reads, bool *writes) +static int vtd_iova_to_slpte(VTDContextEntry *ce, uint64_t iova, bool is_w= rite, + uint64_t *slptep, uint32_t *slpte_level, + bool *reads, bool *writes) { dma_addr_t addr =3D vtd_get_slpt_base_from_context(ce); uint32_t level =3D vtd_get_level_from_context_entry(ce); @@ -642,11 +642,11 @@ static int vtd_gpa_to_slpte(VTDContextEntry *ce, uint= 64_t gpa, bool is_write, uint32_t ce_agaw =3D vtd_get_agaw_from_context_entry(ce); uint64_t access_right_check; =20 - /* Check if @gpa is above 2^X-1, where X is the minimum of MGAW in CAP= _REG - * and AW in context-entry. + /* Check if @iova is above 2^X-1, where X is the minimum of MGAW + * in CAP_REG and AW in context-entry. */ - if (gpa & ~((1ULL << MIN(ce_agaw, VTD_MGAW)) - 1)) { - VTD_DPRINTF(GENERAL, "error: gpa 0x%"PRIx64 " exceeds limits", gpa= ); + if (iova & ~((1ULL << MIN(ce_agaw, VTD_MGAW)) - 1)) { + VTD_DPRINTF(GENERAL, "error: iova 0x%"PRIx64 " exceeds limits", io= va); return -VTD_FR_ADDR_BEYOND_MGAW; } =20 @@ -654,13 +654,13 @@ static int vtd_gpa_to_slpte(VTDContextEntry *ce, uint= 64_t gpa, bool is_write, access_right_check =3D is_write ? VTD_SL_W : VTD_SL_R; =20 while (true) { - offset =3D vtd_gpa_level_offset(gpa, level); + offset =3D vtd_iova_level_offset(iova, level); slpte =3D vtd_get_slpte(addr, offset); =20 if (slpte =3D=3D (uint64_t)-1) { VTD_DPRINTF(GENERAL, "error: fail to access second-level pagin= g " - "entry at level %"PRIu32 " for gpa 0x%"PRIx64, - level, gpa); + "entry at level %"PRIu32 " for iova 0x%"PRIx64, + level, iova); if (level =3D=3D vtd_get_level_from_context_entry(ce)) { /* Invalid programming of context-entry */ return -VTD_FR_CONTEXT_ENTRY_INV; @@ -672,8 +672,8 @@ static int vtd_gpa_to_slpte(VTDContextEntry *ce, uint64= _t gpa, bool is_write, *writes =3D (*writes) && (slpte & VTD_SL_W); if (!(slpte & access_right_check)) { VTD_DPRINTF(GENERAL, "error: lack of %s permission for " - "gpa 0x%"PRIx64 " slpte 0x%"PRIx64, - (is_write ? "write" : "read"), gpa, slpte); + "iova 0x%"PRIx64 " slpte 0x%"PRIx64, + (is_write ? "write" : "read"), iova, slpte); return is_write ? -VTD_FR_WRITE : -VTD_FR_READ; } if (vtd_slpte_nonzero_rsvd(slpte, level)) { @@ -827,7 +827,7 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd= _as, PCIBus *bus, /* Try to fetch slpte form IOTLB */ iotlb_entry =3D vtd_lookup_iotlb(s, source_id, addr); if (iotlb_entry) { - VTD_DPRINTF(CACHE, "hit iotlb sid 0x%"PRIx16 " gpa 0x%"PRIx64 + VTD_DPRINTF(CACHE, "hit iotlb sid 0x%"PRIx16 " iova 0x%"PRIx64 " slpte 0x%"PRIx64 " did 0x%"PRIx16, source_id, addr, iotlb_entry->slpte, iotlb_entry->domain_id); slpte =3D iotlb_entry->slpte; @@ -867,8 +867,8 @@ static void vtd_do_iommu_translate(VTDAddressSpace *vtd= _as, PCIBus *bus, cc_entry->context_cache_gen =3D s->context_cache_gen; } =20 - ret_fr =3D vtd_gpa_to_slpte(&ce, addr, is_write, &slpte, &level, - &reads, &writes); + ret_fr =3D vtd_iova_to_slpte(&ce, addr, is_write, &slpte, &level, + &reads, &writes); if (ret_fr) { ret_fr =3D -ret_fr; if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) { @@ -2033,7 +2033,7 @@ static IOMMUTLBEntry vtd_iommu_translate(MemoryRegion= *iommu, hwaddr addr, is_write, &ret); VTD_DPRINTF(MMU, "bus %"PRIu8 " slot %"PRIu8 " func %"PRIu8 " devfn %"PRIu8 - " gpa 0x%"PRIx64 " hpa 0x%"PRIx64, pci_bus_num(vtd_as->bus= ), + " iova 0x%"PRIx64 " hpa 0x%"PRIx64, pci_bus_num(vtd_as->bu= s), VTD_PCI_SLOT(vtd_as->devfn), VTD_PCI_FUNC(vtd_as->devfn), vtd_as->devfn, addr, ret.translated_addr); return ret; --=20 2.7.4