From nobody Tue Jul 15 05:53:57 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1487266901489864.5462991181607; Thu, 16 Feb 2017 09:41:41 -0800 (PST) Received: from localhost ([::1]:48513 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ceQ3n-00022O-8y for importer@patchew.org; Thu, 16 Feb 2017 12:41:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56173) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ceP2Y-0008Ey-8m for qemu-devel@nongnu.org; Thu, 16 Feb 2017 11:36:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ceP2X-0007cK-Gt for qemu-devel@nongnu.org; Thu, 16 Feb 2017 11:36:18 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48525) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ceP2U-0007Zj-BE; Thu, 16 Feb 2017 11:36:14 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ceP2Q-00036x-80; Thu, 16 Feb 2017 16:36:10 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 16 Feb 2017 16:36:03 +0000 Message-Id: <1487262963-11519-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1487262963-11519-1-git-send-email-peter.maydell@linaro.org> References: <1487262963-11519-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH v2 13/13] armv7m: Allow SHCSR writes to change pending and active bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the NVIC SHCSR write behaviour which allows pending and active status of some exceptions to be changed. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- hw/intc/armv7m_nvic.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a8c5a9e..1d34e0d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -755,8 +755,17 @@ static void nvic_writel(NVICState *s, uint32_t offset,= uint32_t value) cpu->env.v7m.ccr =3D value; break; case 0xd24: /* System Handler Control. */ - /* TODO: Real hardware allows you to set/clear the active bits - under some circumstances. We don't implement this. */ + s->vectors[ARMV7M_EXCP_MEM].active =3D (value & (1 << 0)) !=3D 0; + s->vectors[ARMV7M_EXCP_BUS].active =3D (value & (1 << 1)) !=3D 0; + s->vectors[ARMV7M_EXCP_USAGE].active =3D (value & (1 << 3)) !=3D 0; + s->vectors[ARMV7M_EXCP_SVC].active =3D (value & (1 << 7)) !=3D 0; + s->vectors[ARMV7M_EXCP_DEBUG].active =3D (value & (1 << 8)) !=3D 0; + s->vectors[ARMV7M_EXCP_PENDSV].active =3D (value & (1 << 10)) !=3D= 0; + s->vectors[ARMV7M_EXCP_SYSTICK].active =3D (value & (1 << 11)) != =3D 0; + s->vectors[ARMV7M_EXCP_USAGE].pending =3D (value & (1 << 12)) !=3D= 0; + s->vectors[ARMV7M_EXCP_MEM].pending =3D (value & (1 << 13)) !=3D 0; + s->vectors[ARMV7M_EXCP_BUS].pending =3D (value & (1 << 14)) !=3D 0; + s->vectors[ARMV7M_EXCP_SVC].pending =3D (value & (1 << 15)) !=3D 0; s->vectors[ARMV7M_EXCP_MEM].enabled =3D (value & (1 << 16)) !=3D 0; s->vectors[ARMV7M_EXCP_BUS].enabled =3D (value & (1 << 17)) !=3D 0; s->vectors[ARMV7M_EXCP_USAGE].enabled =3D (value & (1 << 18)) !=3D= 0; --=20 2.7.4